1*4882a593SmuzhiyunChrome OS CROS_EC Binding 2*4882a593Smuzhiyun====================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe device tree node which describes the operation of the CROS_EC interface 5*4882a593Smuzhiyunis as follows: 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties : 8*4882a593Smuzhiyun- compatible = "google,cros-ec" 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunOptional properties : 11*4882a593Smuzhiyun- spi-max-frequency : Sets the maximum frequency (in Hz) for SPI bus 12*4882a593Smuzhiyun operation 13*4882a593Smuzhiyun- i2c-max-frequency : Sets the maximum frequency (in Hz) for I2C bus 14*4882a593Smuzhiyun operation 15*4882a593Smuzhiyun- ec-interrupt : Selects the EC interrupt, defined as a GPIO according 16*4882a593Smuzhiyun to the platform 17*4882a593Smuzhiyun- optimise-flash-write : Boolean property - if present then flash blocks 18*4882a593Smuzhiyun containing all 0xff will not be written, since we assume that the EC 19*4882a593Smuzhiyun uses that pattern for erased blocks 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunThe CROS_EC node should appear as a subnode of the interrupt that connects it 22*4882a593Smuzhiyunto the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate 23*4882a593Smuzhiyunthe unit address on that bus. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample 27*4882a593Smuzhiyun======= 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun spi@131b0000 { 30*4882a593Smuzhiyun cros-ec@0 { 31*4882a593Smuzhiyun reg = <0>; 32*4882a593Smuzhiyun compatible = "google,cros-ec"; 33*4882a593Smuzhiyun spi-max-frequency = <5000000>; 34*4882a593Smuzhiyun ec-interrupt = <&gpio 174 1>; 35*4882a593Smuzhiyun optimise-flash-write; 36*4882a593Smuzhiyun status = "disabled"; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39