xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc.
4*4882a593Smuzhiyun * Author: Ben Ho <ben.ho@mediatek.com>
5*4882a593Smuzhiyun *	   Erin Lo <erin.lo@mediatek.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
9*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
10*4882a593Smuzhiyun#include "mt8183.dtsi"
11*4882a593Smuzhiyun#include "mt6358.dtsi"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	aliases {
15*4882a593Smuzhiyun		serial0 = &uart0;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	chosen {
19*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	memory@40000000 {
23*4882a593Smuzhiyun		device_type = "memory";
24*4882a593Smuzhiyun		reg = <0 0x40000000 0 0x80000000>;
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	clk32k: oscillator1 {
28*4882a593Smuzhiyun		compatible = "fixed-clock";
29*4882a593Smuzhiyun		#clock-cells = <0>;
30*4882a593Smuzhiyun		clock-frequency = <32768>;
31*4882a593Smuzhiyun		clock-output-names = "clk32k";
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	it6505_pp18_reg: regulator0 {
35*4882a593Smuzhiyun		compatible = "regulator-fixed";
36*4882a593Smuzhiyun		regulator-name = "it6505_pp18";
37*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
38*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
39*4882a593Smuzhiyun		gpio = <&pio 178 0>;
40*4882a593Smuzhiyun		enable-active-high;
41*4882a593Smuzhiyun	};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun	lcd_pp3300: regulator1 {
44*4882a593Smuzhiyun		compatible = "regulator-fixed";
45*4882a593Smuzhiyun		regulator-name = "lcd_pp3300";
46*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
47*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
48*4882a593Smuzhiyun		regulator-always-on;
49*4882a593Smuzhiyun		regulator-boot-on;
50*4882a593Smuzhiyun	};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	bl_pp5000: regulator2 {
53*4882a593Smuzhiyun		compatible = "regulator-fixed";
54*4882a593Smuzhiyun		regulator-name = "bl_pp5000";
55*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
56*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
57*4882a593Smuzhiyun		regulator-always-on;
58*4882a593Smuzhiyun		regulator-boot-on;
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun	mmc1_fixed_power: regulator3 {
62*4882a593Smuzhiyun		compatible = "regulator-fixed";
63*4882a593Smuzhiyun		regulator-name = "mmc1_power";
64*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
65*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	mmc1_fixed_io: regulator4 {
69*4882a593Smuzhiyun		compatible = "regulator-fixed";
70*4882a593Smuzhiyun		regulator-name = "mmc1_io";
71*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
72*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun	pp1800_alw: regulator5 {
76*4882a593Smuzhiyun		compatible = "regulator-fixed";
77*4882a593Smuzhiyun		regulator-name = "pp1800_alw";
78*4882a593Smuzhiyun		regulator-always-on;
79*4882a593Smuzhiyun		regulator-boot-on;
80*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
81*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
82*4882a593Smuzhiyun	};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun	pp3300_alw: regulator6 {
85*4882a593Smuzhiyun		compatible = "regulator-fixed";
86*4882a593Smuzhiyun		regulator-name = "pp3300_alw";
87*4882a593Smuzhiyun		regulator-always-on;
88*4882a593Smuzhiyun		regulator-boot-on;
89*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
90*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
91*4882a593Smuzhiyun	};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun	reserved_memory: reserved-memory {
94*4882a593Smuzhiyun		#address-cells = <2>;
95*4882a593Smuzhiyun		#size-cells = <2>;
96*4882a593Smuzhiyun		ranges;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun		scp_mem_reserved: scp_mem_region {
99*4882a593Smuzhiyun			compatible = "shared-dma-pool";
100*4882a593Smuzhiyun			reg = <0 0x50000000 0 0x2900000>;
101*4882a593Smuzhiyun			no-map;
102*4882a593Smuzhiyun		};
103*4882a593Smuzhiyun	};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun	max98357a: codec0 {
106*4882a593Smuzhiyun		compatible = "maxim,max98357a";
107*4882a593Smuzhiyun		sdmode-gpios = <&pio 175 0>;
108*4882a593Smuzhiyun	};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun	btsco: codec1 {
111*4882a593Smuzhiyun		compatible = "linux,bt-sco";
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun	wifi_pwrseq: wifi-pwrseq {
115*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
116*4882a593Smuzhiyun		pinctrl-names = "default";
117*4882a593Smuzhiyun		pinctrl-0 = <&wifi_pins_pwrseq>;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun		/* Toggle WIFI_ENABLE to reset the chip. */
120*4882a593Smuzhiyun		reset-gpios = <&pio 119 1>;
121*4882a593Smuzhiyun	};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun	wifi_wakeup: wifi-wakeup {
124*4882a593Smuzhiyun		compatible = "gpio-keys";
125*4882a593Smuzhiyun		pinctrl-names = "default";
126*4882a593Smuzhiyun		pinctrl-0 = <&wifi_pins_wakeup>;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun		wowlan {
129*4882a593Smuzhiyun			label = "Wake on WiFi";
130*4882a593Smuzhiyun			gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
131*4882a593Smuzhiyun			linux,code = <KEY_WAKEUP>;
132*4882a593Smuzhiyun			wakeup-source;
133*4882a593Smuzhiyun		};
134*4882a593Smuzhiyun	};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun	tboard_thermistor1: thermal-sensor1 {
137*4882a593Smuzhiyun		compatible = "generic-adc-thermal";
138*4882a593Smuzhiyun		#thermal-sensor-cells = <0>;
139*4882a593Smuzhiyun		io-channels = <&auxadc 0>;
140*4882a593Smuzhiyun		io-channel-names = "sensor-channel";
141*4882a593Smuzhiyun		temperature-lookup-table = <    (-5000) 4241
142*4882a593Smuzhiyun						0 4063
143*4882a593Smuzhiyun						5000 3856
144*4882a593Smuzhiyun						10000 3621
145*4882a593Smuzhiyun						15000 3364
146*4882a593Smuzhiyun						20000 3091
147*4882a593Smuzhiyun						25000 2810
148*4882a593Smuzhiyun						30000 2526
149*4882a593Smuzhiyun						35000 2247
150*4882a593Smuzhiyun						40000 1982
151*4882a593Smuzhiyun						45000 1734
152*4882a593Smuzhiyun						50000 1507
153*4882a593Smuzhiyun						55000 1305
154*4882a593Smuzhiyun						60000 1122
155*4882a593Smuzhiyun						65000 964
156*4882a593Smuzhiyun						70000 827
157*4882a593Smuzhiyun						75000 710
158*4882a593Smuzhiyun						80000 606
159*4882a593Smuzhiyun						85000 519
160*4882a593Smuzhiyun						90000 445
161*4882a593Smuzhiyun						95000 382
162*4882a593Smuzhiyun						100000 330
163*4882a593Smuzhiyun						105000 284
164*4882a593Smuzhiyun						110000 245
165*4882a593Smuzhiyun						115000 213
166*4882a593Smuzhiyun						120000 183
167*4882a593Smuzhiyun						125000 161>;
168*4882a593Smuzhiyun	};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun	tboard_thermistor2: thermal-sensor2 {
171*4882a593Smuzhiyun		compatible = "generic-adc-thermal";
172*4882a593Smuzhiyun		#thermal-sensor-cells = <0>;
173*4882a593Smuzhiyun		io-channels = <&auxadc 1>;
174*4882a593Smuzhiyun		io-channel-names = "sensor-channel";
175*4882a593Smuzhiyun		temperature-lookup-table = <    (-5000) 4241
176*4882a593Smuzhiyun						0 4063
177*4882a593Smuzhiyun						5000 3856
178*4882a593Smuzhiyun						10000 3621
179*4882a593Smuzhiyun						15000 3364
180*4882a593Smuzhiyun						20000 3091
181*4882a593Smuzhiyun						25000 2810
182*4882a593Smuzhiyun						30000 2526
183*4882a593Smuzhiyun						35000 2247
184*4882a593Smuzhiyun						40000 1982
185*4882a593Smuzhiyun						45000 1734
186*4882a593Smuzhiyun						50000 1507
187*4882a593Smuzhiyun						55000 1305
188*4882a593Smuzhiyun						60000 1122
189*4882a593Smuzhiyun						65000 964
190*4882a593Smuzhiyun						70000 827
191*4882a593Smuzhiyun						75000 710
192*4882a593Smuzhiyun						80000 606
193*4882a593Smuzhiyun						85000 519
194*4882a593Smuzhiyun						90000 445
195*4882a593Smuzhiyun						95000 382
196*4882a593Smuzhiyun						100000 330
197*4882a593Smuzhiyun						105000 284
198*4882a593Smuzhiyun						110000 245
199*4882a593Smuzhiyun						115000 213
200*4882a593Smuzhiyun						120000 183
201*4882a593Smuzhiyun						125000 161>;
202*4882a593Smuzhiyun	};
203*4882a593Smuzhiyun};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun&auxadc {
206*4882a593Smuzhiyun	status = "okay";
207*4882a593Smuzhiyun};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun&cpu0 {
210*4882a593Smuzhiyun	proc-supply = <&mt6358_vproc12_reg>;
211*4882a593Smuzhiyun};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun&cpu1 {
214*4882a593Smuzhiyun	proc-supply = <&mt6358_vproc12_reg>;
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&cpu2 {
218*4882a593Smuzhiyun	proc-supply = <&mt6358_vproc12_reg>;
219*4882a593Smuzhiyun};
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun&cpu3 {
222*4882a593Smuzhiyun	proc-supply = <&mt6358_vproc12_reg>;
223*4882a593Smuzhiyun};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun&cpu4 {
226*4882a593Smuzhiyun	proc-supply = <&mt6358_vproc11_reg>;
227*4882a593Smuzhiyun};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun&cpu5 {
230*4882a593Smuzhiyun	proc-supply = <&mt6358_vproc11_reg>;
231*4882a593Smuzhiyun};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun&cpu6 {
234*4882a593Smuzhiyun	proc-supply = <&mt6358_vproc11_reg>;
235*4882a593Smuzhiyun};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun&cpu7 {
238*4882a593Smuzhiyun	proc-supply = <&mt6358_vproc11_reg>;
239*4882a593Smuzhiyun};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun&i2c0 {
242*4882a593Smuzhiyun	pinctrl-names = "default";
243*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins>;
244*4882a593Smuzhiyun	status = "okay";
245*4882a593Smuzhiyun	clock-frequency = <400000>;
246*4882a593Smuzhiyun	#address-cells = <1>;
247*4882a593Smuzhiyun	#size-cells = <0>;
248*4882a593Smuzhiyun};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun&i2c1 {
251*4882a593Smuzhiyun	pinctrl-names = "default";
252*4882a593Smuzhiyun	pinctrl-0 = <&i2c1_pins>;
253*4882a593Smuzhiyun	status = "okay";
254*4882a593Smuzhiyun	clock-frequency = <100000>;
255*4882a593Smuzhiyun};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun&i2c3 {
258*4882a593Smuzhiyun	pinctrl-names = "default";
259*4882a593Smuzhiyun	pinctrl-0 = <&i2c3_pins>;
260*4882a593Smuzhiyun	status = "okay";
261*4882a593Smuzhiyun	clock-frequency = <100000>;
262*4882a593Smuzhiyun	#address-cells = <1>;
263*4882a593Smuzhiyun	#size-cells = <0>;
264*4882a593Smuzhiyun};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun&i2c5 {
267*4882a593Smuzhiyun	pinctrl-names = "default";
268*4882a593Smuzhiyun	pinctrl-0 = <&i2c5_pins>;
269*4882a593Smuzhiyun	status = "okay";
270*4882a593Smuzhiyun	clock-frequency = <100000>;
271*4882a593Smuzhiyun	#address-cells = <1>;
272*4882a593Smuzhiyun	#size-cells = <0>;
273*4882a593Smuzhiyun};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun&i2c6 {
276*4882a593Smuzhiyun	pinctrl-names = "default";
277*4882a593Smuzhiyun	pinctrl-0 = <&i2c6_pins>;
278*4882a593Smuzhiyun	status = "okay";
279*4882a593Smuzhiyun	clock-frequency = <100000>;
280*4882a593Smuzhiyun};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun&mmc0 {
283*4882a593Smuzhiyun	status = "okay";
284*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
285*4882a593Smuzhiyun	pinctrl-0 = <&mmc0_pins_default>;
286*4882a593Smuzhiyun	pinctrl-1 = <&mmc0_pins_uhs>;
287*4882a593Smuzhiyun	bus-width = <8>;
288*4882a593Smuzhiyun	max-frequency = <200000000>;
289*4882a593Smuzhiyun	cap-mmc-highspeed;
290*4882a593Smuzhiyun	mmc-hs200-1_8v;
291*4882a593Smuzhiyun	mmc-hs400-1_8v;
292*4882a593Smuzhiyun	cap-mmc-hw-reset;
293*4882a593Smuzhiyun	no-sdio;
294*4882a593Smuzhiyun	no-sd;
295*4882a593Smuzhiyun	hs400-ds-delay = <0x12814>;
296*4882a593Smuzhiyun	vmmc-supply = <&mt6358_vemc_reg>;
297*4882a593Smuzhiyun	vqmmc-supply = <&mt6358_vio18_reg>;
298*4882a593Smuzhiyun	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
299*4882a593Smuzhiyun	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
300*4882a593Smuzhiyun	non-removable;
301*4882a593Smuzhiyun};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun&mmc1 {
304*4882a593Smuzhiyun	status = "okay";
305*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
306*4882a593Smuzhiyun	pinctrl-0 = <&mmc1_pins_default>;
307*4882a593Smuzhiyun	pinctrl-1 = <&mmc1_pins_uhs>;
308*4882a593Smuzhiyun	vmmc-supply = <&mmc1_fixed_power>;
309*4882a593Smuzhiyun	vqmmc-supply = <&mmc1_fixed_io>;
310*4882a593Smuzhiyun	mmc-pwrseq = <&wifi_pwrseq>;
311*4882a593Smuzhiyun	bus-width = <4>;
312*4882a593Smuzhiyun	max-frequency = <200000000>;
313*4882a593Smuzhiyun	drv-type = <2>;
314*4882a593Smuzhiyun	cap-sd-highspeed;
315*4882a593Smuzhiyun	sd-uhs-sdr50;
316*4882a593Smuzhiyun	sd-uhs-sdr104;
317*4882a593Smuzhiyun	keep-power-in-suspend;
318*4882a593Smuzhiyun	enable-sdio-wakeup;
319*4882a593Smuzhiyun	cap-sdio-irq;
320*4882a593Smuzhiyun	non-removable;
321*4882a593Smuzhiyun	no-mmc;
322*4882a593Smuzhiyun	no-sd;
323*4882a593Smuzhiyun	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
324*4882a593Smuzhiyun	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
325*4882a593Smuzhiyun	#address-cells = <1>;
326*4882a593Smuzhiyun	#size-cells = <0>;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun	qca_wifi: qca-wifi@1 {
329*4882a593Smuzhiyun		compatible = "qcom,ath10k";
330*4882a593Smuzhiyun		reg = <1>;
331*4882a593Smuzhiyun	};
332*4882a593Smuzhiyun};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun&mt6358_vdram2_reg {
335*4882a593Smuzhiyun	regulator-always-on;
336*4882a593Smuzhiyun};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun&mt6358codec {
339*4882a593Smuzhiyun	Avdd-supply = <&mt6358_vaud28_reg>;
340*4882a593Smuzhiyun};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun&mt6358_vsim1_reg {
343*4882a593Smuzhiyun	regulator-min-microvolt = <2700000>;
344*4882a593Smuzhiyun	regulator-max-microvolt = <2700000>;
345*4882a593Smuzhiyun};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun&mt6358_vsim2_reg {
348*4882a593Smuzhiyun	regulator-min-microvolt = <2700000>;
349*4882a593Smuzhiyun	regulator-max-microvolt = <2700000>;
350*4882a593Smuzhiyun};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun&pio {
353*4882a593Smuzhiyun	bt_pins: bt-pins {
354*4882a593Smuzhiyun		pins_bt_en {
355*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
356*4882a593Smuzhiyun			output-low;
357*4882a593Smuzhiyun		};
358*4882a593Smuzhiyun	};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun	ec_ap_int_odl: ec_ap_int_odl {
361*4882a593Smuzhiyun		pins1 {
362*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
363*4882a593Smuzhiyun			input-enable;
364*4882a593Smuzhiyun			bias-pull-up;
365*4882a593Smuzhiyun		};
366*4882a593Smuzhiyun	};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun	h1_int_od_l: h1_int_od_l {
369*4882a593Smuzhiyun		pins1 {
370*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
371*4882a593Smuzhiyun			input-enable;
372*4882a593Smuzhiyun		};
373*4882a593Smuzhiyun	};
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun	i2c0_pins: i2c0 {
376*4882a593Smuzhiyun		pins_bus {
377*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
378*4882a593Smuzhiyun				 <PINMUX_GPIO83__FUNC_SCL0>;
379*4882a593Smuzhiyun			mediatek,pull-up-adv = <3>;
380*4882a593Smuzhiyun			mediatek,drive-strength-adv = <00>;
381*4882a593Smuzhiyun		};
382*4882a593Smuzhiyun	};
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun	i2c1_pins: i2c1 {
385*4882a593Smuzhiyun		pins_bus {
386*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
387*4882a593Smuzhiyun				 <PINMUX_GPIO84__FUNC_SCL1>;
388*4882a593Smuzhiyun			mediatek,pull-up-adv = <3>;
389*4882a593Smuzhiyun			mediatek,drive-strength-adv = <00>;
390*4882a593Smuzhiyun		};
391*4882a593Smuzhiyun	};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun	i2c2_pins: i2c2 {
394*4882a593Smuzhiyun		pins_bus {
395*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
396*4882a593Smuzhiyun				 <PINMUX_GPIO104__FUNC_SDA2>;
397*4882a593Smuzhiyun			bias-disable;
398*4882a593Smuzhiyun			mediatek,drive-strength-adv = <00>;
399*4882a593Smuzhiyun		};
400*4882a593Smuzhiyun	};
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun	i2c3_pins: i2c3 {
403*4882a593Smuzhiyun		pins_bus {
404*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
405*4882a593Smuzhiyun				 <PINMUX_GPIO51__FUNC_SDA3>;
406*4882a593Smuzhiyun			mediatek,pull-up-adv = <3>;
407*4882a593Smuzhiyun			mediatek,drive-strength-adv = <00>;
408*4882a593Smuzhiyun		};
409*4882a593Smuzhiyun	};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun	i2c4_pins: i2c4 {
412*4882a593Smuzhiyun		pins_bus {
413*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
414*4882a593Smuzhiyun				 <PINMUX_GPIO106__FUNC_SDA4>;
415*4882a593Smuzhiyun			bias-disable;
416*4882a593Smuzhiyun			mediatek,drive-strength-adv = <00>;
417*4882a593Smuzhiyun		};
418*4882a593Smuzhiyun	};
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun	i2c5_pins: i2c5 {
421*4882a593Smuzhiyun		pins_bus {
422*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
423*4882a593Smuzhiyun				 <PINMUX_GPIO49__FUNC_SDA5>;
424*4882a593Smuzhiyun			mediatek,pull-up-adv = <3>;
425*4882a593Smuzhiyun			mediatek,drive-strength-adv = <00>;
426*4882a593Smuzhiyun		};
427*4882a593Smuzhiyun	};
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun	i2c6_pins: i2c6 {
430*4882a593Smuzhiyun		pins_bus {
431*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
432*4882a593Smuzhiyun				 <PINMUX_GPIO12__FUNC_SDA6>;
433*4882a593Smuzhiyun			bias-disable;
434*4882a593Smuzhiyun		};
435*4882a593Smuzhiyun	};
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun	mmc0_pins_default: mmc0-pins-default {
438*4882a593Smuzhiyun		pins_cmd_dat {
439*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
440*4882a593Smuzhiyun				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
441*4882a593Smuzhiyun				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
442*4882a593Smuzhiyun				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
443*4882a593Smuzhiyun				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
444*4882a593Smuzhiyun				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
445*4882a593Smuzhiyun				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
446*4882a593Smuzhiyun				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
447*4882a593Smuzhiyun				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
448*4882a593Smuzhiyun			input-enable;
449*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_14mA>;
450*4882a593Smuzhiyun			mediatek,pull-up-adv = <01>;
451*4882a593Smuzhiyun		};
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun		pins_clk {
454*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
455*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_14mA>;
456*4882a593Smuzhiyun			mediatek,pull-down-adv = <10>;
457*4882a593Smuzhiyun		};
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun		pins_rst {
460*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
461*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_14mA>;
462*4882a593Smuzhiyun			mediatek,pull-down-adv = <01>;
463*4882a593Smuzhiyun		};
464*4882a593Smuzhiyun	};
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun	mmc0_pins_uhs: mmc0-pins-uhs {
467*4882a593Smuzhiyun		pins_cmd_dat {
468*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
469*4882a593Smuzhiyun				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
470*4882a593Smuzhiyun				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
471*4882a593Smuzhiyun				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
472*4882a593Smuzhiyun				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
473*4882a593Smuzhiyun				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
474*4882a593Smuzhiyun				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
475*4882a593Smuzhiyun				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
476*4882a593Smuzhiyun				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
477*4882a593Smuzhiyun			input-enable;
478*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_14mA>;
479*4882a593Smuzhiyun			mediatek,pull-up-adv = <01>;
480*4882a593Smuzhiyun		};
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun		pins_clk {
483*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
484*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_14mA>;
485*4882a593Smuzhiyun			mediatek,pull-down-adv = <10>;
486*4882a593Smuzhiyun		};
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun		pins_ds {
489*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
490*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_14mA>;
491*4882a593Smuzhiyun			mediatek,pull-down-adv = <10>;
492*4882a593Smuzhiyun		};
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun		pins_rst {
495*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
496*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_14mA>;
497*4882a593Smuzhiyun			mediatek,pull-up-adv = <01>;
498*4882a593Smuzhiyun		};
499*4882a593Smuzhiyun	};
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun	mmc1_pins_default: mmc1-pins-default {
502*4882a593Smuzhiyun		pins_cmd_dat {
503*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
504*4882a593Smuzhiyun				 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
505*4882a593Smuzhiyun				 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
506*4882a593Smuzhiyun				 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
507*4882a593Smuzhiyun				 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
508*4882a593Smuzhiyun			input-enable;
509*4882a593Smuzhiyun			mediatek,pull-up-adv = <10>;
510*4882a593Smuzhiyun		};
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun		pins_clk {
513*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
514*4882a593Smuzhiyun			input-enable;
515*4882a593Smuzhiyun			mediatek,pull-down-adv = <10>;
516*4882a593Smuzhiyun		};
517*4882a593Smuzhiyun	};
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun	mmc1_pins_uhs: mmc1-pins-uhs {
520*4882a593Smuzhiyun		pins_cmd_dat {
521*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
522*4882a593Smuzhiyun				 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
523*4882a593Smuzhiyun				 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
524*4882a593Smuzhiyun				 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
525*4882a593Smuzhiyun				 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
526*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_6mA>;
527*4882a593Smuzhiyun			input-enable;
528*4882a593Smuzhiyun			mediatek,pull-up-adv = <10>;
529*4882a593Smuzhiyun		};
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun		pins_clk {
532*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
533*4882a593Smuzhiyun			drive-strength = <MTK_DRIVE_8mA>;
534*4882a593Smuzhiyun			mediatek,pull-down-adv = <10>;
535*4882a593Smuzhiyun			input-enable;
536*4882a593Smuzhiyun		};
537*4882a593Smuzhiyun	};
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun	scp_pins: scp {
540*4882a593Smuzhiyun		pins_scp_uart {
541*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
542*4882a593Smuzhiyun				 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
543*4882a593Smuzhiyun		};
544*4882a593Smuzhiyun	};
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun	spi0_pins: spi0 {
547*4882a593Smuzhiyun		pins_spi{
548*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
549*4882a593Smuzhiyun				 <PINMUX_GPIO86__FUNC_GPIO86>,
550*4882a593Smuzhiyun				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
551*4882a593Smuzhiyun				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
552*4882a593Smuzhiyun			bias-disable;
553*4882a593Smuzhiyun		};
554*4882a593Smuzhiyun	};
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun	spi1_pins: spi1 {
557*4882a593Smuzhiyun		pins_spi{
558*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
559*4882a593Smuzhiyun				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
560*4882a593Smuzhiyun				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
561*4882a593Smuzhiyun				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
562*4882a593Smuzhiyun			bias-disable;
563*4882a593Smuzhiyun		};
564*4882a593Smuzhiyun	};
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun	spi2_pins: spi2 {
567*4882a593Smuzhiyun		pins_spi{
568*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
569*4882a593Smuzhiyun				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
570*4882a593Smuzhiyun				 <PINMUX_GPIO2__FUNC_SPI2_CLK>;
571*4882a593Smuzhiyun			bias-disable;
572*4882a593Smuzhiyun		};
573*4882a593Smuzhiyun		pins_spi_mi {
574*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
575*4882a593Smuzhiyun			mediatek,pull-down-adv = <00>;
576*4882a593Smuzhiyun		};
577*4882a593Smuzhiyun	};
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun	spi3_pins: spi3 {
580*4882a593Smuzhiyun		pins_spi{
581*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
582*4882a593Smuzhiyun				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
583*4882a593Smuzhiyun				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
584*4882a593Smuzhiyun				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
585*4882a593Smuzhiyun			bias-disable;
586*4882a593Smuzhiyun		};
587*4882a593Smuzhiyun	};
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun	spi4_pins: spi4 {
590*4882a593Smuzhiyun		pins_spi{
591*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
592*4882a593Smuzhiyun				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
593*4882a593Smuzhiyun				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
594*4882a593Smuzhiyun				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
595*4882a593Smuzhiyun			bias-disable;
596*4882a593Smuzhiyun		};
597*4882a593Smuzhiyun	};
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun	spi5_pins: spi5 {
600*4882a593Smuzhiyun		pins_spi{
601*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
602*4882a593Smuzhiyun				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
603*4882a593Smuzhiyun				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
604*4882a593Smuzhiyun				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
605*4882a593Smuzhiyun			bias-disable;
606*4882a593Smuzhiyun		};
607*4882a593Smuzhiyun	};
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun	uart0_pins_default: uart0-pins-default {
610*4882a593Smuzhiyun		pins_rx {
611*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
612*4882a593Smuzhiyun			input-enable;
613*4882a593Smuzhiyun			bias-pull-up;
614*4882a593Smuzhiyun		};
615*4882a593Smuzhiyun		pins_tx {
616*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
617*4882a593Smuzhiyun		};
618*4882a593Smuzhiyun	};
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun	uart1_pins_default: uart1-pins-default {
621*4882a593Smuzhiyun		pins_rx {
622*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
623*4882a593Smuzhiyun			input-enable;
624*4882a593Smuzhiyun			bias-pull-up;
625*4882a593Smuzhiyun		};
626*4882a593Smuzhiyun		pins_tx {
627*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
628*4882a593Smuzhiyun		};
629*4882a593Smuzhiyun		pins_rts {
630*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
631*4882a593Smuzhiyun			output-enable;
632*4882a593Smuzhiyun		};
633*4882a593Smuzhiyun		pins_cts {
634*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
635*4882a593Smuzhiyun			input-enable;
636*4882a593Smuzhiyun		};
637*4882a593Smuzhiyun	};
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun	uart1_pins_sleep: uart1-pins-sleep {
640*4882a593Smuzhiyun		pins_rx {
641*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
642*4882a593Smuzhiyun			input-enable;
643*4882a593Smuzhiyun			bias-pull-up;
644*4882a593Smuzhiyun		};
645*4882a593Smuzhiyun		pins_tx {
646*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
647*4882a593Smuzhiyun		};
648*4882a593Smuzhiyun		pins_rts {
649*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
650*4882a593Smuzhiyun			output-enable;
651*4882a593Smuzhiyun		};
652*4882a593Smuzhiyun		pins_cts {
653*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
654*4882a593Smuzhiyun			input-enable;
655*4882a593Smuzhiyun		};
656*4882a593Smuzhiyun	};
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun	wifi_pins_pwrseq: wifi-pins-pwrseq {
659*4882a593Smuzhiyun		pins_wifi_enable {
660*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
661*4882a593Smuzhiyun			output-low;
662*4882a593Smuzhiyun		};
663*4882a593Smuzhiyun	};
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun	wifi_pins_wakeup: wifi-pins-wakeup {
666*4882a593Smuzhiyun		pins_wifi_wakeup {
667*4882a593Smuzhiyun			pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
668*4882a593Smuzhiyun			input-enable;
669*4882a593Smuzhiyun		};
670*4882a593Smuzhiyun	};
671*4882a593Smuzhiyun};
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun&scp {
674*4882a593Smuzhiyun	status = "okay";
675*4882a593Smuzhiyun	pinctrl-names = "default";
676*4882a593Smuzhiyun	pinctrl-0 = <&scp_pins>;
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun	cros_ec {
679*4882a593Smuzhiyun		compatible = "google,cros-ec-rpmsg";
680*4882a593Smuzhiyun		mtk,rpmsg-name = "cros-ec-rpmsg";
681*4882a593Smuzhiyun	};
682*4882a593Smuzhiyun};
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun&soc_data {
685*4882a593Smuzhiyun	status = "okay";
686*4882a593Smuzhiyun};
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun&spi0 {
689*4882a593Smuzhiyun	pinctrl-names = "default";
690*4882a593Smuzhiyun	pinctrl-0 = <&spi0_pins>;
691*4882a593Smuzhiyun	mediatek,pad-select = <0>;
692*4882a593Smuzhiyun	status = "okay";
693*4882a593Smuzhiyun	cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun	cr50@0 {
696*4882a593Smuzhiyun		compatible = "google,cr50";
697*4882a593Smuzhiyun		reg = <0>;
698*4882a593Smuzhiyun		spi-max-frequency = <1000000>;
699*4882a593Smuzhiyun		pinctrl-names = "default";
700*4882a593Smuzhiyun		pinctrl-0 = <&h1_int_od_l>;
701*4882a593Smuzhiyun		interrupt-parent = <&pio>;
702*4882a593Smuzhiyun		interrupts = <153 IRQ_TYPE_EDGE_RISING>;
703*4882a593Smuzhiyun	};
704*4882a593Smuzhiyun};
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun&spi1 {
707*4882a593Smuzhiyun	pinctrl-names = "default";
708*4882a593Smuzhiyun	pinctrl-0 = <&spi1_pins>;
709*4882a593Smuzhiyun	mediatek,pad-select = <0>;
710*4882a593Smuzhiyun	status = "okay";
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun	w25q64dw: spi-flash@0 {
713*4882a593Smuzhiyun		compatible = "winbond,w25q64dw", "jedec,spi-nor";
714*4882a593Smuzhiyun		reg = <0>;
715*4882a593Smuzhiyun		spi-max-frequency = <25000000>;
716*4882a593Smuzhiyun	};
717*4882a593Smuzhiyun};
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun&spi2 {
720*4882a593Smuzhiyun	pinctrl-names = "default";
721*4882a593Smuzhiyun	pinctrl-0 = <&spi2_pins>;
722*4882a593Smuzhiyun	mediatek,pad-select = <0>;
723*4882a593Smuzhiyun	status = "okay";
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun	cros_ec: cros-ec@0 {
726*4882a593Smuzhiyun		compatible = "google,cros-ec-spi";
727*4882a593Smuzhiyun		reg = <0>;
728*4882a593Smuzhiyun		spi-max-frequency = <3000000>;
729*4882a593Smuzhiyun		interrupt-parent = <&pio>;
730*4882a593Smuzhiyun		interrupts = <151 IRQ_TYPE_LEVEL_LOW>;
731*4882a593Smuzhiyun		pinctrl-names = "default";
732*4882a593Smuzhiyun		pinctrl-0 = <&ec_ap_int_odl>;
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun		i2c_tunnel: i2c-tunnel {
735*4882a593Smuzhiyun			compatible = "google,cros-ec-i2c-tunnel";
736*4882a593Smuzhiyun			google,remote-bus = <1>;
737*4882a593Smuzhiyun			#address-cells = <1>;
738*4882a593Smuzhiyun			#size-cells = <0>;
739*4882a593Smuzhiyun		};
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun		usbc_extcon: extcon0 {
742*4882a593Smuzhiyun			compatible = "google,extcon-usbc-cros-ec";
743*4882a593Smuzhiyun			google,usb-port-id = <0>;
744*4882a593Smuzhiyun		};
745*4882a593Smuzhiyun	};
746*4882a593Smuzhiyun};
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun&spi3 {
749*4882a593Smuzhiyun	pinctrl-names = "default";
750*4882a593Smuzhiyun	pinctrl-0 = <&spi3_pins>;
751*4882a593Smuzhiyun	mediatek,pad-select = <0>;
752*4882a593Smuzhiyun	status = "disabled";
753*4882a593Smuzhiyun};
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun&spi4 {
756*4882a593Smuzhiyun	pinctrl-names = "default";
757*4882a593Smuzhiyun	pinctrl-0 = <&spi4_pins>;
758*4882a593Smuzhiyun	mediatek,pad-select = <0>;
759*4882a593Smuzhiyun	status = "disabled";
760*4882a593Smuzhiyun};
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun&spi5 {
763*4882a593Smuzhiyun	pinctrl-names = "default";
764*4882a593Smuzhiyun	pinctrl-0 = <&spi5_pins>;
765*4882a593Smuzhiyun	mediatek,pad-select = <0>;
766*4882a593Smuzhiyun	status = "disabled";
767*4882a593Smuzhiyun};
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun&ssusb {
770*4882a593Smuzhiyun	dr_mode = "host";
771*4882a593Smuzhiyun	wakeup-source;
772*4882a593Smuzhiyun	vusb33-supply = <&mt6358_vusb_reg>;
773*4882a593Smuzhiyun	status = "okay";
774*4882a593Smuzhiyun};
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun&u3phy {
777*4882a593Smuzhiyun	status = "okay";
778*4882a593Smuzhiyun};
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun&uart0 {
781*4882a593Smuzhiyun	pinctrl-names = "default";
782*4882a593Smuzhiyun	pinctrl-0 = <&uart0_pins_default>;
783*4882a593Smuzhiyun	status = "okay";
784*4882a593Smuzhiyun};
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun&uart1 {
787*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
788*4882a593Smuzhiyun	pinctrl-0 = <&uart1_pins_default>;
789*4882a593Smuzhiyun	pinctrl-1 = <&uart1_pins_sleep>;
790*4882a593Smuzhiyun	status = "okay";
791*4882a593Smuzhiyun	interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
792*4882a593Smuzhiyun			      <&pio 121 IRQ_TYPE_EDGE_FALLING>;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun	bluetooth: bluetooth {
795*4882a593Smuzhiyun		pinctrl-names = "default";
796*4882a593Smuzhiyun		pinctrl-0 = <&bt_pins>;
797*4882a593Smuzhiyun		status = "okay";
798*4882a593Smuzhiyun		compatible = "qcom,qca6174-bt";
799*4882a593Smuzhiyun		enable-gpios = <&pio 120 0>;
800*4882a593Smuzhiyun		clocks = <&clk32k>;
801*4882a593Smuzhiyun		firmware-name = "nvm_00440302_i2s.bin";
802*4882a593Smuzhiyun	};
803*4882a593Smuzhiyun};
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun&usb_host {
806*4882a593Smuzhiyun	#address-cells = <1>;
807*4882a593Smuzhiyun	#size-cells = <0>;
808*4882a593Smuzhiyun	vusb33-supply = <&mt6358_vusb_reg>;
809*4882a593Smuzhiyun	status = "okay";
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun	hub@1 {
812*4882a593Smuzhiyun		compatible = "usb5e3,610";
813*4882a593Smuzhiyun		reg = <1>;
814*4882a593Smuzhiyun	};
815*4882a593Smuzhiyun};
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun#include <arm/cros-ec-keyboard.dtsi>
818*4882a593Smuzhiyun#include <arm/cros-ec-sbs.dtsi>
819