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/OK3568_Linux_fs/u-boot/drivers/clk/
H A Dclk_scmi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2020 Linaro Limited
6 #include <clk-uclass.h>
12 static int scmi_clk_gate(struct clk *clk, int enable) in scmi_clk_gate() argument
15 .clock_id = clk->id, in scmi_clk_gate()
18 struct scmi_clk_state_out out; in scmi_clk_gate() local
21 in, out); in scmi_clk_gate()
24 ret = devm_scmi_process_msg(clk->dev->parent, &msg); in scmi_clk_gate()
28 return scmi_to_linux_errno(out.status); in scmi_clk_gate()
31 static int scmi_clk_enable(struct clk *clk) in scmi_clk_enable() argument
[all …]
/OK3568_Linux_fs/kernel/kernel/time/
H A Dposix-clock.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/posix-clock.h>
15 #include "posix-timers.h"
22 struct posix_clock *clk = fp->private_data; in get_posix_clock() local
24 down_read(&clk->rwsem); in get_posix_clock()
26 if (!clk->zombie) in get_posix_clock()
27 return clk; in get_posix_clock()
29 up_read(&clk->rwsem); in get_posix_clock()
34 static void put_posix_clock(struct posix_clock *clk) in put_posix_clock() argument
36 up_read(&clk->rwsem); in put_posix_clock()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dmcp77.c19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 read_div(struct mcp77_clk *clk) in read_div() argument
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) in read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
83 struct mcp77_clk *clk = mcp77_clk(base); in mcp77_clk_read() local
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
91 return device->crystal; in mcp77_clk_read()
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H A Dnv50.c19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
32 read_div(struct nv50_clk *clk) in read_div() argument
34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
52 read_pll_src(struct nv50_clk *clk, u32 base) in read_pll_src() argument
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
60 switch (device->chipset) { in read_pll_src()
103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
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H A Dgt215.c19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 read_vco(struct gt215_clk *clk, int idx) in read_vco() argument
45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
52 return read_pll(clk, 0x41, 0x00e820); in read_vco()
54 return read_pll(clk, 0x42, 0x00e8a0); in read_vco()
61 read_clk(struct gt215_clk *clk, int idx, bool ignore_en) in read_clk() argument
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Drockchip,clk-out.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Clock Out Control Module Binding
10 - Sugar Zhang <sugar.zhang@rock-chips.com>
13 This add support switch for clk-bidirection which located
14 at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
16 which hard to addressed in one single clk driver. so, we add
20 clk usage (avoid high freq glitch), we set all clk out as disabled
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/OK3568_Linux_fs/kernel/sound/soc/sh/rcar/
H A Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
7 #include <linux/clk-provider.h>
29 struct clk *clk[CLKMAX]; member
30 struct clk *clkout[CLKOUTMAX];
49 ((pos) = adg->clk[i]); \
54 ((pos) = adg->clkout[i]); \
56 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
72 for (i = 3; i >= 0; i--) { in rsnd_adg_calculate_rbgx()
75 return (u32)((i << 8) | ((div / ratio) - 1)); in rsnd_adg_calculate_rbgx()
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/OK3568_Linux_fs/kernel/drivers/devfreq/event/
H A Dexynos-nocp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * exynos-nocp.c - Exynos NoC (Network On Chip) Probe support
9 #include <linux/clk.h>
11 #include <linux/devfreq-event.h>
17 #include "exynos-nocp.h"
26 struct clk *clk; member
30 * The devfreq-event ops structure for nocp probe.
38 ret = regmap_update_bits(nocp->regmap, NOCP_MAIN_CTL, in exynos_nocp_set_event()
41 dev_err(nocp->dev, "failed to disable the NoC probe device\n"); in exynos_nocp_set_event()
46 ret = regmap_write(nocp->regmap, NOCP_STAT_PERIOD, 0x0); in exynos_nocp_set_event()
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/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-ath79.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7 * This driver has been based on the spi-gpio.c:
20 #include <linux/clk.h>
22 #include <linux/platform_data/spi-ath79.h>
24 #define DRV_NAME "ath79-spi"
36 #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
37 #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
45 struct clk *clk; member
51 return ioread32(sp->base + reg); in ath79_spi_rr()
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H A Dspi-armada-3700.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Armada-3700 SPI controller driver
8 * Author: Romain Perier <romain.perier@free-electrons.com>
11 #include <linux/clk.h>
105 struct clk *clk; member
119 return readl(a3700_spi->base + offset); in spireg_read()
124 writel(data, a3700_spi->base + offset); in spireg_write()
172 /* RX during address reception uses 4-pin */ in a3700_spi_pin_mode_set()
177 dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode); in a3700_spi_pin_mode_set()
178 return -EINVAL; in a3700_spi_pin_mode_set()
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/OK3568_Linux_fs/kernel/drivers/clk/meson/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
24 * +--------------------------------+
26 * out = in * (m + frac / frac_max) / n
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/OK3568_Linux_fs/kernel/drivers/clk/keystone/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
26 * struct clk_pll_data - pll data structure
28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
64 * struct clk_pll - Main pll clock
79 struct clk_pll_data *pll_data = pll->pll_data; in clk_pllclk_recalc()
84 * get bits 0-5 of multiplier from pllctrl PLLM register in clk_pllclk_recalc()
87 if (pll_data->has_pllctrl) { in clk_pllclk_recalc()
88 val = readl(pll_data->pllm); in clk_pllclk_recalc()
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H A Dgate.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
38 /* Maximum timeout to bail out state transition for module */
44 * struct clk_psc_data - PSC data
56 * struct clk_psc - PSC clock structure
96 } while (((ptstat >> domain_id) & 1) && count--); in psc_config()
101 } while (!((mdstat & MDSTAT_STATE_MASK) == next_state) && count--); in psc_config()
107 struct clk_psc_data *data = psc->psc_data; in keystone_clk_is_enabled()
108 u32 mdstat = readl(data->control_base + MDSTAT); in keystone_clk_is_enabled()
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/OK3568_Linux_fs/kernel/drivers/soc/rockchip/
H A Drockchip_opp_select.c4 * SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk.h>
12 #include <linux/nvmem-consumer.h>
22 #include "../../clk/rockchip/clk.h"
88 * conv = exp(-ln(1.2) / 5 * (temp - 23)) * 100
154 return -EINVAL; in rockchip_nvmem_cell_read_common()
186 return -EINVAL; in rockchip_get_sel_table()
188 if (!prop->value) in rockchip_get_sel_table()
189 return -ENODATA; in rockchip_get_sel_table()
193 return -EINVAL; in rockchip_get_sel_table()
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/OK3568_Linux_fs/kernel/drivers/input/serio/
H A Dambakmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd.
19 #include <linux/clk.h>
24 #define KMI_BASE (kmi->base)
28 struct clk *clk; member
42 serio_interrupt(kmi->io, readb(KMIDATA), 0); in amba_kmi_int()
52 struct amba_kmi_port *kmi = io->port_data; in amba_kmi_write()
55 while ((readb(KMISTAT) & KMISTAT_TXEMPTY) == 0 && --timeleft) in amba_kmi_write()
66 struct amba_kmi_port *kmi = io->port_data; in amba_kmi_open()
70 ret = clk_prepare_enable(kmi->clk); in amba_kmi_open()
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/OK3568_Linux_fs/kernel/drivers/sh/clk/
H A Dcore.c4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
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/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dmps2-timer.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
51 writel_relaxed(val, to_mps2_clkevt(c)->reg + offset); in clockevent_mps2_writel()
72 u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; in mps2_timer_set_periodic()
84 u32 status = readl_relaxed(ce->reg + TIMER_INT); in mps2_timer_interrupt()
91 writel_relaxed(1, ce->reg + TIMER_INT); in mps2_timer_interrupt()
93 ce->clkevt.event_handler(&ce->clkevt); in mps2_timer_interrupt()
101 struct clk *clk = NULL; in mps2_clockevent_init() local
105 const char *name = "mps2-clkevt"; in mps2_clockevent_init()
107 ret = of_property_read_u32(np, "clock-frequency", &rate); in mps2_clockevent_init()
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H A Darm_arch_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
93 struct clock_event_device *clk) in arch_timer_reg_write() argument
96 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write()
99 writel_relaxed(val, timer->base + CNTP_CTL); in arch_timer_reg_write()
102 writel_relaxed(val, timer->base + CNTP_TVAL); in arch_timer_reg_write()
106 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write()
109 writel_relaxed(val, timer->base + CNTV_CTL); in arch_timer_reg_write()
112 writel_relaxed(val, timer->base + CNTV_TVAL); in arch_timer_reg_write()
122 struct clock_event_device *clk) in arch_timer_reg_read() argument
127 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_read()
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/OK3568_Linux_fs/kernel/arch/arm/kernel/
H A Dsmp_twd.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
28 static struct clk *twd_clk;
37 static int twd_shutdown(struct clock_event_device *clk) in twd_shutdown() argument
43 static int twd_set_oneshot(struct clock_event_device *clk) in twd_set_oneshot() argument
51 static int twd_set_periodic(struct clock_event_device *clk) in twd_set_periodic() argument
94 struct clock_event_device *clk = raw_cpu_ptr(twd_evt); in twd_timer_stop() local
96 twd_shutdown(clk); in twd_timer_stop()
97 disable_percpu_irq(clk->irq); in twd_timer_stop()
118 * frequency. The timer is local to a cpu, so cross-call to the in twd_rate_change()
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/OK3568_Linux_fs/kernel/drivers/clk/at91/
H A Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/clk/at91_pmc.h>
31 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
48 "atmel,sama5d2-clk-audio-pll-frac",
54 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
71 "atmel,sama5d2-clk-audio-pll-pad",
77 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
94 "atmel,sama5d2-clk-audio-pll-pmc",
148 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
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/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-sirf.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/clk.h>
70 struct clk *clk; member
92 for (i = 0; i < siic->read_cmd_len; i++) { in i2c_sirfsoc_read_data()
94 data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i); in i2c_sirfsoc_read_data()
95 siic->buf[siic->finished_len++] = in i2c_sirfsoc_read_data()
106 if (siic->msg_read) { in i2c_sirfsoc_queue_cmd()
107 while (((siic->finished_len + i) < siic->msg_len) in i2c_sirfsoc_queue_cmd()
108 && (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) { in i2c_sirfsoc_queue_cmd()
110 if (((siic->finished_len + i) == in i2c_sirfsoc_queue_cmd()
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/OK3568_Linux_fs/kernel/drivers/clk/ti/
H A Dclk-dra7-atl.c19 #include <linux/clk.h>
20 #include <linux/clk-provider.h>
27 #include <linux/clk/ti.h>
47 struct clk *clk; member
72 __raw_writel(val, cinfo->iobase + reg); in atl_write()
77 return __raw_readl(cinfo->iobase + reg); in atl_read()
84 if (!cdesc->probed) in atl_clk_enable()
85 goto out; in atl_clk_enable()
87 if (unlikely(!cdesc->valid)) in atl_clk_enable()
88 dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n", in atl_clk_enable()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
26 qca,clk-out-strength:
31 qca,keep-pll-enabled:
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/OK3568_Linux_fs/kernel/drivers/hwmon/
H A Dg762.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * g762 - Driver for the Global Mixed-mode Technology Inc. fan speed
15 * http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf
27 * http://www.gmt.com.tw/product/datasheet/EDS-762_3.pdf
36 #include <linux/hwmon-sysfs.h>
40 #include <linux/clk.h>
66 #define G762_REG_FAN_CMD1_OUT_MODE 0x20 /* out mode: PWM or DC */
67 #define G762_REG_FAN_CMD1_FAN_MODE 0x10 /* fan mode: closed/open-loop */
79 #define G762_REG_FAN_STA_OOC 0x01 /* fan out of control */
119 struct clk *clk; member
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/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
13 #include "clk.h"
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
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