| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/xilinx/ |
| H A D | video.txt | 1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
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| H A D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/ |
| H A D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
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| /OK3568_Linux_fs/kernel/drivers/media/platform/xilinx/ |
| H A D | xilinx-vip.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Xilinx Video IP Core
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
17 #include <media/v4l2-subdev.h>
22 * Minimum and maximum width and height common to most video IP cores. IP
23 * cores with different requirements must define their own values.
31 * Pad IDs. IP cores with with multiple inputs or outputs should define
37 /* Xilinx Video IP Control Registers */
68 /* Xilinx Video IP Timing Registers */
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/ti/ |
| H A D | ti,pruss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
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| /OK3568_Linux_fs/kernel/Documentation/networking/device_drivers/ethernet/intel/ |
| H A D | i40e.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
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| /OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/ |
| H A D | nonsec_virt.S | 2 * code for switching cores into non-secure state and into HYP mode
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/proc-armv/ptrace.h>
40 * U-Boot calls this "software interrupt" in start.S
42 * to non-secure state.
44 * ip: target PC
56 push {r0, r1, r2, ip}
58 pop {r0, r1, r2, ip}
97 mov lr, ip
98 mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
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| /OK3568_Linux_fs/u-boot/doc/ |
| H A D | README.socfpga | 1 ----------------------------------------
2 SOCFPGA Documentation for U-Boot and SPL
3 ----------------------------------------
5 This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
11 --------------
17 -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
19 --------------------------------------------------
20 Generating the handoff header files for U-Boot SPL
21 --------------------------------------------------
28 projects must have the IP cores updated as shown below.
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| /OK3568_Linux_fs/kernel/arch/arc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
98 source "arch/arc/plat-tb10x/Kconfig"
99 source "arch/arc/plat-axs10x/Kconfig"
100 source "arch/arc/plat-hsdk/Kconfig"
112 The original ARC ISA of ARC600/700 cores
118 ISA for the Next Generation ARC-HS cores
143 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
145 -Caches: New Prog Model, Region Flush
146 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
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| /OK3568_Linux_fs/kernel/arch/arm/mach-exynos/ |
| H A D | mcpm-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // Based on arch/arm/mach-vexpress/dcscb.c
7 #include <linux/arm-cci.h>
12 #include <linux/soc/samsung/exynos-regs-pmu.h>
38 "stmfd sp!, {fp, ip}\n\t"\
53 "ldmfd sp!, {fp, ip}" \
67 return -EINVAL; in exynos_cpu_powerup()
73 * This assumes the cluster number of the big cores(Cortex A15) in exynos_cpu_powerup()
74 * is 0 and the Little cores(Cortex A7) is 1. in exynos_cpu_powerup()
83 * Before we reset the Little cores, we should wait in exynos_cpu_powerup()
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| /OK3568_Linux_fs/u-boot/drivers/spi/ |
| H A D | Kconfig | 16 typically use driver-private data instead of extending the
24 by providing an high-level interface to send memory-like commands.
33 IP core. Please find details on the "Embedded Peripherals IP
41 this Andestech IP core.
50 please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
74 SPI cores.
79 Enable the Broadcom set-top box SPI driver. This driver can
86 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
88 Cadence IP core.
95 IP core.
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| /OK3568_Linux_fs/kernel/Documentation/networking/device_drivers/ethernet/stmicro/ |
| H A D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-grgpio.txt | 1 Aeroflex Gaisler GRGPIO General Purpose I/O cores.
3 The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.
10 - name : Should be "GAISLER_GPIO" or "01_01a"
12 - reg : Address and length of the register set for the device
14 - interrupts : Interrupt numbers for this device
18 - nbits : The number of gpio lines. If not present driver assumes 32 lines.
20 - irqmap : An array with an index for each gpio line. An index is either a valid
25 For further information look in the documentation for the GLIB IP core library:
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | ti,keystone-irq.txt | 1 Keystone 2 IRQ controller IP
3 On Keystone SOCs, DSP cores can send interrupts to ARM
4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
24 compatible = "ti,keystone-irq";
25 ti,syscon-dev = <&devctrl 0x2a0>;
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/bus/ |
| H A D | baikal,bt1-axi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
23 accessible by means of the Baikal-T1 System Controller.
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| /OK3568_Linux_fs/kernel/drivers/clocksource/ |
| H A D | arc_timer.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
18 #include <linux/clk-provider.h>
65 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's in arc_read_gfrc()
68 * simultaneous read/write accesses from cores via those two registers. in arc_read_gfrc()
70 * trying to access two different sub-components (like GFRC, in arc_read_gfrc()
71 * inter-core interrupt, etc...). HW also supports simultaneously in arc_read_gfrc()
72 * accessing GFRC by multiple cores. in arc_read_gfrc()
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| /OK3568_Linux_fs/buildroot/arch/ |
| H A D | Config.in | 28 Synopsys' DesignWare ARC Processor Cores are a family of
29 32-bit CPUs that can be used from deeply embedded to high
36 Synopsys' DesignWare ARC Processor Cores are a family of
37 32-bit CPUs that can be used from deeply embedded to high
44 ARM is a 32-bit reduced instruction set computer (RISC)
54 ARM is a 32-bit reduced instruction set computer (RISC)
65 Aarch64 is a 64-bit architecture developed by ARM Holdings.
66 http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
74 Aarch64 is a 64-bit architecture developed by ARM Holdings.
75 http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/etnaviv/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 tristate "ETNAVIV (DRM support for Vivante GPU IP cores)"
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/ |
| H A D | designware-pcie.txt | 4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
18 - ranges: ranges for the PCI memory and I/O regions
19 - #interrupt-cells: set to <1>
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| /OK3568_Linux_fs/kernel/drivers/net/ethernet/stmicro/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
11 If you have a network (Ethernet) card based on Synopsys Ethernet IP
12 Cores, say Y.
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/timer/ |
| H A D | ti,c64x+timer64.txt | 2 -------
8 - compatible: must be "ti,c64x+timer64"
9 - reg: base address and size of register region
10 - interrupts: interrupt id
14 - ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
16 - ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
21 ti,core-mask = < 0x01 >;
23 interrupt-parent = <&megamod_pic>;
|
| /OK3568_Linux_fs/buildroot/board/arm/foundation-v8/ |
| H A D | readme.txt | 13 ${LOCATION_OF_FOUNDATIONV8_SIMULATOR}/models/Linux64_GCC-6.4/Foundation_Platform \
14 --image output/images/linux-system.axf \
15 --block-device output/images/rootfs.ext2 \
16 --network=nat \
17 --cores 4
20 by requesting an IP address using DHCP (run the command 'udhcpc').
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
16 Split mode providing two individual compute cores for doubling the compute
20 Each Dual-Core R5F sub-system is represented as a single DTS node
22 the individual R5F cores. Each node has a number of required or optional
33 - ti,am654-r5fss
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/ |
| H A D | iproc-udc.txt | 5 on Synopsys Designware Cores AHB Subsystem Device Controller
6 IP.
9 - compatible: Add the compatibility strings for supported platforms.
10 For Broadcom NS2 platform, add "brcm,ns2-udc","brcm,iproc-udc".
11 For Broadcom Cygnus platform, add "brcm,cygnus-udc", "brcm,iproc-udc".
12 - reg: Offset and length of UDC register set
13 - interrupts: description of interrupt line
14 - phys: phandle to phy node.
18 compatible = "brcm,ns2-udc", "brcm,iproc-udc";
|