1menu "Target options" 2 3config BR2_ARCH_IS_64 4 bool 5 6config BR2_KERNEL_64_USERLAND_32 7 bool 8 9config BR2_SOFT_FLOAT 10 bool 11 12config BR2_ARCH_HAS_MMU_MANDATORY 13 bool 14 15config BR2_ARCH_HAS_MMU_OPTIONAL 16 bool 17 18choice 19 prompt "Target Architecture" 20 default BR2_i386 21 help 22 Select the target architecture family to build for. 23 24config BR2_arcle 25 bool "ARC (little endian)" 26 select BR2_ARCH_HAS_MMU_MANDATORY 27 help 28 Synopsys' DesignWare ARC Processor Cores are a family of 29 32-bit CPUs that can be used from deeply embedded to high 30 performance host applications. Little endian. 31 32config BR2_arceb 33 bool "ARC (big endian)" 34 select BR2_ARCH_HAS_MMU_MANDATORY 35 help 36 Synopsys' DesignWare ARC Processor Cores are a family of 37 32-bit CPUs that can be used from deeply embedded to high 38 performance host applications. Big endian. 39 40config BR2_arm 41 bool "ARM (little endian)" 42 # MMU support is set by the subarchitecture file, arch/Config.in.arm 43 help 44 ARM is a 32-bit reduced instruction set computer (RISC) 45 instruction set architecture (ISA) developed by ARM Holdings. 46 Little endian. 47 http://www.arm.com/ 48 http://en.wikipedia.org/wiki/ARM 49 50config BR2_armeb 51 bool "ARM (big endian)" 52 # MMU support is set by the subarchitecture file, arch/Config.in.arm 53 help 54 ARM is a 32-bit reduced instruction set computer (RISC) 55 instruction set architecture (ISA) developed by ARM Holdings. 56 Big endian. 57 http://www.arm.com/ 58 http://en.wikipedia.org/wiki/ARM 59 60config BR2_aarch64 61 bool "AArch64 (little endian)" 62 select BR2_ARCH_IS_64 63 select BR2_ARCH_HAS_MMU_MANDATORY 64 help 65 Aarch64 is a 64-bit architecture developed by ARM Holdings. 66 http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php 67 http://en.wikipedia.org/wiki/ARM 68 69config BR2_aarch64_be 70 bool "AArch64 (big endian)" 71 select BR2_ARCH_IS_64 72 select BR2_ARCH_HAS_MMU_MANDATORY 73 help 74 Aarch64 is a 64-bit architecture developed by ARM Holdings. 75 http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php 76 http://en.wikipedia.org/wiki/ARM 77 78config BR2_csky 79 bool "csky" 80 select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT 81 select BR2_ARCH_HAS_MMU_MANDATORY 82 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 83 help 84 csky is processor IP from china. 85 http://www.c-sky.com/ 86 http://www.github.com/c-sky 87 88config BR2_i386 89 bool "i386" 90 select BR2_ARCH_HAS_MMU_MANDATORY 91 help 92 Intel i386 architecture compatible microprocessor 93 http://en.wikipedia.org/wiki/I386 94 95config BR2_m68k 96 bool "m68k" 97 # MMU support is set by the subarchitecture file, arch/Config.in.m68k 98 help 99 Motorola 68000 family microprocessor 100 http://en.wikipedia.org/wiki/M68k 101 102config BR2_microblazeel 103 bool "Microblaze AXI (little endian)" 104 select BR2_ARCH_HAS_MMU_MANDATORY 105 help 106 Soft processor core designed for Xilinx FPGAs from Xilinx. AXI 107 bus based architecture (little endian) 108 http://www.xilinx.com 109 http://en.wikipedia.org/wiki/Microblaze 110 111config BR2_microblazebe 112 bool "Microblaze non-AXI (big endian)" 113 select BR2_ARCH_HAS_MMU_MANDATORY 114 help 115 Soft processor core designed for Xilinx FPGAs from Xilinx. PLB 116 bus based architecture (non-AXI, big endian) 117 http://www.xilinx.com 118 http://en.wikipedia.org/wiki/Microblaze 119 120config BR2_mips 121 bool "MIPS (big endian)" 122 select BR2_ARCH_HAS_MMU_MANDATORY 123 help 124 MIPS is a RISC microprocessor from MIPS Technologies. Big 125 endian. 126 http://www.mips.com/ 127 http://en.wikipedia.org/wiki/MIPS_Technologies 128 129config BR2_mipsel 130 bool "MIPS (little endian)" 131 select BR2_ARCH_HAS_MMU_MANDATORY 132 help 133 MIPS is a RISC microprocessor from MIPS Technologies. Little 134 endian. 135 http://www.mips.com/ 136 http://en.wikipedia.org/wiki/MIPS_Technologies 137 138config BR2_mips64 139 bool "MIPS64 (big endian)" 140 select BR2_ARCH_IS_64 141 select BR2_ARCH_HAS_MMU_MANDATORY 142 help 143 MIPS is a RISC microprocessor from MIPS Technologies. Big 144 endian. 145 http://www.mips.com/ 146 http://en.wikipedia.org/wiki/MIPS_Technologies 147 148config BR2_mips64el 149 bool "MIPS64 (little endian)" 150 select BR2_ARCH_IS_64 151 select BR2_ARCH_HAS_MMU_MANDATORY 152 help 153 MIPS is a RISC microprocessor from MIPS Technologies. Little 154 endian. 155 http://www.mips.com/ 156 http://en.wikipedia.org/wiki/MIPS_Technologies 157 158config BR2_nds32 159 bool "nds32" 160 select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT 161 select BR2_ARCH_HAS_MMU_MANDATORY 162 help 163 nds32 is a 32-bit architecture developed by Andes Technology. 164 https://en.wikipedia.org/wiki/Andes_Technology 165 166config BR2_nios2 167 bool "Nios II" 168 select BR2_ARCH_HAS_MMU_MANDATORY 169 help 170 Nios II is a soft core processor from Altera Corporation. 171 http://www.altera.com/ 172 http://en.wikipedia.org/wiki/Nios_II 173 174config BR2_or1k 175 bool "OpenRISC" 176 select BR2_ARCH_HAS_MMU_MANDATORY 177 help 178 OpenRISC is a free and open processor for embedded system. 179 http://openrisc.io 180 181config BR2_powerpc 182 bool "PowerPC" 183 select BR2_ARCH_HAS_MMU_MANDATORY 184 help 185 PowerPC is a RISC architecture created by Apple-IBM-Motorola 186 alliance. Big endian. 187 http://www.power.org/ 188 http://en.wikipedia.org/wiki/Powerpc 189 190config BR2_powerpc64 191 bool "PowerPC64 (big endian)" 192 select BR2_ARCH_IS_64 193 select BR2_ARCH_HAS_MMU_MANDATORY 194 help 195 PowerPC is a RISC architecture created by Apple-IBM-Motorola 196 alliance. Big endian. 197 http://www.power.org/ 198 http://en.wikipedia.org/wiki/Powerpc 199 200config BR2_powerpc64le 201 bool "PowerPC64 (little endian)" 202 select BR2_ARCH_IS_64 203 select BR2_ARCH_HAS_MMU_MANDATORY 204 help 205 PowerPC is a RISC architecture created by Apple-IBM-Motorola 206 alliance. Little endian. 207 http://www.power.org/ 208 http://en.wikipedia.org/wiki/Powerpc 209 210config BR2_riscv 211 bool "RISCV" 212 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 213 help 214 RISC-V is an open, free Instruction Set Architecture created 215 by the UC Berkeley Architecture Research group and supported 216 and promoted by RISC-V Foundation. 217 https://riscv.org/ 218 https://en.wikipedia.org/wiki/RISC-V 219 220config BR2_s390x 221 bool "s390x" 222 select BR2_ARCH_IS_64 223 select BR2_ARCH_HAS_MMU_MANDATORY 224 help 225 s390x is a big-endian architecture made by IBM. 226 http://www.ibm.com/ 227 http://en.wikipedia.org/wiki/IBM_System/390 228 229config BR2_sh 230 bool "SuperH" 231 select BR2_ARCH_HAS_MMU_OPTIONAL 232 help 233 SuperH (or SH) is a 32-bit reduced instruction set computer 234 (RISC) instruction set architecture (ISA) developed by 235 Hitachi. 236 http://www.hitachi.com/ 237 http://en.wikipedia.org/wiki/SuperH 238 239config BR2_sparc 240 bool "SPARC" 241 select BR2_ARCH_HAS_MMU_MANDATORY 242 help 243 SPARC (from Scalable Processor Architecture) is a RISC 244 instruction set architecture (ISA) developed by Sun 245 Microsystems. 246 http://www.oracle.com/sun 247 http://en.wikipedia.org/wiki/Sparc 248 249config BR2_sparc64 250 bool "SPARC64" 251 select BR2_ARCH_IS_64 252 select BR2_ARCH_HAS_MMU_MANDATORY 253 help 254 SPARC (from Scalable Processor Architecture) is a RISC 255 instruction set architecture (ISA) developed by Sun 256 Microsystems. 257 http://www.oracle.com/sun 258 http://en.wikipedia.org/wiki/Sparc 259 260config BR2_x86_64 261 bool "x86_64" 262 select BR2_ARCH_IS_64 263 select BR2_ARCH_HAS_MMU_MANDATORY 264 help 265 x86-64 is an extension of the x86 instruction set (Intel i386 266 architecture compatible microprocessor). 267 http://en.wikipedia.org/wiki/X86_64 268 269config BR2_xtensa 270 bool "Xtensa" 271 # MMU support is set by the subarchitecture file, arch/Config.in.xtensa 272 help 273 Xtensa is a Tensilica processor IP architecture. 274 http://en.wikipedia.org/wiki/Xtensa 275 http://www.tensilica.com/ 276 277endchoice 278 279# For some architectures or specific cores, our internal toolchain 280# backend is not suitable (like, missing support in upstream gcc, or 281# no ChipCo fork exists...) 282config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT 283 bool 284 285config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT 286 bool 287 default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT 288 289# The following symbols are selected by the individual 290# Config.in.$ARCH files 291config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8 292 bool 293 294config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 295 bool 296 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8 297 298config BR2_ARCH_NEEDS_GCC_AT_LEAST_5 299 bool 300 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 301 302config BR2_ARCH_NEEDS_GCC_AT_LEAST_6 303 bool 304 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 305 306config BR2_ARCH_NEEDS_GCC_AT_LEAST_7 307 bool 308 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 309 310config BR2_ARCH_NEEDS_GCC_AT_LEAST_8 311 bool 312 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 313 314config BR2_ARCH_NEEDS_GCC_AT_LEAST_9 315 bool 316 select BR2_ARCH_NEEDS_GCC_AT_LEAST_8 317 318config BR2_ARCH_NEEDS_GCC_AT_LEAST_10 319 bool 320 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 321 322config BR2_ARCH_NEEDS_GCC_AT_LEAST_11 323 bool 324 select BR2_ARCH_NEEDS_GCC_AT_LEAST_10 325 326# The following string values are defined by the individual 327# Config.in.$ARCH files 328config BR2_ARCH 329 string 330 331config BR2_NORMALIZED_ARCH 332 string 333 334config BR2_ENDIAN 335 string 336 337config BR2_GCC_TARGET_ARCH 338 string 339 340config BR2_GCC_TARGET_ABI 341 string 342 343config BR2_GCC_TARGET_NAN 344 string 345 346config BR2_GCC_TARGET_FP32_MODE 347 string 348 349config BR2_GCC_TARGET_CPU 350 string 351 352# The value of this option will be passed as --with-fpu=<value> when 353# building gcc (internal backend) or -mfpu=<value> in the toolchain 354# wrapper (external toolchain) 355config BR2_GCC_TARGET_FPU 356 string 357 358# The value of this option will be passed as --with-float=<value> when 359# building gcc (internal backend) or -mfloat-abi=<value> in the toolchain 360# wrapper (external toolchain) 361config BR2_GCC_TARGET_FLOAT_ABI 362 string 363 364# The value of this option will be passed as --with-mode=<value> when 365# building gcc (internal backend) or -m<value> in the toolchain 366# wrapper (external toolchain) 367config BR2_GCC_TARGET_MODE 368 string 369 370# Must be selected by binary formats that support shared libraries. 371config BR2_BINFMT_SUPPORTS_SHARED 372 bool 373 374# Must match the name of the architecture from readelf point of view, 375# i.e the "Machine:" field of readelf output. See get_machine_name() 376# in binutils/readelf.c for the list of possible values. 377config BR2_READELF_ARCH_NAME 378 string 379 380# Set up target binary format 381choice 382 prompt "Target Binary Format" 383 default BR2_BINFMT_ELF if BR2_USE_MMU 384 default BR2_BINFMT_FLAT 385 386config BR2_BINFMT_ELF 387 bool "ELF" 388 depends on BR2_USE_MMU 389 select BR2_BINFMT_SUPPORTS_SHARED 390 help 391 ELF (Executable and Linkable Format) is a format for libraries 392 and executables used across different architectures and 393 operating systems. 394 395config BR2_BINFMT_FLAT 396 bool "FLAT" 397 depends on !BR2_USE_MMU 398 help 399 FLAT binary is a relatively simple and lightweight executable 400 format based on the original a.out format. It is widely used 401 in environment where no MMU is available. 402 403endchoice 404 405# Set up flat binary type 406choice 407 prompt "FLAT Binary type" 408 default BR2_BINFMT_FLAT_ONE 409 depends on BR2_BINFMT_FLAT 410 411config BR2_BINFMT_FLAT_ONE 412 bool "One memory region" 413 help 414 All segments are linked into one memory region. 415 416config BR2_BINFMT_FLAT_SHARED 417 bool "Shared binary" 418 depends on BR2_m68k 419 # Even though this really generates shared binaries, there is no libdl 420 # and dlopen() cannot be used. So packages that require shared 421 # libraries cannot be built. Therefore, we don't select 422 # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS. 423 # Although this adds -static to the compilation, that's not a problem 424 # because the -mid-shared-library option overrides it. 425 help 426 Allow to load and link indiviual FLAT binaries at run time. 427 428endchoice 429 430if BR2_arcle || BR2_arceb 431source "arch/Config.in.arc" 432endif 433 434if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be 435source "arch/Config.in.arm" 436endif 437 438if BR2_csky 439source "arch/Config.in.csky" 440endif 441 442if BR2_m68k 443source "arch/Config.in.m68k" 444endif 445 446if BR2_microblazeel || BR2_microblazebe 447source "arch/Config.in.microblaze" 448endif 449 450if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el 451source "arch/Config.in.mips" 452endif 453 454if BR2_nds32 455source "arch/Config.in.nds32" 456endif 457 458if BR2_nios2 459source "arch/Config.in.nios2" 460endif 461 462if BR2_or1k 463source "arch/Config.in.or1k" 464endif 465 466if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le 467source "arch/Config.in.powerpc" 468endif 469 470if BR2_riscv 471source "arch/Config.in.riscv" 472endif 473 474if BR2_s390x 475source "arch/Config.in.s390x" 476endif 477 478if BR2_sh 479source "arch/Config.in.sh" 480endif 481 482if BR2_sparc || BR2_sparc64 483source "arch/Config.in.sparc" 484endif 485 486if BR2_i386 || BR2_x86_64 487source "arch/Config.in.x86" 488endif 489 490if BR2_xtensa 491source "arch/Config.in.xtensa" 492endif 493 494endmenu # Target options 495