xref: /OK3568_Linux_fs/buildroot/arch/Config.in (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyunmenu "Target options"
2*4882a593Smuzhiyun
3*4882a593Smuzhiyunconfig BR2_ARCH_IS_64
4*4882a593Smuzhiyun	bool
5*4882a593Smuzhiyun
6*4882a593Smuzhiyunconfig BR2_KERNEL_64_USERLAND_32
7*4882a593Smuzhiyun	bool
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunconfig BR2_SOFT_FLOAT
10*4882a593Smuzhiyun	bool
11*4882a593Smuzhiyun
12*4882a593Smuzhiyunconfig BR2_ARCH_HAS_MMU_MANDATORY
13*4882a593Smuzhiyun	bool
14*4882a593Smuzhiyun
15*4882a593Smuzhiyunconfig BR2_ARCH_HAS_MMU_OPTIONAL
16*4882a593Smuzhiyun	bool
17*4882a593Smuzhiyun
18*4882a593Smuzhiyunchoice
19*4882a593Smuzhiyun	prompt "Target Architecture"
20*4882a593Smuzhiyun	default BR2_i386
21*4882a593Smuzhiyun	help
22*4882a593Smuzhiyun	  Select the target architecture family to build for.
23*4882a593Smuzhiyun
24*4882a593Smuzhiyunconfig BR2_arcle
25*4882a593Smuzhiyun	bool "ARC (little endian)"
26*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
27*4882a593Smuzhiyun	help
28*4882a593Smuzhiyun	  Synopsys' DesignWare ARC Processor Cores are a family of
29*4882a593Smuzhiyun	  32-bit CPUs that can be used from deeply embedded to high
30*4882a593Smuzhiyun	  performance host applications. Little endian.
31*4882a593Smuzhiyun
32*4882a593Smuzhiyunconfig BR2_arceb
33*4882a593Smuzhiyun	bool "ARC (big endian)"
34*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
35*4882a593Smuzhiyun	help
36*4882a593Smuzhiyun	  Synopsys' DesignWare ARC Processor Cores are a family of
37*4882a593Smuzhiyun	  32-bit CPUs that can be used from deeply embedded to high
38*4882a593Smuzhiyun	  performance host applications. Big endian.
39*4882a593Smuzhiyun
40*4882a593Smuzhiyunconfig BR2_arm
41*4882a593Smuzhiyun	bool "ARM (little endian)"
42*4882a593Smuzhiyun	# MMU support is set by the subarchitecture file, arch/Config.in.arm
43*4882a593Smuzhiyun	help
44*4882a593Smuzhiyun	  ARM is a 32-bit reduced instruction set computer (RISC)
45*4882a593Smuzhiyun	  instruction set architecture (ISA) developed by ARM Holdings.
46*4882a593Smuzhiyun	  Little endian.
47*4882a593Smuzhiyun	  http://www.arm.com/
48*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/ARM
49*4882a593Smuzhiyun
50*4882a593Smuzhiyunconfig BR2_armeb
51*4882a593Smuzhiyun	bool "ARM (big endian)"
52*4882a593Smuzhiyun	# MMU support is set by the subarchitecture file, arch/Config.in.arm
53*4882a593Smuzhiyun	help
54*4882a593Smuzhiyun	  ARM is a 32-bit reduced instruction set computer (RISC)
55*4882a593Smuzhiyun	  instruction set architecture (ISA) developed by ARM Holdings.
56*4882a593Smuzhiyun	  Big endian.
57*4882a593Smuzhiyun	  http://www.arm.com/
58*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/ARM
59*4882a593Smuzhiyun
60*4882a593Smuzhiyunconfig BR2_aarch64
61*4882a593Smuzhiyun	bool "AArch64 (little endian)"
62*4882a593Smuzhiyun	select BR2_ARCH_IS_64
63*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
64*4882a593Smuzhiyun	help
65*4882a593Smuzhiyun	  Aarch64 is a 64-bit architecture developed by ARM Holdings.
66*4882a593Smuzhiyun	  http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
67*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/ARM
68*4882a593Smuzhiyun
69*4882a593Smuzhiyunconfig BR2_aarch64_be
70*4882a593Smuzhiyun	bool "AArch64 (big endian)"
71*4882a593Smuzhiyun	select BR2_ARCH_IS_64
72*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
73*4882a593Smuzhiyun	help
74*4882a593Smuzhiyun	  Aarch64 is a 64-bit architecture developed by ARM Holdings.
75*4882a593Smuzhiyun	  http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
76*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/ARM
77*4882a593Smuzhiyun
78*4882a593Smuzhiyunconfig BR2_csky
79*4882a593Smuzhiyun	bool "csky"
80*4882a593Smuzhiyun	select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
81*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
82*4882a593Smuzhiyun	select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
83*4882a593Smuzhiyun	help
84*4882a593Smuzhiyun	  csky is processor IP from china.
85*4882a593Smuzhiyun	  http://www.c-sky.com/
86*4882a593Smuzhiyun	  http://www.github.com/c-sky
87*4882a593Smuzhiyun
88*4882a593Smuzhiyunconfig BR2_i386
89*4882a593Smuzhiyun	bool "i386"
90*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
91*4882a593Smuzhiyun	help
92*4882a593Smuzhiyun	  Intel i386 architecture compatible microprocessor
93*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/I386
94*4882a593Smuzhiyun
95*4882a593Smuzhiyunconfig BR2_m68k
96*4882a593Smuzhiyun	bool "m68k"
97*4882a593Smuzhiyun	# MMU support is set by the subarchitecture file, arch/Config.in.m68k
98*4882a593Smuzhiyun	help
99*4882a593Smuzhiyun	  Motorola 68000 family microprocessor
100*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/M68k
101*4882a593Smuzhiyun
102*4882a593Smuzhiyunconfig BR2_microblazeel
103*4882a593Smuzhiyun	bool "Microblaze AXI (little endian)"
104*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
105*4882a593Smuzhiyun	help
106*4882a593Smuzhiyun	  Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
107*4882a593Smuzhiyun	  bus based architecture (little endian)
108*4882a593Smuzhiyun	  http://www.xilinx.com
109*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/Microblaze
110*4882a593Smuzhiyun
111*4882a593Smuzhiyunconfig BR2_microblazebe
112*4882a593Smuzhiyun	bool "Microblaze non-AXI (big endian)"
113*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
114*4882a593Smuzhiyun	help
115*4882a593Smuzhiyun	  Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
116*4882a593Smuzhiyun	  bus based architecture (non-AXI, big endian)
117*4882a593Smuzhiyun	  http://www.xilinx.com
118*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/Microblaze
119*4882a593Smuzhiyun
120*4882a593Smuzhiyunconfig BR2_mips
121*4882a593Smuzhiyun	bool "MIPS (big endian)"
122*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
123*4882a593Smuzhiyun	help
124*4882a593Smuzhiyun	  MIPS is a RISC microprocessor from MIPS Technologies. Big
125*4882a593Smuzhiyun	  endian.
126*4882a593Smuzhiyun	  http://www.mips.com/
127*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/MIPS_Technologies
128*4882a593Smuzhiyun
129*4882a593Smuzhiyunconfig BR2_mipsel
130*4882a593Smuzhiyun	bool "MIPS (little endian)"
131*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
132*4882a593Smuzhiyun	help
133*4882a593Smuzhiyun	  MIPS is a RISC microprocessor from MIPS Technologies. Little
134*4882a593Smuzhiyun	  endian.
135*4882a593Smuzhiyun	  http://www.mips.com/
136*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/MIPS_Technologies
137*4882a593Smuzhiyun
138*4882a593Smuzhiyunconfig BR2_mips64
139*4882a593Smuzhiyun	bool "MIPS64 (big endian)"
140*4882a593Smuzhiyun	select BR2_ARCH_IS_64
141*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
142*4882a593Smuzhiyun	help
143*4882a593Smuzhiyun	  MIPS is a RISC microprocessor from MIPS Technologies. Big
144*4882a593Smuzhiyun	  endian.
145*4882a593Smuzhiyun	  http://www.mips.com/
146*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/MIPS_Technologies
147*4882a593Smuzhiyun
148*4882a593Smuzhiyunconfig BR2_mips64el
149*4882a593Smuzhiyun	bool "MIPS64 (little endian)"
150*4882a593Smuzhiyun	select BR2_ARCH_IS_64
151*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
152*4882a593Smuzhiyun	help
153*4882a593Smuzhiyun	  MIPS is a RISC microprocessor from MIPS Technologies. Little
154*4882a593Smuzhiyun	  endian.
155*4882a593Smuzhiyun	  http://www.mips.com/
156*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/MIPS_Technologies
157*4882a593Smuzhiyun
158*4882a593Smuzhiyunconfig BR2_nds32
159*4882a593Smuzhiyun	bool "nds32"
160*4882a593Smuzhiyun	select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
161*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
162*4882a593Smuzhiyun	help
163*4882a593Smuzhiyun	  nds32 is a 32-bit architecture developed by Andes Technology.
164*4882a593Smuzhiyun	  https://en.wikipedia.org/wiki/Andes_Technology
165*4882a593Smuzhiyun
166*4882a593Smuzhiyunconfig BR2_nios2
167*4882a593Smuzhiyun	bool "Nios II"
168*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
169*4882a593Smuzhiyun	help
170*4882a593Smuzhiyun	  Nios II is a soft core processor from Altera Corporation.
171*4882a593Smuzhiyun	  http://www.altera.com/
172*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/Nios_II
173*4882a593Smuzhiyun
174*4882a593Smuzhiyunconfig BR2_or1k
175*4882a593Smuzhiyun	bool "OpenRISC"
176*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
177*4882a593Smuzhiyun	help
178*4882a593Smuzhiyun	  OpenRISC is a free and open processor for embedded system.
179*4882a593Smuzhiyun	  http://openrisc.io
180*4882a593Smuzhiyun
181*4882a593Smuzhiyunconfig BR2_powerpc
182*4882a593Smuzhiyun	bool "PowerPC"
183*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
184*4882a593Smuzhiyun	help
185*4882a593Smuzhiyun	  PowerPC is a RISC architecture created by Apple-IBM-Motorola
186*4882a593Smuzhiyun	  alliance. Big endian.
187*4882a593Smuzhiyun	  http://www.power.org/
188*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/Powerpc
189*4882a593Smuzhiyun
190*4882a593Smuzhiyunconfig BR2_powerpc64
191*4882a593Smuzhiyun	bool "PowerPC64 (big endian)"
192*4882a593Smuzhiyun	select BR2_ARCH_IS_64
193*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
194*4882a593Smuzhiyun	help
195*4882a593Smuzhiyun	  PowerPC is a RISC architecture created by Apple-IBM-Motorola
196*4882a593Smuzhiyun	  alliance. Big endian.
197*4882a593Smuzhiyun	  http://www.power.org/
198*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/Powerpc
199*4882a593Smuzhiyun
200*4882a593Smuzhiyunconfig BR2_powerpc64le
201*4882a593Smuzhiyun	bool "PowerPC64 (little endian)"
202*4882a593Smuzhiyun	select BR2_ARCH_IS_64
203*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
204*4882a593Smuzhiyun	help
205*4882a593Smuzhiyun	  PowerPC is a RISC architecture created by Apple-IBM-Motorola
206*4882a593Smuzhiyun	  alliance. Little endian.
207*4882a593Smuzhiyun	  http://www.power.org/
208*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/Powerpc
209*4882a593Smuzhiyun
210*4882a593Smuzhiyunconfig BR2_riscv
211*4882a593Smuzhiyun	bool "RISCV"
212*4882a593Smuzhiyun	select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
213*4882a593Smuzhiyun	help
214*4882a593Smuzhiyun	  RISC-V is an open, free Instruction Set Architecture created
215*4882a593Smuzhiyun	  by the UC Berkeley Architecture Research group and supported
216*4882a593Smuzhiyun	  and promoted by RISC-V Foundation.
217*4882a593Smuzhiyun	  https://riscv.org/
218*4882a593Smuzhiyun	  https://en.wikipedia.org/wiki/RISC-V
219*4882a593Smuzhiyun
220*4882a593Smuzhiyunconfig BR2_s390x
221*4882a593Smuzhiyun	bool "s390x"
222*4882a593Smuzhiyun	select BR2_ARCH_IS_64
223*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
224*4882a593Smuzhiyun	help
225*4882a593Smuzhiyun	  s390x is a big-endian architecture made by IBM.
226*4882a593Smuzhiyun	  http://www.ibm.com/
227*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/IBM_System/390
228*4882a593Smuzhiyun
229*4882a593Smuzhiyunconfig BR2_sh
230*4882a593Smuzhiyun	bool "SuperH"
231*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_OPTIONAL
232*4882a593Smuzhiyun	help
233*4882a593Smuzhiyun	  SuperH (or SH) is a 32-bit reduced instruction set computer
234*4882a593Smuzhiyun	  (RISC) instruction set architecture (ISA) developed by
235*4882a593Smuzhiyun	  Hitachi.
236*4882a593Smuzhiyun	  http://www.hitachi.com/
237*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/SuperH
238*4882a593Smuzhiyun
239*4882a593Smuzhiyunconfig BR2_sparc
240*4882a593Smuzhiyun	bool "SPARC"
241*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
242*4882a593Smuzhiyun	help
243*4882a593Smuzhiyun	  SPARC (from Scalable Processor Architecture) is a RISC
244*4882a593Smuzhiyun	  instruction set architecture (ISA) developed by Sun
245*4882a593Smuzhiyun	  Microsystems.
246*4882a593Smuzhiyun	  http://www.oracle.com/sun
247*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/Sparc
248*4882a593Smuzhiyun
249*4882a593Smuzhiyunconfig BR2_sparc64
250*4882a593Smuzhiyun	bool "SPARC64"
251*4882a593Smuzhiyun	select BR2_ARCH_IS_64
252*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
253*4882a593Smuzhiyun	help
254*4882a593Smuzhiyun	  SPARC (from Scalable Processor Architecture) is a RISC
255*4882a593Smuzhiyun	  instruction set architecture (ISA) developed by Sun
256*4882a593Smuzhiyun	  Microsystems.
257*4882a593Smuzhiyun	  http://www.oracle.com/sun
258*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/Sparc
259*4882a593Smuzhiyun
260*4882a593Smuzhiyunconfig BR2_x86_64
261*4882a593Smuzhiyun	bool "x86_64"
262*4882a593Smuzhiyun	select BR2_ARCH_IS_64
263*4882a593Smuzhiyun	select BR2_ARCH_HAS_MMU_MANDATORY
264*4882a593Smuzhiyun	help
265*4882a593Smuzhiyun	  x86-64 is an extension of the x86 instruction set (Intel i386
266*4882a593Smuzhiyun	  architecture compatible microprocessor).
267*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/X86_64
268*4882a593Smuzhiyun
269*4882a593Smuzhiyunconfig BR2_xtensa
270*4882a593Smuzhiyun	bool "Xtensa"
271*4882a593Smuzhiyun	# MMU support is set by the subarchitecture file, arch/Config.in.xtensa
272*4882a593Smuzhiyun	help
273*4882a593Smuzhiyun	  Xtensa is a Tensilica processor IP architecture.
274*4882a593Smuzhiyun	  http://en.wikipedia.org/wiki/Xtensa
275*4882a593Smuzhiyun	  http://www.tensilica.com/
276*4882a593Smuzhiyun
277*4882a593Smuzhiyunendchoice
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun# For some architectures or specific cores, our internal toolchain
280*4882a593Smuzhiyun# backend is not suitable (like, missing support in upstream gcc, or
281*4882a593Smuzhiyun# no ChipCo fork exists...)
282*4882a593Smuzhiyunconfig BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
283*4882a593Smuzhiyun	bool
284*4882a593Smuzhiyun
285*4882a593Smuzhiyunconfig BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
286*4882a593Smuzhiyun	bool
287*4882a593Smuzhiyun	default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun# The following symbols are selected by the individual
290*4882a593Smuzhiyun# Config.in.$ARCH files
291*4882a593Smuzhiyunconfig BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
292*4882a593Smuzhiyun	bool
293*4882a593Smuzhiyun
294*4882a593Smuzhiyunconfig BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
295*4882a593Smuzhiyun	bool
296*4882a593Smuzhiyun	select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
297*4882a593Smuzhiyun
298*4882a593Smuzhiyunconfig BR2_ARCH_NEEDS_GCC_AT_LEAST_5
299*4882a593Smuzhiyun	bool
300*4882a593Smuzhiyun	select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
301*4882a593Smuzhiyun
302*4882a593Smuzhiyunconfig BR2_ARCH_NEEDS_GCC_AT_LEAST_6
303*4882a593Smuzhiyun	bool
304*4882a593Smuzhiyun	select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
305*4882a593Smuzhiyun
306*4882a593Smuzhiyunconfig BR2_ARCH_NEEDS_GCC_AT_LEAST_7
307*4882a593Smuzhiyun	bool
308*4882a593Smuzhiyun	select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
309*4882a593Smuzhiyun
310*4882a593Smuzhiyunconfig BR2_ARCH_NEEDS_GCC_AT_LEAST_8
311*4882a593Smuzhiyun	bool
312*4882a593Smuzhiyun	select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
313*4882a593Smuzhiyun
314*4882a593Smuzhiyunconfig BR2_ARCH_NEEDS_GCC_AT_LEAST_9
315*4882a593Smuzhiyun	bool
316*4882a593Smuzhiyun	select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
317*4882a593Smuzhiyun
318*4882a593Smuzhiyunconfig BR2_ARCH_NEEDS_GCC_AT_LEAST_10
319*4882a593Smuzhiyun	bool
320*4882a593Smuzhiyun	select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
321*4882a593Smuzhiyun
322*4882a593Smuzhiyunconfig BR2_ARCH_NEEDS_GCC_AT_LEAST_11
323*4882a593Smuzhiyun	bool
324*4882a593Smuzhiyun	select BR2_ARCH_NEEDS_GCC_AT_LEAST_10
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun# The following string values are defined by the individual
327*4882a593Smuzhiyun# Config.in.$ARCH files
328*4882a593Smuzhiyunconfig BR2_ARCH
329*4882a593Smuzhiyun	string
330*4882a593Smuzhiyun
331*4882a593Smuzhiyunconfig BR2_NORMALIZED_ARCH
332*4882a593Smuzhiyun	string
333*4882a593Smuzhiyun
334*4882a593Smuzhiyunconfig BR2_ENDIAN
335*4882a593Smuzhiyun	string
336*4882a593Smuzhiyun
337*4882a593Smuzhiyunconfig BR2_GCC_TARGET_ARCH
338*4882a593Smuzhiyun	string
339*4882a593Smuzhiyun
340*4882a593Smuzhiyunconfig BR2_GCC_TARGET_ABI
341*4882a593Smuzhiyun	string
342*4882a593Smuzhiyun
343*4882a593Smuzhiyunconfig BR2_GCC_TARGET_NAN
344*4882a593Smuzhiyun	string
345*4882a593Smuzhiyun
346*4882a593Smuzhiyunconfig BR2_GCC_TARGET_FP32_MODE
347*4882a593Smuzhiyun	string
348*4882a593Smuzhiyun
349*4882a593Smuzhiyunconfig BR2_GCC_TARGET_CPU
350*4882a593Smuzhiyun	string
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun# The value of this option will be passed as --with-fpu=<value> when
353*4882a593Smuzhiyun# building gcc (internal backend) or -mfpu=<value> in the toolchain
354*4882a593Smuzhiyun# wrapper (external toolchain)
355*4882a593Smuzhiyunconfig BR2_GCC_TARGET_FPU
356*4882a593Smuzhiyun	string
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun# The value of this option will be passed as --with-float=<value> when
359*4882a593Smuzhiyun# building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
360*4882a593Smuzhiyun# wrapper (external toolchain)
361*4882a593Smuzhiyunconfig BR2_GCC_TARGET_FLOAT_ABI
362*4882a593Smuzhiyun	string
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun# The value of this option will be passed as --with-mode=<value> when
365*4882a593Smuzhiyun# building gcc (internal backend) or -m<value> in the toolchain
366*4882a593Smuzhiyun# wrapper (external toolchain)
367*4882a593Smuzhiyunconfig BR2_GCC_TARGET_MODE
368*4882a593Smuzhiyun	string
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun# Must be selected by binary formats that support shared libraries.
371*4882a593Smuzhiyunconfig BR2_BINFMT_SUPPORTS_SHARED
372*4882a593Smuzhiyun	bool
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun# Must match the name of the architecture from readelf point of view,
375*4882a593Smuzhiyun# i.e the "Machine:" field of readelf output. See get_machine_name()
376*4882a593Smuzhiyun# in binutils/readelf.c for the list of possible values.
377*4882a593Smuzhiyunconfig BR2_READELF_ARCH_NAME
378*4882a593Smuzhiyun	string
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun# Set up target binary format
381*4882a593Smuzhiyunchoice
382*4882a593Smuzhiyun	prompt "Target Binary Format"
383*4882a593Smuzhiyun	default BR2_BINFMT_ELF if BR2_USE_MMU
384*4882a593Smuzhiyun	default BR2_BINFMT_FLAT
385*4882a593Smuzhiyun
386*4882a593Smuzhiyunconfig BR2_BINFMT_ELF
387*4882a593Smuzhiyun	bool "ELF"
388*4882a593Smuzhiyun	depends on BR2_USE_MMU
389*4882a593Smuzhiyun	select BR2_BINFMT_SUPPORTS_SHARED
390*4882a593Smuzhiyun	help
391*4882a593Smuzhiyun	  ELF (Executable and Linkable Format) is a format for libraries
392*4882a593Smuzhiyun	  and executables used across different architectures and
393*4882a593Smuzhiyun	  operating systems.
394*4882a593Smuzhiyun
395*4882a593Smuzhiyunconfig BR2_BINFMT_FLAT
396*4882a593Smuzhiyun	bool "FLAT"
397*4882a593Smuzhiyun	depends on !BR2_USE_MMU
398*4882a593Smuzhiyun	help
399*4882a593Smuzhiyun	  FLAT binary is a relatively simple and lightweight executable
400*4882a593Smuzhiyun	  format based on the original a.out format. It is widely used
401*4882a593Smuzhiyun	  in environment where no MMU is available.
402*4882a593Smuzhiyun
403*4882a593Smuzhiyunendchoice
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun# Set up flat binary type
406*4882a593Smuzhiyunchoice
407*4882a593Smuzhiyun	prompt "FLAT Binary type"
408*4882a593Smuzhiyun	default BR2_BINFMT_FLAT_ONE
409*4882a593Smuzhiyun	depends on BR2_BINFMT_FLAT
410*4882a593Smuzhiyun
411*4882a593Smuzhiyunconfig BR2_BINFMT_FLAT_ONE
412*4882a593Smuzhiyun	bool "One memory region"
413*4882a593Smuzhiyun	help
414*4882a593Smuzhiyun	  All segments are linked into one memory region.
415*4882a593Smuzhiyun
416*4882a593Smuzhiyunconfig BR2_BINFMT_FLAT_SHARED
417*4882a593Smuzhiyun	bool "Shared binary"
418*4882a593Smuzhiyun	depends on BR2_m68k
419*4882a593Smuzhiyun	# Even though this really generates shared binaries, there is no libdl
420*4882a593Smuzhiyun	# and dlopen() cannot be used. So packages that require shared
421*4882a593Smuzhiyun	# libraries cannot be built. Therefore, we don't select
422*4882a593Smuzhiyun	# BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
423*4882a593Smuzhiyun	# Although this adds -static to the compilation, that's not a problem
424*4882a593Smuzhiyun	# because the -mid-shared-library option overrides it.
425*4882a593Smuzhiyun	help
426*4882a593Smuzhiyun	  Allow to load and link indiviual FLAT binaries at run time.
427*4882a593Smuzhiyun
428*4882a593Smuzhiyunendchoice
429*4882a593Smuzhiyun
430*4882a593Smuzhiyunif BR2_arcle || BR2_arceb
431*4882a593Smuzhiyunsource "arch/Config.in.arc"
432*4882a593Smuzhiyunendif
433*4882a593Smuzhiyun
434*4882a593Smuzhiyunif BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
435*4882a593Smuzhiyunsource "arch/Config.in.arm"
436*4882a593Smuzhiyunendif
437*4882a593Smuzhiyun
438*4882a593Smuzhiyunif BR2_csky
439*4882a593Smuzhiyunsource "arch/Config.in.csky"
440*4882a593Smuzhiyunendif
441*4882a593Smuzhiyun
442*4882a593Smuzhiyunif BR2_m68k
443*4882a593Smuzhiyunsource "arch/Config.in.m68k"
444*4882a593Smuzhiyunendif
445*4882a593Smuzhiyun
446*4882a593Smuzhiyunif BR2_microblazeel || BR2_microblazebe
447*4882a593Smuzhiyunsource "arch/Config.in.microblaze"
448*4882a593Smuzhiyunendif
449*4882a593Smuzhiyun
450*4882a593Smuzhiyunif BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
451*4882a593Smuzhiyunsource "arch/Config.in.mips"
452*4882a593Smuzhiyunendif
453*4882a593Smuzhiyun
454*4882a593Smuzhiyunif BR2_nds32
455*4882a593Smuzhiyunsource "arch/Config.in.nds32"
456*4882a593Smuzhiyunendif
457*4882a593Smuzhiyun
458*4882a593Smuzhiyunif BR2_nios2
459*4882a593Smuzhiyunsource "arch/Config.in.nios2"
460*4882a593Smuzhiyunendif
461*4882a593Smuzhiyun
462*4882a593Smuzhiyunif BR2_or1k
463*4882a593Smuzhiyunsource "arch/Config.in.or1k"
464*4882a593Smuzhiyunendif
465*4882a593Smuzhiyun
466*4882a593Smuzhiyunif BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
467*4882a593Smuzhiyunsource "arch/Config.in.powerpc"
468*4882a593Smuzhiyunendif
469*4882a593Smuzhiyun
470*4882a593Smuzhiyunif BR2_riscv
471*4882a593Smuzhiyunsource "arch/Config.in.riscv"
472*4882a593Smuzhiyunendif
473*4882a593Smuzhiyun
474*4882a593Smuzhiyunif BR2_s390x
475*4882a593Smuzhiyunsource "arch/Config.in.s390x"
476*4882a593Smuzhiyunendif
477*4882a593Smuzhiyun
478*4882a593Smuzhiyunif BR2_sh
479*4882a593Smuzhiyunsource "arch/Config.in.sh"
480*4882a593Smuzhiyunendif
481*4882a593Smuzhiyun
482*4882a593Smuzhiyunif BR2_sparc || BR2_sparc64
483*4882a593Smuzhiyunsource "arch/Config.in.sparc"
484*4882a593Smuzhiyunendif
485*4882a593Smuzhiyun
486*4882a593Smuzhiyunif BR2_i386 || BR2_x86_64
487*4882a593Smuzhiyunsource "arch/Config.in.x86"
488*4882a593Smuzhiyunendif
489*4882a593Smuzhiyun
490*4882a593Smuzhiyunif BR2_xtensa
491*4882a593Smuzhiyunsource "arch/Config.in.xtensa"
492*4882a593Smuzhiyunendif
493*4882a593Smuzhiyun
494*4882a593Smuzhiyunendmenu # Target options
495