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/rk3399_rockchip-uboot/lib/zlib/
H A Dinffixed.h12 {0,9,192},{16,7,10},{0,8,96},{0,8,32},{0,9,160},{0,8,0},{0,8,128},
13 {0,8,64},{0,9,224},{16,7,6},{0,8,88},{0,8,24},{0,9,144},{19,7,59},
14 {0,8,120},{0,8,56},{0,9,208},{17,7,17},{0,8,104},{0,8,40},{0,9,176},
15 {0,8,8},{0,8,136},{0,8,72},{0,9,240},{16,7,4},{0,8,84},{0,8,20},
16 {21,8,227},{19,7,43},{0,8,116},{0,8,52},{0,9,200},{17,7,13},{0,8,100},
17 {0,8,36},{0,9,168},{0,8,4},{0,8,132},{0,8,68},{0,9,232},{16,7,8},
18 {0,8,92},{0,8,28},{0,9,152},{20,7,83},{0,8,124},{0,8,60},{0,9,216},
19 {18,7,23},{0,8,108},{0,8,44},{0,9,184},{0,8,12},{0,8,140},{0,8,76},
20 {0,9,248},{16,7,3},{0,8,82},{0,8,18},{21,8,163},{19,7,35},{0,8,114},
21 {0,8,50},{0,9,196},{17,7,11},{0,8,98},{0,8,34},{0,9,164},{0,8,2},
[all …]
H A Dtrees.h23 {{241},{ 8}}, {{ 9},{ 8}}, {{137},{ 8}}, {{ 73},{ 8}}, {{201},{ 8}},
32 {{ 61},{ 8}}, {{189},{ 8}}, {{125},{ 8}}, {{253},{ 8}}, {{ 19},{ 9}},
33 {{275},{ 9}}, {{147},{ 9}}, {{403},{ 9}}, {{ 83},{ 9}}, {{339},{ 9}},
34 {{211},{ 9}}, {{467},{ 9}}, {{ 51},{ 9}}, {{307},{ 9}}, {{179},{ 9}},
35 {{435},{ 9}}, {{115},{ 9}}, {{371},{ 9}}, {{243},{ 9}}, {{499},{ 9}},
36 {{ 11},{ 9}}, {{267},{ 9}}, {{139},{ 9}}, {{395},{ 9}}, {{ 75},{ 9}},
37 {{331},{ 9}}, {{203},{ 9}}, {{459},{ 9}}, {{ 43},{ 9}}, {{299},{ 9}},
38 {{171},{ 9}}, {{427},{ 9}}, {{107},{ 9}}, {{363},{ 9}}, {{235},{ 9}},
39 {{491},{ 9}}, {{ 27},{ 9}}, {{283},{ 9}}, {{155},{ 9}}, {{411},{ 9}},
40 {{ 91},{ 9}}, {{347},{ 9}}, {{219},{ 9}}, {{475},{ 9}}, {{ 59},{ 9}},
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A Dsha1_ce_core.S95 add_update c, ev, k0, 8, 9, 10, 11, dgb
96 add_update c, od, k0, 9, 10, 11, 8
97 add_update c, ev, k0, 10, 11, 8, 9
98 add_update c, od, k0, 11, 8, 9, 10
99 add_update c, ev, k1, 8, 9, 10, 11
101 add_update p, od, k1, 9, 10, 11, 8
102 add_update p, ev, k1, 10, 11, 8, 9
103 add_update p, od, k1, 11, 8, 9, 10
104 add_update p, ev, k1, 8, 9, 10, 11
105 add_update p, od, k2, 9, 10, 11, 8
[all …]
/rk3399_rockchip-uboot/board/sunxi/
H A Ddram_timings_sun4i.h64 # elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333H @540MHz, timings: 9-8-8-20 */
65 .cas = 9,
70 # elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333H @552MHz, timings: 9-8-8-20 */
71 .cas = 9,
76 # elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333H @576MHz, timings: 9-8-8-21 */
77 .cas = 9,
82 # elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333H @600MHz, timings: 9-9-9-22 */
83 .cas = 9,
88 # elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333H @624MHz, timings: 9-9-9-23 */
89 .cas = 9,
[all …]
/rk3399_rockchip-uboot/tools/scripts/
H A Ddefine2mk.sed10 /^#define CONFIG_[A-Za-z0-9_][A-Za-z0-9_]*/ {
24 s/="\([0-9][0-9]*\)"/=\1/;
26 s/="\(-[1-9][0-9]*\)"/=\1/;
28 s/="\(0[Xx][0-9a-fA-F][0-9a-fA-F]*\)"/=\1/;
30 s/="\(CONFIG_[A-Za-z0-9_][A-Za-z0-9_]*\)"/=$(\1)/;
/rk3399_rockchip-uboot/scripts/
H A Dcheckstack.pl44 $x = "[0-9a-f]"; # hex character
45 $xs = "[0-9a-f ]"; # hex character or space
49 $re = qr/^.*stp.*sp,\#-([0-9]{1,8})\]\!/o;
52 $re = qr/.*sub.*sp, sp, #(([0-9]{2}|[3-9])[0-9]{2})/o;
61 $re = qr/.*adds.*r12=-(([0-9]{2}|[3-9])[0-9]{2}),r12/o;
65 $re = qr/.*(?:linkw %fp,|addaw )#-([0-9]{1,4})(?:,%sp)?$/o;
72 $re = qr/.*daddiu.*sp,sp,-(([0-9]{2}|[3-9])[0-9]{2})/o;
75 $re = qr/.*addiu.*sp,sp,-(([0-9]{2}|[3-9])[0-9]{2})/o;
90 $re = qr/.*(?:lay|ag?hi).*\%r15,-(([0-9]{2}|[3-9])[0-9]{2})
97 $re = qr/.*addi\.l.*r15,-(([0-9]{2}|[3-9])[0-9]{2}),r15/o;
[all …]
H A Dfit-msg.sh49 …strings ${IMG} | grep '\-g[0-9,a-f][0-9,a-f][0-9,a-f][0-9,a-f][0-9,a-f][0-9,a-f][0-9,a-f]' | sort …
/rk3399_rockchip-uboot/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier-pxs2.c22 static const int emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
24 static const int emmc_dat8_muxvals[] = {9, 9, 9, 9};
37 static const int ether_rmii_muxvals[] = {8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9};
57 static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_training_db.c57 { {6, 6, 8, 9, 0, 0, 0, 6, 6, 8, 0, 9, 6, 0, 6, 0} },
63 { {6, 5, 6, 8, 9, 0, 0, 5, 5, 6, 0, 8, 5, 0, 5, 0} },
65 { {6, 5, 7, 9, 10, 0, 0, 5, 5, 7, 0, 9, 5, 0, 5, 0} },
69 { {6, 5, 6, 8, 9, 11, 0, 5, 5, 6, 11, 8, 5, 0, 5, 0} },
73 { {6, 6, 7, 9, 11, 12, 0, 6, 6, 7, 12, 9, 6, 12, 6, 12} },
77 { {6, 5, 6, 7, 9, 10, 11, 5, 5, 6, 10, 7, 5, 11, 5, 11} },
79 { {6, 5, 6, 8, 9, 11, 12, 5, 5, 6, 11, 8, 5, 12, 5, 12} },
81 { {6, 5, 7, 9, 10, 12, 13, 5, 5, 7, 12, 9, 5, 13, 5, 13} },
83 { {6, 6, 7, 9, 11, 13, 14, 6, 6, 7, 13, 9, 6, 14, 6, 14} },
85 { {6, 6, 7, 9, 0, 0, 0, 6, 6, 7, 0, 9, 6, 0, 6, 0} },
[all …]
/rk3399_rockchip-uboot/drivers/rkflash/
H A Dsfc_nor.c16 { 0xc84013, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x05, 10, 9, 0 },
18 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
20 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
22 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
28 { 0xc86017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
30 { 0xc86018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 },
32 { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
38 { 0xc86019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1D, 16, 9, 0 },
49 { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
51 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
[all …]
/rk3399_rockchip-uboot/drivers/video/drm/
H A Dsamsung_mipi_dcphy.c46 #define M_MASK GENMASK(9, 0)
47 #define M(x) UPDATE(x, 9, 0)
73 #define EDGE_CON_DIR(x) UPDATE(x, 9, 9)
92 #define T_ULPS_EXIT(x) UPDATE(x, 9, 0)
627 {2660, 12, 47, 12, 12, 12, 21, 11, 9, 18, 14},
628 {2650, 12, 46, 12, 11, 12, 21, 11, 9, 18, 14},
629 {2640, 12, 46, 12, 11, 12, 21, 11, 9, 18, 14},
630 {2630, 12, 46, 12, 11, 12, 21, 11, 9, 18, 14},
631 {2620, 12, 46, 12, 11, 12, 21, 10, 9, 18, 14},
632 {2610, 12, 45, 12, 11, 12, 21, 10, 9, 17, 14},
[all …]
/rk3399_rockchip-uboot/board/freescale/b4860qds/
H A Db4860qds_crossbar_con.h13 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
14 {5, 11}, {4, 5}, {2, 6}, {12, 9} };
16 static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
20 {7, 8}, {9, 0}, {2, 14}, {12, 15},
24 {7, 8}, {9, 0}, {5, 14}, {4, 15},
28 {7, 8}, {9, 0}, {5, 14},
39 static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
40 {11, 11}, {5, 10}, {6, 3}, {9, 12} };
42 static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
46 {7, 8}, {1, 9}, {14, 3}, {15, 12},
[all …]
/rk3399_rockchip-uboot/include/dt-bindings/clock/
H A Drockchip-ddr.h28 #define DDR3_1333H (7) /* 9-9-9 */
30 #define DDR3_1600G (9) /* 8-8-8 */
31 #define DDR3_1600H (10) /* 9-9-9 */
56 #define DDR4_2400P (9) /* 15-15-15 */
H A Dexynos7420-clk.h22 #define DOUT_SCLK_AUD_PLL 9
46 #define CLK_SCLK_SPI2 9
65 #define CLK_ACLK_FSYS0_200 9
89 #define PCLK_HSI2C11 9
104 #define PCLK_HSI2C6 9
142 #define ACLK_PDMA0 9
155 #define PHYCLK_UFS20_RX0_SYMBOL_USER 9
173 #define ACLK_AXI2ACEL_BRIDGE 9
H A Dstih407-clks.h25 #define CLK_TX_ICN_DMU 9
26 #define CLK_TX_ICN_HVA 9
27 #define CLK_TX_ICN_TS 9
28 #define CLK_ICN_COMPO 9
73 #define CLK_HDDAC 9
/rk3399_rockchip-uboot/arch/arm/mach-davinci/
H A Dda850_pinmux.c123 { pinmux(9), 1, 0 }, /* EMA_D[7] */
124 { pinmux(9), 1, 1 }, /* EMA_D[6] */
125 { pinmux(9), 1, 2 }, /* EMA_D[5] */
126 { pinmux(9), 1, 3 }, /* EMA_D[4] */
127 { pinmux(9), 1, 4 }, /* EMA_D[3] */
128 { pinmux(9), 1, 5 }, /* EMA_D[2] */
129 { pinmux(9), 1, 6 }, /* EMA_D[1] */
130 { pinmux(9), 1, 7 }, /* EMA_D[0] */
147 { pinmux(8), 1, 6 }, /* EMA_D[9] */
149 { pinmux(9), 1, 0 }, /* EMA_D[7] */
[all …]
/rk3399_rockchip-uboot/doc/
H A DREADME.davinci.nand_spl34 00000800 14 00 00 ea 14 f0 9f e5 10 f0 9f e5 0c f0 9f e5 |................|
35 00000810 08 f0 9f e5 04 f0 9f e5 00 f0 9f e5 04 f0 1f e5 |................|
42 00003800 14 00 00 ea 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
43 00003810 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 14 f0 9f e5 |................|
/rk3399_rockchip-uboot/board/freescale/mpc8568mds/
H A Dbcsr.c27 bcsr[9] |= 0x01; in enable_8568mds_flash_write()
34 bcsr[9] &= ~(0x01); in disable_8568mds_flash_write()
51 out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN); in reset_8568mds_uccs()
59 out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN); in reset_8568mds_uccs()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk3588-vccio3-pinctrl.dtsi152 <4 RK_PC5 9 &pcfg_pull_none_smt>,
154 <4 RK_PC6 9 &pcfg_pull_none_smt>;
162 <2 RK_PC1 9 &pcfg_pull_none_smt>,
164 <2 RK_PC0 9 &pcfg_pull_none_smt>;
172 <2 RK_PB2 9 &pcfg_pull_none_smt>,
174 <2 RK_PB3 9 &pcfg_pull_none_smt>;
182 <2 RK_PB5 9 &pcfg_pull_none_smt>,
184 <2 RK_PB4 9 &pcfg_pull_none_smt>;
192 <2 RK_PB6 9 &pcfg_pull_none_smt>,
194 <2 RK_PB7 9 &pcfg_pull_none_smt>;
[all …]
H A Drk3576-pinctrl.dtsi164 <0 RK_PA2 9 &pcfg_pull_none>;
258 <0 RK_PC5 9 &pcfg_pull_none>;
1433 <4 RK_PC0 9 &pcfg_pull_none>,
1435 <4 RK_PC1 9 &pcfg_pull_none>;
1441 <0 RK_PC3 9 &pcfg_pull_none>,
1443 <0 RK_PB6 9 &pcfg_pull_none>;
1449 <4 RK_PC2 9 &pcfg_pull_none>;
1454 <4 RK_PC3 9 &pcfg_pull_none>;
1470 <0 RK_PC1 9 &pcfg_pull_none_smt>,
1472 <0 RK_PC2 9 &pcfg_pull_none_smt>;
[all …]
/rk3399_rockchip-uboot/include/usb/
H A Dfusbh200.h18 uint32_t data[9];
35 #define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */
36 #define BMCSR_SPD_LOW (1 << 9)
37 #define BMCSR_SPD_FULL (0 << 9)
38 #define BMCSR_SPD_MASK (3 << 9)
39 #define BMCSR_SPD_SHIFT 9
40 #define BMCSR_SPD(x) ((x >> 9) & 0x03)
/rk3399_rockchip-uboot/tools/kermit/
H A Ddot.kermrc13 define sz !sz \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
14 define rz !rz \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
15 define sx !sx \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
16 define rx !rx \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3368-dmc.txt27 DDR3_1333H (9-9-9)
30 DDR3_1600H (9-9-9)
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/dram/
H A Dddrphy-regs.h24 #define PHY_PIR_WL BIT(9) /* Write Leveling */
48 #define PHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
81 #define PHY_DXCCR_DQSNRES_OPEN (0 << 9)
82 #define PHY_DXCCR_DQSNRES_688_OHM (1 << 9)
83 #define PHY_DXCCR_DQSNRES_611_OHM (2 << 9)
84 #define PHY_DXCCR_DQSNRES_550_OHM (3 << 9)
85 #define PHY_DXCCR_DQSNRES_500_OHM (4 << 9)
86 #define PHY_DXCCR_DQSNRES_458_OHM (5 << 9)
87 #define PHY_DXCCR_DQSNRES_393_OHM (6 << 9)
88 #define PHY_DXCCR_DQSNRES_344_OHM (7 << 9)
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-typec.c42 #define TX_TXCC_MGNFS_MULT_000(n) ((0x4050 | ((n) << 9)) << 2)
43 #define XCVR_DIAG_PLLDRC_CTRL(n) ((0x40e0 | ((n) << 9)) << 2)
44 #define XCVR_DIAG_BIDI_CTRL(n) ((0x40e8 | ((n) << 9)) << 2)
45 #define XCVR_DIAG_LANE_FCM_EN_MGN(n) ((0x40f2 | ((n) << 9)) << 2)
46 #define TX_PSC_A0(n) ((0x4100 | ((n) << 9)) << 2)
47 #define TX_PSC_A1(n) ((0x4101 | ((n) << 9)) << 2)
48 #define TX_PSC_A2(n) ((0x4102 | ((n) << 9)) << 2)
49 #define TX_PSC_A3(n) ((0x4103 | ((n) << 9)) << 2)
50 #define TX_RCVDET_CTRL(n) ((0x4120 | ((n) << 9)) << 2)
51 #define TX_RCVDET_EN_TMR(n) ((0x4122 | ((n) << 9)) << 2)
[all …]

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