Home
last modified time | relevance | path

Searched +full:8 +full:- +full:channel (Results 1 – 25 of 1138) sorted by relevance

12345678910>>...46

/OK3568_Linux_fs/yocto/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dcz-All2 # Created from http://www.ctu.cz/cs/download/plan-vyuziti-radioveho-spektra/rok_2012/pv-p_10-08_201…
4 [CHANNEL]
11 TRANSMISSION_MODE = 8K
12 GUARD_INTERVAL = 1/8
16 [CHANNEL]
23 TRANSMISSION_MODE = 8K
24 GUARD_INTERVAL = 1/8
28 [CHANNEL]
35 TRANSMISSION_MODE = 8K
36 GUARD_INTERVAL = 1/8
[all …]
H A Dit-All1 # This file lists all frequencies used in Western Europe for DVB-T.
4 # Moreover, other countries use a bandwidth of 8 MHz also for Band III
16 ### VHF - Band III ###
18 [CHANNEL]
25 TRANSMISSION_MODE = 8K
31 [CHANNEL]
38 TRANSMISSION_MODE = 8K
44 [CHANNEL]
51 TRANSMISSION_MODE = 8K
56 # 8
[all …]
H A Dnl-All2 # Created from http://radio-tv-nederland.nl/TV 1.251978e-312nderlijst%20Nederland.xls
3 # and http://radio-tv-nederland.nl/dvbt/dvbt-lokaal.html
4 [CHANNEL]
11 TRANSMISSION_MODE = 8K
16 [CHANNEL]
23 TRANSMISSION_MODE = 8K
28 [CHANNEL]
35 TRANSMISSION_MODE = 8K
40 [CHANNEL]
47 TRANSMISSION_MODE = 8K
[all …]
H A Dat-All1 # Austria, all DVB-T transmitters run by ORS
3 # http://www.ors.at/fileadmin/user_upload/downloads/DVB-T_Kanalbezeichnungen_und_Mittenfrequenzen.p…
4 [CHANNEL]
11 TRANSMISSION_MODE = 8K
16 [CHANNEL]
23 TRANSMISSION_MODE = 8K
28 [CHANNEL]
35 TRANSMISSION_MODE = 8K
40 [CHANNEL]
47 TRANSMISSION_MODE = 8K
[all …]
H A Dch-Citycable1 # Lausanne - Switzerland (DVB-T on CityCable cable network)
2 [CHANNEL]
6 CODE_RATE_HP = 7/8
9 TRANSMISSION_MODE = 8K
14 [CHANNEL]
18 CODE_RATE_HP = 7/8
21 TRANSMISSION_MODE = 8K
26 [CHANNEL]
30 CODE_RATE_HP = 7/8
33 TRANSMISSION_MODE = 8K
[all …]
H A Dee-All3 # and http://wiki.wifi.ee/index.php/DVB-T#Tehniline_teave
5 [CHANNEL]
12 TRANSMISSION_MODE = 8K
13 GUARD_INTERVAL = 1/8
17 [CHANNEL]
24 TRANSMISSION_MODE = 8K
25 GUARD_INTERVAL = 1/8
29 [CHANNEL]
36 TRANSMISSION_MODE = 8K
37 GUARD_INTERVAL = 1/8
[all …]
H A Ddk-All2 # Created from http://www.digi-tv.dk/Indhold_og_tilbud/frekvenser.asp
3 # and http://www.digi-tv.dk/Sendenettets_opbygning/
4 [CHANNEL]
11 TRANSMISSION_MODE = 8K
16 [CHANNEL]
23 TRANSMISSION_MODE = 8K
28 [CHANNEL]
35 TRANSMISSION_MODE = 8K
40 [CHANNEL]
47 TRANSMISSION_MODE = 8K
[all …]
H A Dch-Geneva3 #------------------------------------------------------------------------------
4 [CHANNEL]
11 TRANSMISSION_MODE = 8K
16 [CHANNEL]
23 TRANSMISSION_MODE = 8K
28 [CHANNEL]
35 TRANSMISSION_MODE = 8K
36 GUARD_INTERVAL = 1/8
40 [CHANNEL]
47 TRANSMISSION_MODE = 8K
[all …]
/OK3568_Linux_fs/yocto/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-s/
H A DAnik-F3-119W1 #Dish Network USA works with PSK/8turbo
2 #Just DVBS-USB Genpix Sky Walker 1 or 2 works with PSK/8turbo
4 [CHANNEL]
10 MODULATION = PSK/8
13 [CHANNEL]
19 MODULATION = PSK/8
22 [CHANNEL]
28 MODULATION = PSK/8
31 [CHANNEL]
37 MODULATION = PSK/8
[all …]
H A DIntelsat34_C-55.5W1 # Intelsat 34 @ 55.5W C-BAND
4 [CHANNEL]
13 [CHANNEL]
22 [CHANNEL]
31 [CHANNEL]
40 [CHANNEL]
49 [CHANNEL]
58 [CHANNEL]
64 MODULATION = PSK/8
67 [CHANNEL]
[all …]
H A DEchostar-10+11-110W1 #Dish Network USA works with PSK/8turbo
2 #Just DVBS-USB Genpix Sky Walker 1 or 2 works with PSK/8turbo
4 [CHANNEL]
10 MODULATION = PSK/8
13 [CHANNEL]
19 MODULATION = PSK/8
22 [CHANNEL]
28 MODULATION = PSK/8
31 [CHANNEL]
40 [CHANNEL]
[all …]
H A DIntelsat21_C-58.0W1 # Intelsat 21 @ 58.0W C-BAND
4 [CHANNEL]
10 MODULATION = PSK/8
13 [CHANNEL]
19 MODULATION = PSK/8
22 [CHANNEL]
31 [CHANNEL]
40 [CHANNEL]
45 INNER_FEC = 7/8
49 [CHANNEL]
[all …]
H A DGalaxy19_C-97.0W1 # Galaxy 19 @ 97W C-BAND
3 [CHANNEL]
9 MODULATION = PSK/8
12 [CHANNEL]
21 [CHANNEL]
27 MODULATION = PSK/8
30 [CHANNEL]
36 MODULATION = PSK/8
39 [CHANNEL]
48 [CHANNEL]
[all …]
/OK3568_Linux_fs/kernel/drivers/ptp/
H A Dptp_clockmatrix.c1 // SPDX-License-Identifier: GPL-2.0+
23 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
29 * over-rides any automatic selection
38 struct idtcm_channel *channel = in set_write_phase_ready() local
41 channel->write_phase_ready = 1; in set_write_phase_ready()
57 /* Sub-nanoseconds are in buf[0]. */ in char_array_to_timespec()
60 nsec <<= 8; in char_array_to_timespec()
61 nsec |= buf[3 - i]; in char_array_to_timespec()
66 sec <<= 8; in char_array_to_timespec()
67 sec |= buf[9 - i]; in char_array_to_timespec()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/bcm/
H A Dclk-ns2.c16 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/bcm-ns2.h>
22 #include "clk-iproc.h"
59 .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
62 .mdiv = REG_VAL(0x18, 0, 8),
65 .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
68 .mdiv = REG_VAL(0x18, 8, 8),
71 .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
74 .mdiv = REG_VAL(0x14, 0, 8),
77 .channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
[all …]
H A Dclk-cygnus.c16 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/bcm-cygnus.h>
24 #include "clk-iproc.h"
55 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
73 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
76 .mdiv = REG_VAL(0x20, 0, 8),
79 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
82 .mdiv = REG_VAL(0x20, 10, 8),
85 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
87 .enable = ENABLE_VAL(0x4, 8, 2, 14),
[all …]
/OK3568_Linux_fs/kernel/sound/core/oss/
H A Dlinear.c2 * Linear conversion Plug-In
4 * Abramo Bagnara <abramo@alsa-project.org>
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48 memcpy(p + data->copy_ofs, src + data->src_ofs, data->copy_bytes); in do_convert()
49 if (data->cvt_endian) in do_convert()
51 tmp ^= data->flip; in do_convert()
52 memcpy(dst, p + data->dst_ofs, data->dst_bytes); in do_convert()
60 struct linear_priv *data = (struct linear_priv *)plugin->extra_data; in convert()
61 int channel; in convert() local
62 int nchannels = plugin->src_format.channels; in convert()
[all …]
H A Dmulaw.c2 * Mu-Law conversion Plug-In Interface
4 * Uros Bizjak <uros@kss-loka.si>
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define SIGN_BIT (0x80) /* Sign bit for a u-law byte. */
31 #define NSEGS (8) /* Number of u-law segments. */
55 * linear2ulaw() - Convert a linear PCM value to u-law
58 * is biased by adding 33 which shifts the encoding range from (0 - 8158) to
59 * (33 - 8191). The result can be seen in the following encoding table:
62 * ------------------------ ---------------
75 * four bits wxyz. * The trailing bits (a - h) are ignored.
[all …]
H A Drate.c2 * Rate conversion Plug-In
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define R_MASK (BITS-1)
55 unsigned int channel; in rate_init() local
56 struct rate_priv *data = (struct rate_priv *)plugin->extra_data; in rate_init()
57 data->pos = 0; in rate_init()
58 for (channel = 0; channel < plugin->src_format.channels; channel++) { in rate_init()
59 data->channels[channel].last_S1 = 0; in rate_init()
60 data->channels[channel].last_S2 = 0; in rate_init()
73 unsigned int channel; in resample_expand() local
[all …]
/OK3568_Linux_fs/kernel/sound/soc/sprd/
H A Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
57 /* Channel water mark definition */
60 #define MCDT_CH_FIFO_AF_MASK GENMASK(8, 0)
62 /* DMA channel select definition */
67 #define MCDT_DMA_CH2_SEL_MASK GENMASK(11, 8)
68 #define MCDT_DMA_CH2_SEL_SHIFT 8
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3399.c2 * (C) Copyright 2016-2017 Rockchip Inc.
4 * SPDX-License-Identifier: GPL-2.0
12 #include <dt-structs.h>
53 #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
78 #include "sdram-rk3399-lpddr4-400.inc"
79 #include "sdram-rk3399-lpddr4-800.inc"
82 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
83 ((n) << (8 + (ch) * 4)))
86 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, in rkclk_ddr_reset() argument
89 channel &= 0x1; in rkclk_ddr_reset()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Deeprom.c1 // SPDX-License-Identifier: ISC
17 void *src = dev->mt76.eeprom.data + MT_EE_MAC_ADDR; in mt76x2_eeprom_get_macaddr()
19 memcpy(dev->mt76.macaddr, src, ETH_ALEN); in mt76x2_eeprom_get_macaddr()
80 struct device_node *np = dev->mt76.dev->of_node; in mt76x2_apply_cal_free_data()
81 u8 *eeprom = dev->mt76.eeprom.data; in mt76x2_apply_cal_free_data()
91 if (!np || !of_property_read_bool(np, "mediatek,eeprom-merge-otp")) in mt76x2_apply_cal_free_data()
116 eeprom[MT_EE_BT_VCDL_CALIBRATION + 1] = val >> 8; in mt76x2_apply_cal_free_data()
125 u16 val = get_unaligned_le16(dev->mt76.eeprom.data); in mt76x2_check_eeprom()
128 val = get_unaligned_le16(dev->mt76.eeprom.data + MT_EE_PCI_ID); in mt76x2_check_eeprom()
135 dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n", val); in mt76x2_check_eeprom()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/
H A Dipu_common.c2 * Porting to u-boot:
9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
11 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/arch/imx-regs.h>
41 (((struct ipu_ch_param *)(base))->word[(w)].data)
47 if (((bit) + (size) - 1) / 32 > i) { \
48 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
55 u32 mask = (1UL << size) - 1; \
59 if (((bit) + (size) - 1) / 32 > i) { \
61 temp &= ~(mask >> (32 - off)); \
[all …]
/OK3568_Linux_fs/kernel/sound/pci/emu10k1/
H A Dp16v.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
8 * Output fixed at S32_LE, 2 channel to hw:0,0
15 * Use 2 channel output streams instead of 8 channel.
16 * (8 channel output streams might be good for ASIO type output)
17 * Corrected speaker output, so Front -> Front etc.
36 * Merging with snd-emu10k1 driver.
38 * One stereo channel at 24bit now works.
42 * Integrated with snd-emu10k1 driver.
50 * setting HD Capture channel to 0 captures from CDROM digital input.
[all …]

12345678910>>...46