Lines Matching +full:8 +full:- +full:channel
2 * (C) Copyright 2016-2017 Rockchip Inc.
4 * SPDX-License-Identifier: GPL-2.0
12 #include <dt-structs.h>
53 #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
78 #include "sdram-rk3399-lpddr4-400.inc"
79 #include "sdram-rk3399-lpddr4-800.inc"
82 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
83 ((n) << (8 + (ch) * 4)))
86 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, in rkclk_ddr_reset() argument
89 channel &= 0x1; in rkclk_ddr_reset()
92 writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | in rkclk_ddr_reset()
93 CRU_SFTRST_DDR_PHY(channel, phy), in rkclk_ddr_reset()
94 &cru->softrst_con[4]); in rkclk_ddr_reset()
98 u32 channel) in phy_pctrl_reset() argument
100 rkclk_ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
102 rkclk_ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
104 rkclk_ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
111 u32 *denali_phy = ddr_publ_regs->denali_phy; in phy_dll_bypass_set()
116 setbits_le32(&denali_phy[86], (0x3 << 2) << 8); in phy_dll_bypass_set()
117 setbits_le32(&denali_phy[214], (0x3 << 2) << 8); in phy_dll_bypass_set()
118 setbits_le32(&denali_phy[342], (0x3 << 2) << 8); in phy_dll_bypass_set()
119 setbits_le32(&denali_phy[470], (0x3 << 2) << 8); in phy_dll_bypass_set()
127 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8); in phy_dll_bypass_set()
128 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8); in phy_dll_bypass_set()
129 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8); in phy_dll_bypass_set()
130 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8); in phy_dll_bypass_set()
139 static void set_memory_map(const struct chan_info *chan, u32 channel, in set_memory_map() argument
143 &sdram_params->ch[channel]; in set_memory_map()
144 u32 *denali_ctl = chan->pctl->denali_ctl; in set_memory_map()
145 u32 *denali_pi = chan->pi->denali_pi; in set_memory_map()
151 if (sdram_ch->cap_info.ddrconfig < 2 || in set_memory_map()
152 sdram_ch->cap_info.ddrconfig == 4) in set_memory_map()
154 else if (sdram_ch->cap_info.ddrconfig == 3 || in set_memory_map()
155 sdram_ch->cap_info.ddrconfig == 5) in set_memory_map()
160 cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1; in set_memory_map()
161 reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1; in set_memory_map()
164 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col)); in set_memory_map()
166 ((3 - sdram_ch->cap_info.bk) << 16) | in set_memory_map()
167 ((16 - row) << 24)); in set_memory_map()
173 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col)); in set_memory_map()
177 ((3 - sdram_ch->cap_info.bk) << 16) | in set_memory_map()
178 ((16 - row) << 24)); in set_memory_map()
179 if (sdram_params->base.dramtype == LPDDR4) { in set_memory_map()
190 if (sdram_ch->cap_info.rank == 1 && in set_memory_map()
191 sdram_params->base.dramtype == DDR3) in set_memory_map()
197 u32 b_reg, u32 channel) in phy_io_config() argument
212 denali_phy = chan->publ->denali_phy; in phy_io_config()
213 denali_ctl = chan->pctl->denali_ctl; in phy_io_config()
215 denali_phy = sdram_params->phy_regs.denali_phy; in phy_io_config()
216 denali_ctl = sdram_params->pctl_regs.denali_ctl; in phy_io_config()
220 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
226 vref_value_dq = (rd_vref - 3300) / 521; in phy_io_config()
232 vref_value_dq = (rd_vref - 15300) / 521; in phy_io_config()
237 } else if (sdram_params->base.dramtype == LPDDR3) { in phy_io_config()
239 if (sdram_params->base.odt == 1) { in phy_io_config()
287 } else if (sdram_params->base.dramtype == DDR3) { in phy_io_config()
295 reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; in phy_io_config()
297 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); in phy_io_config()
305 reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; in phy_io_config()
327 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
332 clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8); in phy_io_config()
350 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
355 clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8); in phy_io_config()
361 clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8); in phy_io_config()
363 clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8); in phy_io_config()
365 clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8); in phy_io_config()
367 clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8); in phy_io_config()
369 clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8); in phy_io_config()
373 if (sdram_params->base.ddr_freq < 400 * MHz) in phy_io_config()
375 else if (sdram_params->base.ddr_freq < 800 * MHz) in phy_io_config()
377 else if (sdram_params->base.ddr_freq < 1200 * MHz) in phy_io_config()
399 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
454 41, /* rd_vref; (unit %, range 3.3% - 48.7%) */
472 41, /* rd_vref; (unit %, range 3.3% - 48.7%) */
489 17, /* rd_vref; (unit %, range 3.3% - 48.7%) */
506 17, /* rd_vref; (unit %, range 3.3% - 48.7%) */
518 if (io->mr5 != 0) { in get_io_set()
519 if (io->mhz >= sdram_params->base.ddr_freq && in get_io_set()
520 io->mr5 == mr5) in get_io_set()
523 if (io->mhz >= sdram_params->base.ddr_freq) in get_io_set()
533 * if b_reg = 0, channel, mr5 are not care
537 u32 channel, u32 mr5) in set_ds_odt() argument
552 denali_phy = chan->publ->denali_phy; in set_ds_odt()
553 denali_ctl = chan->pctl->denali_ctl; in set_ds_odt()
555 denali_phy = sdram_params->phy_regs.denali_phy; in set_ds_odt()
556 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_ds_odt()
559 if (sdram_params->base.dramtype == LPDDR4) { in set_ds_odt()
563 tsel_rd_select_n = io->rd_odt; in set_ds_odt()
568 tsel_wr_select_dq_p = io->wr_dq_drv; in set_ds_odt()
571 tsel_wr_select_ca_p = io->wr_ca_drv; in set_ds_odt()
574 tsel_ckcs_select_p = io->wr_ckcs_drv; in set_ds_odt()
605 } else if (sdram_params->base.dramtype == LPDDR3) { in set_ds_odt()
637 if (sdram_params->base.dramtype == LPDDR4) { in set_ds_odt()
638 if (sdram_params->base.odt == 1) { in set_ds_odt()
639 tsel_rd_en = io->rd_odt_en; in set_ds_odt()
646 tsel_rd_en = sdram_params->base.odt; in set_ds_odt()
674 (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) | in set_ds_odt()
691 /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ in set_ds_odt()
693 if (sdram_params->base.dramtype == LPDDR4) { in set_ds_odt()
697 writel((0x300 << 8) | reg_value, &denali_phy[544]); in set_ds_odt()
698 writel((0x300 << 8) | reg_value, &denali_phy[672]); in set_ds_odt()
699 writel((0x300 << 8) | reg_value, &denali_phy[800]); in set_ds_odt()
706 /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ in set_ds_odt()
709 /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ in set_ds_odt()
713 /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ in set_ds_odt()
716 /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ in set_ds_odt()
720 /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ in set_ds_odt()
747 reg_value = tsel_wr_en << 8; in set_ds_odt()
748 clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); in set_ds_odt()
749 clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); in set_ds_odt()
750 clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); in set_ds_odt()
767 if (sdram_params->base.dramtype == LPDDR4) in set_ds_odt()
768 phy_io_config(chan, sdram_params, io->rd_vref, b_reg, channel); in set_ds_odt()
770 phy_io_config(chan, sdram_params, 0, b_reg, channel); in set_ds_odt()
777 const struct chan_info *chan_0 = &dram->chan[0]; in pctl_start()
778 const struct chan_info *chan_1 = &dram->chan[1]; in pctl_start()
780 u32 *denali_ctl_0 = chan_0->pctl->denali_ctl; in pctl_start()
781 u32 *denali_phy_0 = chan_0->publ->denali_phy; in pctl_start()
782 u32 *denali_ctl_1 = chan_1->pctl->denali_ctl; in pctl_start()
783 u32 *denali_phy_1 = chan_1->publ->denali_phy; in pctl_start()
788 writel(0x01000000, &dram->grf->ddrc0_con0); in pctl_start()
796 printf("channel 0 init err!\n"); in pctl_start()
804 writel(0x01000100, &dram->grf->ddrc0_con0); in pctl_start()
825 writel(0x01000000, &dram->grf->ddrc1_con0); in pctl_start()
832 printf("channel 1 init err!\n"); in pctl_start()
840 writel(0x01000100, &dram->grf->ddrc1_con0); in pctl_start()
861 * restore channel 1 RESET original setting in pctl_start()
864 if (sdram_params->base.dramtype == LPDDR4) in pctl_start()
866 sdram_params->phy_regs.denali_phy[937] & in pctl_start()
892 * if b_reg = 0, channel, mr5 are not care
896 u32 en, u32 b_reg, u32 channel, u32 mr5) in set_lp4_dq_odt() argument
904 denali_pi = chan->pi->denali_pi; in set_lp4_dq_odt()
905 denali_ctl = chan->pctl->denali_ctl; in set_lp4_dq_odt()
907 denali_pi = sdram_params->pi_regs.denali_pi; in set_lp4_dq_odt()
908 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_lp4_dq_odt()
912 reg_value = io->dq_odt; in set_lp4_dq_odt()
937 clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8)); in set_lp4_dq_odt()
938 clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8)); in set_lp4_dq_odt()
951 * if b_reg = 0, channel, mr5 are not care
955 u32 en, u32 b_reg, u32 channel, u32 mr5) in set_lp4_ca_odt() argument
963 denali_pi = chan->pi->denali_pi; in set_lp4_ca_odt()
964 denali_ctl = chan->pctl->denali_ctl; in set_lp4_ca_odt()
966 denali_pi = sdram_params->pi_regs.denali_pi; in set_lp4_ca_odt()
967 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_lp4_ca_odt()
971 reg_value = io->ca_odt; in set_lp4_ca_odt()
1010 * if b_reg = 0, channel, mr5 are not care
1014 u32 b_reg, u32 channel, u32 mr5) in set_lp4_MR3() argument
1022 denali_pi = chan->pi->denali_pi; in set_lp4_MR3()
1023 denali_ctl = chan->pctl->denali_ctl; in set_lp4_MR3()
1025 denali_pi = sdram_params->pi_regs.denali_pi; in set_lp4_MR3()
1026 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_lp4_MR3()
1030 reg_value = ((io->pdds << 3) | 1); in set_lp4_MR3()
1068 * if b_reg = 0, channel, mr5 are not care
1072 u32 b_reg, u32 channel, u32 mr5) in set_lp4_MR12() argument
1080 denali_pi = chan->pi->denali_pi; in set_lp4_MR12()
1081 denali_ctl = chan->pctl->denali_ctl; in set_lp4_MR12()
1083 denali_pi = sdram_params->pi_regs.denali_pi; in set_lp4_MR12()
1084 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_lp4_MR12()
1088 reg_value = io->ca_vref; in set_lp4_MR12()
1096 clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8); in set_lp4_MR12()
1098 clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8); in set_lp4_MR12()
1106 clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8); in set_lp4_MR12()
1108 clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8); in set_lp4_MR12()
1117 clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8); in set_lp4_MR12()
1119 clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8); in set_lp4_MR12()
1128 * if b_reg = 0, channel, mr5 are not care
1132 u32 b_reg, u32 channel, u32 mr5) in set_lp4_MR14() argument
1140 denali_pi = chan->pi->denali_pi; in set_lp4_MR14()
1141 denali_ctl = chan->pctl->denali_ctl; in set_lp4_MR14()
1143 denali_pi = sdram_params->pi_regs.denali_pi; in set_lp4_MR14()
1144 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_lp4_MR14()
1148 reg_value = io->dq_vref; in set_lp4_MR14()
1193 denali_ctl_params = sdram_params->pctl_regs.denali_ctl; in modify_param()
1194 denali_pi_params = sdram_params->pi_regs.denali_pi; in modify_param()
1195 denali_phy_params = sdram_params->phy_regs.denali_phy; in modify_param()
1197 if (sdram_params->base.dramtype == LPDDR4) { in modify_param()
1218 clrsetbits_le32(&denali_pi_params[45], 0x3 << 8, 0x3 << 8); in modify_param()
1241 static int pctl_cfg(const struct chan_info *chan, u32 channel, in pctl_cfg() argument
1244 u32 *denali_ctl = chan->pctl->denali_ctl; in pctl_cfg()
1245 u32 *denali_pi = chan->pi->denali_pi; in pctl_cfg()
1246 u32 *denali_phy = chan->publ->denali_phy; in pctl_cfg()
1247 const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl; in pctl_cfg()
1248 const u32 *params_phy = sdram_params->phy_regs.denali_phy; in pctl_cfg()
1259 sizeof(struct rk3399_ddr_pctl_regs) - 4); in pctl_cfg()
1263 * two channel init at the same time, then ZQ Cal Start in pctl_cfg()
1265 * to fix it: increase tINIT3 for channel 1, will avoid two in pctl_cfg()
1266 * channel ZQ Cal Start at the same time in pctl_cfg()
1268 if (sdram_params->base.dramtype == LPDDR4 && channel == 1) { in pctl_cfg()
1269 tmp = ((1000000 * (sdram_params->base.ddr_freq / MHz) + 999) / in pctl_cfg()
1275 sdram_copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], in pctl_cfg()
1278 set_memory_map(chan, channel, sdram_params); in pctl_cfg()
1280 writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]); in pctl_cfg()
1281 writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); in pctl_cfg()
1282 writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); in pctl_cfg()
1284 if (sdram_params->base.dramtype == LPDDR4) { in pctl_cfg()
1285 writel(sdram_params->phy_regs.denali_phy[898], in pctl_cfg()
1287 writel(sdram_params->phy_regs.denali_phy[919], in pctl_cfg()
1291 g_pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) & in pctl_cfg()
1304 if (sdram_params->base.dramtype != LPDDR4) { in pctl_cfg()
1318 sdram_copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); in pctl_cfg()
1319 sdram_copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4); in pctl_cfg()
1321 ¶ms_phy[128], (218 - 128 + 1) * 4); in pctl_cfg()
1323 ¶ms_phy[256], (346 - 256 + 1) * 4); in pctl_cfg()
1325 ¶ms_phy[384], (474 - 384 + 1) * 4); in pctl_cfg()
1327 ¶ms_phy[512], (549 - 512 + 1) * 4); in pctl_cfg()
1329 ¶ms_phy[640], (677 - 640 + 1) * 4); in pctl_cfg()
1331 ¶ms_phy[768], (805 - 768 + 1) * 4); in pctl_cfg()
1333 if (sdram_params->base.dramtype == LPDDR4) in pctl_cfg()
1338 clrsetbits_le32(¶ms->phy_regs.denali_phy[896], 0x3 << 8, in pctl_cfg()
1339 0 << 8); in pctl_cfg()
1340 writel(params->phy_regs.denali_phy[896], &denali_phy[896]); in pctl_cfg()
1342 writel(sdram_params->phy_regs.denali_phy[83] + (0x10 << 16), in pctl_cfg()
1344 writel(sdram_params->phy_regs.denali_phy[84] + (0x10 << 8), in pctl_cfg()
1346 writel(sdram_params->phy_regs.denali_phy[211] + (0x10 << 16), in pctl_cfg()
1348 writel(sdram_params->phy_regs.denali_phy[212] + (0x10 << 8), in pctl_cfg()
1350 writel(sdram_params->phy_regs.denali_phy[339] + (0x10 << 16), in pctl_cfg()
1352 writel(sdram_params->phy_regs.denali_phy[340] + (0x10 << 8), in pctl_cfg()
1354 writel(sdram_params->phy_regs.denali_phy[467] + (0x10 << 16), in pctl_cfg()
1356 writel(sdram_params->phy_regs.denali_phy[468] + (0x10 << 8), in pctl_cfg()
1359 if (sdram_params->base.dramtype == LPDDR4) { in pctl_cfg()
1367 0xfff << 8, tmp << 8); in pctl_cfg()
1370 * to workaround 366ball two channel's RESET connect to in pctl_cfg()
1373 if (channel == 1) in pctl_cfg()
1385 u32 *denali_phy = chan->publ->denali_phy; in select_per_cs_training_index()
1393 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); in select_per_cs_training_index()
1402 u32 *denali_ctl = chan->pctl->denali_ctl; in override_write_leveling_value()
1403 u32 *denali_phy = chan->publ->denali_phy; in override_write_leveling_value()
1413 clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); in override_write_leveling_value()
1426 clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); in override_write_leveling_value()
1429 static int data_training_ca(const struct chan_info *chan, u32 channel, in data_training_ca() argument
1432 u32 *denali_pi = chan->pi->denali_pi; in data_training_ca()
1433 u32 *denali_phy = chan->publ->denali_phy; in data_training_ca()
1436 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_ca()
1442 if (sdram_params->base.dramtype == LPDDR4) in data_training_ca()
1451 /* PI_100 PI_CALVL_EN:RW:8:2 */ in data_training_ca()
1452 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); in data_training_ca()
1460 /* PI_174 PI_INT_STATUS:RD:8:18 */ in data_training_ca()
1461 tmp = readl(&denali_pi[174]) >> 8; in data_training_ca()
1480 return -EIO; in data_training_ca()
1485 clrbits_le32(&denali_pi[100], 0x3 << 8); in data_training_ca()
1490 static int data_training_wl(const struct chan_info *chan, u32 channel, in data_training_wl() argument
1493 u32 *denali_pi = chan->pi->denali_pi; in data_training_wl()
1494 u32 *denali_phy = chan->publ->denali_phy; in data_training_wl()
1497 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_wl()
1504 /* PI_60 PI_WRLVL_EN:RW:8:2 */ in data_training_wl()
1505 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); in data_training_wl()
1506 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ in data_training_wl()
1508 (0x1 << 8) | (0x3 << 16), in data_training_wl()
1509 (0x1 << 8) | (i << 16)); in data_training_wl()
1513 /* PI_174 PI_INT_STATUS:RD:8:18 */ in data_training_wl()
1514 tmp = readl(&denali_pi[174]) >> 8; in data_training_wl()
1537 return -EIO; in data_training_wl()
1544 clrbits_le32(&denali_pi[60], 0x3 << 8); in data_training_wl()
1549 static int data_training_rg(const struct chan_info *chan, u32 channel, in data_training_rg() argument
1552 u32 *denali_pi = chan->pi->denali_pi; in data_training_rg()
1553 u32 *denali_phy = chan->publ->denali_phy; in data_training_rg()
1556 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_rg()
1575 /* PI_174 PI_INT_STATUS:RD:8:18 */ in data_training_rg()
1576 tmp = readl(&denali_pi[174]) >> 8; in data_training_rg()
1581 * PHY_GTLVL_STATUS_OBS_x:16:8 in data_training_rg()
1599 return -EIO; in data_training_rg()
1609 static int data_training_rl(const struct chan_info *chan, u32 channel, in data_training_rl() argument
1612 u32 *denali_pi = chan->pi->denali_pi; in data_training_rl()
1614 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_rl()
1623 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ in data_training_rl()
1625 (0x1 << 8) | (0x3 << 24), in data_training_rl()
1626 (0x1 << 8) | (i << 24)); in data_training_rl()
1630 /* PI_174 PI_INT_STATUS:RD:8:18 */ in data_training_rl()
1631 tmp = readl(&denali_pi[174]) >> 8; in data_training_rl()
1636 * phy_rdlvl_status_obs_X:16:8 in data_training_rl()
1638 if ((((tmp >> 8) & 0x1) == 0x1) && in data_training_rl()
1643 return -EIO; in data_training_rl()
1653 static int data_training_wdql(const struct chan_info *chan, u32 channel, in data_training_wdql() argument
1656 u32 *denali_pi = chan->pi->denali_pi; in data_training_wdql()
1658 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_wdql()
1664 if (sdram_params->base.dramtype == LPDDR4) in data_training_wdql()
1676 * PI_117 PI_WDQLVL_VREF_EN:RW:8:1 in data_training_wdql()
1678 clrbits_le32(&denali_pi[117], 0x1 << 8); in data_training_wdql()
1681 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ in data_training_wdql()
1683 (0x1 << 8) | (0x3 << 16), in data_training_wdql()
1684 (0x1 << 8) | (i << 16)); in data_training_wdql()
1688 /* PI_174 PI_INT_STATUS:RD:8:18 */ in data_training_wdql()
1689 tmp = readl(&denali_pi[174]) >> 8; in data_training_wdql()
1695 return -EIO; in data_training_wdql()
1705 static int data_training(const struct chan_info *chan, u32 channel, in data_training() argument
1709 u32 *denali_phy = chan->publ->denali_phy; in data_training()
1716 if (sdram_params->base.dramtype == LPDDR4) { in data_training()
1720 } else if (sdram_params->base.dramtype == LPDDR3) { in data_training()
1723 } else if (sdram_params->base.dramtype == DDR3) { in data_training()
1732 ret = data_training_ca(chan, channel, sdram_params); in data_training()
1739 ret = data_training_wl(chan, channel, sdram_params); in data_training()
1746 ret = data_training_rg(chan, channel, sdram_params); in data_training()
1753 ret = data_training_rl(chan, channel, sdram_params); in data_training()
1760 ret = data_training_wdql(chan, channel, sdram_params); in data_training()
1774 unsigned char channel, u32 ddrconfig) in set_ddrconfig() argument
1777 struct msch_regs *ddr_msch_regs = chan->msch; in set_ddrconfig()
1781 cs0_cap = (1 << (sdram_params->ch[channel].cap_info.cs0_row in set_ddrconfig()
1782 + sdram_params->ch[channel].cap_info.col in set_ddrconfig()
1783 + sdram_params->ch[channel].cap_info.bk in set_ddrconfig()
1784 + sdram_params->ch[channel].cap_info.bw - 20)); in set_ddrconfig()
1785 if (sdram_params->ch[channel].cap_info.rank > 1) in set_ddrconfig()
1786 cs1_cap = cs0_cap >> (sdram_params->ch[channel].cap_info.cs0_row in set_ddrconfig()
1787 - sdram_params->ch[channel].cap_info.cs1_row); in set_ddrconfig()
1788 if (sdram_params->ch[channel].cap_info.row_3_4) { in set_ddrconfig()
1793 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); in set_ddrconfig()
1794 writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8), in set_ddrconfig()
1795 &ddr_msch_regs->ddrsize); in set_ddrconfig()
1801 writel(noc_timings->ddrtiminga0.d32, in sdram_msch_config()
1802 &msch->ddrtiminga0.d32); in sdram_msch_config()
1803 writel(noc_timings->ddrtimingb0.d32, in sdram_msch_config()
1804 &msch->ddrtimingb0.d32); in sdram_msch_config()
1805 writel(noc_timings->ddrtimingc0.d32, in sdram_msch_config()
1806 &msch->ddrtimingc0.d32); in sdram_msch_config()
1807 writel(noc_timings->devtodev0.d32, in sdram_msch_config()
1808 &msch->devtodev0.d32); in sdram_msch_config()
1809 writel(noc_timings->ddrmode.d32, in sdram_msch_config()
1810 &msch->ddrmode.d32); in sdram_msch_config()
1818 unsigned int channel, idx; in dram_all_config() local
1820 for (channel = 0, idx = 0; in dram_all_config()
1821 (idx < sdram_params->base.num_channels) && (channel < 2); in dram_all_config()
1822 channel++) { in dram_all_config()
1826 if (sdram_params->ch[channel].cap_info.col == 0) in dram_all_config()
1829 sdram_org_config(&sdram_params->ch[channel].cap_info, in dram_all_config()
1830 &sdram_params->base, &sys_reg2, in dram_all_config()
1831 &sys_reg3, channel); in dram_all_config()
1832 ddr_msch_regs = dram->chan[channel].msch; in dram_all_config()
1833 noc_timing = &sdram_params->ch[channel].noc_timings; in dram_all_config()
1837 if (sdram_params->ch[channel].cap_info.rank == 1) in dram_all_config()
1838 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], in dram_all_config()
1842 writel(sys_reg2, &dram->pmugrf->os_reg2); in dram_all_config()
1843 writel(sys_reg3, &dram->pmugrf->os_reg3); in dram_all_config()
1844 rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, in dram_all_config()
1845 sdram_params->base.stride << 10); in dram_all_config()
1850 &dram->pmucru->pmucru_rstnhold_con[1]); in dram_all_config()
1851 clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); in dram_all_config()
1857 u32 channel; in switch_to_phy_index1() local
1859 u32 ch_count = sdram_params->base.num_channels; in switch_to_phy_index1()
1865 &dram->cic->cic_ctrl0); in switch_to_phy_index1()
1866 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) { in switch_to_phy_index1()
1871 return -ETIME; in switch_to_phy_index1()
1876 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0); in switch_to_phy_index1()
1877 while (!(readl(&dram->cic->cic_status0) & (1 << 0))) { in switch_to_phy_index1()
1881 return -ETIME; in switch_to_phy_index1()
1885 for (channel = 0; channel < ch_count; channel++) { in switch_to_phy_index1()
1886 denali_phy = dram->chan[channel].publ->denali_phy; in switch_to_phy_index1()
1887 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); in switch_to_phy_index1()
1888 ret = data_training(&dram->chan[channel], channel, in switch_to_phy_index1()
1919 u32 channel) in calculate_ddrconfig() argument
1922 unsigned int cs0_row = sdram_params->ch[channel].cap_info.cs0_row; in calculate_ddrconfig()
1923 unsigned int col = sdram_params->ch[channel].cap_info.col; in calculate_ddrconfig()
1924 unsigned int bw = sdram_params->ch[channel].cap_info.bw; in calculate_ddrconfig()
1926 col -= (bw == 2) ? 0 : 1; in calculate_ddrconfig()
1927 col -= 9; in calculate_ddrconfig()
1936 i = -1; in calculate_ddrconfig()
1944 unsigned int channel; in calculate_stride() local
1947 unsigned int stride = -1; in calculate_stride()
1952 for (channel = 0; channel < 2; channel++) { in calculate_stride()
1956 &sdram_params->ch[channel].cap_info; in calculate_stride()
1958 if (cap_info->col == 0) in calculate_stride()
1961 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + in calculate_stride()
1962 cap_info->bk + cap_info->bw - 20)); in calculate_stride()
1963 if (cap_info->rank > 1) in calculate_stride()
1964 cs1_cap = cs0_cap >> (cap_info->cs0_row in calculate_stride()
1965 - cap_info->cs1_row); in calculate_stride()
1966 if (cap_info->row_3_4) { in calculate_stride()
1970 ch_cap[channel] = cs0_cap + cs1_cap; in calculate_stride()
1971 chinfo |= 1 << channel; in calculate_stride()
1975 if (sdram_params->base.num_channels == 1) { in calculate_stride()
1976 if (chinfo & 1) /* channel a only */ in calculate_stride()
1978 else /* channel b only */ in calculate_stride()
1980 } else {/* 2 channel */ in calculate_stride()
1986 * if 786M+768M.useful space from 0-1280MB and in calculate_stride()
1987 * 1536MB-1792MB in calculate_stride()
1988 * if 1.5G+1.5G(continuous).useful space from 0-2560MB in calculate_stride()
1989 * and 3072MB-3584MB in calculate_stride()
2005 * useful space: 0-768MB 1GB-1792MB in calculate_stride()
2035 * remain two channel capability not equal OR capability in calculate_stride()
2038 if (stride == (-1)) { in calculate_stride()
2057 if (stride == (-1)) in calculate_stride()
2089 return (-1); in calculate_stride()
2096 val = (readl(&pmusgrf->soc_con4) >> 10) & 0x1F; in get_ddr_stride()
2103 rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, in set_ddr_stride()
2109 unsigned int channel) in set_cap_relate_config() argument
2111 u32 *denali_ctl = chan->pctl->denali_ctl; in set_cap_relate_config()
2115 if (sdram_params->base.dramtype == LPDDR3) { in set_cap_relate_config()
2116 tmp = (8 << sdram_params->ch[channel].cap_info.bw) / in set_cap_relate_config()
2117 (8 << sdram_params->ch[channel].cap_info.dbw); in set_cap_relate_config()
2119 * 1 -> 0, 2 -> 1, 4 -> 2 in set_cap_relate_config()
2123 clrsetbits_le32(&denali_ctl[198], 0x7 << 8, in set_cap_relate_config()
2124 (tmp >> 1) << 8); in set_cap_relate_config()
2126 noc_timing = &sdram_params->ch[channel].noc_timings; in set_cap_relate_config()
2131 if (sdram_params->ch[channel].cap_info.bw == 16 && in set_cap_relate_config()
2132 noc_timing->ddrmode.b.mwrsize == 2) { in set_cap_relate_config()
2133 if (noc_timing->ddrmode.b.burstsize) in set_cap_relate_config()
2134 noc_timing->ddrmode.b.burstsize -= 1; in set_cap_relate_config()
2135 noc_timing->ddrmode.b.mwrsize -= 1; in set_cap_relate_config()
2136 noc_timing->ddrtimingc0.b.burstpenalty *= 2; in set_cap_relate_config()
2137 noc_timing->ddrtimingc0.b.wrtomwr *= 2; in set_cap_relate_config()
2142 unsigned int channel) in clear_channel_params() argument
2144 sdram_params->ch[channel].cap_info.rank = 0; in clear_channel_params()
2145 sdram_params->ch[channel].cap_info.col = 0; in clear_channel_params()
2146 sdram_params->ch[channel].cap_info.bk = 0; in clear_channel_params()
2147 sdram_params->ch[channel].cap_info.bw = 32; in clear_channel_params()
2148 sdram_params->ch[channel].cap_info.dbw = 32; in clear_channel_params()
2149 sdram_params->ch[channel].cap_info.row_3_4 = 0; in clear_channel_params()
2150 sdram_params->ch[channel].cap_info.cs0_row = 0; in clear_channel_params()
2151 sdram_params->ch[channel].cap_info.cs1_row = 0; in clear_channel_params()
2152 sdram_params->ch[channel].cap_info.ddrconfig = 0; in clear_channel_params()
2163 u32 *denali_ctl = chan->pctl->denali_ctl; in dram_set_cs()
2164 u32 *denali_pi = chan->pi->denali_pi; in dram_set_cs()
2165 struct msch_regs *ddr_msch_regs = chan->msch; in dram_set_cs()
2168 writel((cs0_cap / 32) | (((4096 - cs0_cap) / 32) << 8), in dram_set_cs()
2169 &ddr_msch_regs->ddrsize); in dram_set_cs()
2187 u32 *denali_ctl = chan->pctl->denali_ctl; in dram_set_bw()
2197 u32 *denali_ctl = chan->pctl->denali_ctl; in dram_set_max_col()
2198 struct msch_regs *ddr_msch_regs = chan->msch; in dram_set_max_col()
2199 u32 *denali_pi = chan->pi->denali_pi; in dram_set_max_col()
2205 ((16 - ((bw == 2) ? 14 : 15)) << 24)); in dram_set_max_col()
2211 ((16 - 12) << 24)); in dram_set_max_col()
2213 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); in dram_set_max_col()
2215 writel((4096 / 32) | ((0 / 32) << 8), in dram_set_max_col()
2216 &ddr_msch_regs->ddrsize); in dram_set_max_col()
2224 u32 *denali_ctl = chan->pctl->denali_ctl; in dram_set_max_bank()
2225 u32 *denali_pi = chan->pi->denali_pi; in dram_set_max_bank()
2241 u32 *denali_ctl = chan->pctl->denali_ctl; in dram_set_max_row()
2242 u32 *denali_pi = chan->pi->denali_pi; in dram_set_max_row()
2243 struct msch_regs *ddr_msch_regs = chan->msch; in dram_set_max_row()
2245 clrsetbits_le32(&denali_ctl[191], 0xf, 12 - 10); in dram_set_max_row()
2249 clrsetbits_le32(&denali_pi[199], 0xf, 12 - 10); in dram_set_max_row()
2253 writel(1 | (1 << 8), &ddr_msch_regs->ddrconf); in dram_set_max_row()
2255 writel((4096 / 32) | ((0 / 32) << 8), in dram_set_max_row()
2256 &ddr_msch_regs->ddrsize); in dram_set_max_row()
2265 unsigned char channel) in dram_detect_cap() argument
2267 const struct chan_info *chan = &dram->chan[channel]; in dram_detect_cap()
2268 struct sdram_cap_info *cap_info = &sdram_params->ch[channel].cap_info; in dram_detect_cap()
2279 if (sdram_params->base.dramtype != LPDDR4) { in dram_detect_cap()
2281 cap_info->bw = bw; in dram_detect_cap()
2282 if (data_training(chan, channel, sdram_params, in dram_detect_cap()
2286 cap_info->bw = bw; in dram_detect_cap()
2287 if (data_training(chan, channel, sdram_params, in dram_detect_cap()
2298 if (sdram_params->base.dramtype == LPDDR3) in dram_detect_cap()
2303 if (sdram_params->base.dramtype != LPDDR4) { in dram_detect_cap()
2304 if (data_training(chan, channel, sdram_params, training_flag)) { in dram_detect_cap()
2328 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + cap_info->bk + in dram_detect_cap()
2329 cap_info->bw - 20)); in dram_detect_cap()
2330 if (cap_info->row_3_4) in dram_detect_cap()
2333 cap_info->cs1_row = cap_info->cs0_row; in dram_detect_cap()
2334 set_memory_map(chan, channel, sdram_params); in dram_detect_cap()
2335 ddrconfig = calculate_ddrconfig(sdram_params, channel); in dram_detect_cap()
2336 if (-1 == ddrconfig) in dram_detect_cap()
2338 set_ddrconfig(chan, sdram_params, channel, in dram_detect_cap()
2339 cap_info->ddrconfig); in dram_detect_cap()
2342 sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); in dram_detect_cap()
2345 sdram_detect_dbw(cap_info, sdram_params->base.dramtype); in dram_detect_cap()
2349 return (-1); in dram_detect_cap()
2363 (((rank == 2) ? 1 : 0) << 8) | in read_mr()
2364 mr_num) << 8, in read_mr()
2365 &ddr_pctl_regs->denali_ctl[118]); in read_mr()
2366 while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) & in read_mr()
2371 timeout--; in read_mr()
2373 if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) { in read_mr()
2374 *buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF; in read_mr()
2378 readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3); in read_mr()
2381 setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12)); in read_mr()
2384 return (-1); in read_mr()
2387 static int read_mr_for_detect(struct dram_info *dram, u32 channel, u32 rank, in read_mr_for_detect() argument
2396 &dram->chan[channel]; in read_mr_for_detect()
2397 struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl; in read_mr_for_detect()
2402 stride = get_ddr_stride(dram->pmusgrf); in read_mr_for_detect()
2404 if (sdram_params->ch[channel].cap_info.col == 0) { in read_mr_for_detect()
2405 ret = -1; in read_mr_for_detect()
2409 cs = sdram_params->ch[channel].cap_info.rank; in read_mr_for_detect()
2410 col = sdram_params->ch[channel].cap_info.col; in read_mr_for_detect()
2411 bk = sdram_params->ch[channel].cap_info.bk; in read_mr_for_detect()
2412 bw = sdram_params->ch[channel].cap_info.bw; in read_mr_for_detect()
2413 row_3_4 = sdram_params->ch[channel].cap_info.row_3_4; in read_mr_for_detect()
2414 cs0_row = sdram_params->ch[channel].cap_info.cs0_row; in read_mr_for_detect()
2415 cs1_row = sdram_params->ch[channel].cap_info.cs1_row; in read_mr_for_detect()
2416 ddrconfig = sdram_params->ch[channel].cap_info.ddrconfig; in read_mr_for_detect()
2419 sdram_params->ch[channel].cap_info.rank = 2; in read_mr_for_detect()
2420 sdram_params->ch[channel].cap_info.col = 10; in read_mr_for_detect()
2421 sdram_params->ch[channel].cap_info.bk = 3; in read_mr_for_detect()
2422 sdram_params->ch[channel].cap_info.bw = 2; in read_mr_for_detect()
2423 sdram_params->ch[channel].cap_info.row_3_4 = 0; in read_mr_for_detect()
2424 sdram_params->ch[channel].cap_info.cs0_row = 15; in read_mr_for_detect()
2425 sdram_params->ch[channel].cap_info.cs1_row = 15; in read_mr_for_detect()
2426 sdram_params->ch[channel].cap_info.ddrconfig = 1; in read_mr_for_detect()
2428 set_memory_map(chan, channel, sdram_params); in read_mr_for_detect()
2429 sdram_params->ch[channel].cap_info.ddrconfig = in read_mr_for_detect()
2430 calculate_ddrconfig(sdram_params, channel); in read_mr_for_detect()
2431 set_ddrconfig(chan, sdram_params, channel, in read_mr_for_detect()
2432 sdram_params->ch[channel].cap_info.ddrconfig); in read_mr_for_detect()
2433 set_cap_relate_config(chan, sdram_params, channel); in read_mr_for_detect()
2435 cs0_cap = (1 << (sdram_params->ch[channel].cap_info.bw in read_mr_for_detect()
2436 + sdram_params->ch[channel].cap_info.col in read_mr_for_detect()
2437 + sdram_params->ch[channel].cap_info.bk in read_mr_for_detect()
2438 + sdram_params->ch[channel].cap_info.cs0_row)); in read_mr_for_detect()
2440 if (sdram_params->ch[channel].cap_info.row_3_4) in read_mr_for_detect()
2443 if (channel == 0) in read_mr_for_detect()
2444 set_ddr_stride(dram->pmusgrf, 0x17); in read_mr_for_detect()
2446 set_ddr_stride(dram->pmusgrf, 0x18); in read_mr_for_detect()
2464 ret = -1; in read_mr_for_detect()
2468 sdram_params->ch[channel].cap_info.rank = cs; in read_mr_for_detect()
2469 sdram_params->ch[channel].cap_info.col = col; in read_mr_for_detect()
2470 sdram_params->ch[channel].cap_info.bk = bk; in read_mr_for_detect()
2471 sdram_params->ch[channel].cap_info.bw = bw; in read_mr_for_detect()
2472 sdram_params->ch[channel].cap_info.row_3_4 = row_3_4; in read_mr_for_detect()
2473 sdram_params->ch[channel].cap_info.cs0_row = cs0_row; in read_mr_for_detect()
2474 sdram_params->ch[channel].cap_info.cs1_row = cs1_row; in read_mr_for_detect()
2475 sdram_params->ch[channel].cap_info.ddrconfig = ddrconfig; in read_mr_for_detect()
2477 set_ddr_stride(dram->pmusgrf, stride); in read_mr_for_detect()
2485 if (sdram_params->base.dramtype == LPDDR4) in get_phy_fn()
2495 if (sdram_params->base.dramtype == LPDDR4) in get_ctl_fn()
2504 u32 channel) in dram_copy_phy_fn() argument
2513 denali_ctl = dram->chan[channel].pctl->denali_ctl; in dram_copy_phy_fn()
2514 denali_phy = dram->chan[channel].publ->denali_phy; in dram_copy_phy_fn()
2515 denali_phy_params = f1_sdram_params->phy_regs.denali_phy; in dram_copy_phy_fn()
2518 clrsetbits_le32(&denali_phy_params[896], 0x3 << 8, in dram_copy_phy_fn()
2519 fn << 8); in dram_copy_phy_fn()
2578 (63 - 58) * 4); in dram_copy_phy_fn()
2581 (191 - 186) * 4); in dram_copy_phy_fn()
2584 (319 - 314) * 4); in dram_copy_phy_fn()
2587 (447 - 442) * 4); in dram_copy_phy_fn()
2590 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 in dram_copy_phy_fn()
2592 * phy_dq_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 in dram_copy_phy_fn()
2596 writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]); in dram_copy_phy_fn()
2600 writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]); in dram_copy_phy_fn()
2604 writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]); in dram_copy_phy_fn()
2608 writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]); in dram_copy_phy_fn()
2688 (67 - 63) * 4); in dram_copy_phy_fn()
2693 (79 - 68) * 4); in dram_copy_phy_fn()
2697 (195 - 191) * 4); in dram_copy_phy_fn()
2702 (207 - 196) * 4); in dram_copy_phy_fn()
2706 (323 - 319) * 4); in dram_copy_phy_fn()
2711 (335 - 324) * 4); in dram_copy_phy_fn()
2715 (451 - 447) * 4); in dram_copy_phy_fn()
2720 (463 - 452) * 4); in dram_copy_phy_fn()
2733 if (f1_sdram_params->base.ddr_freq < 400 * MHz) in dram_copy_phy_fn()
2735 else if (f1_sdram_params->base.ddr_freq < 800 * MHz) in dram_copy_phy_fn()
2737 else if (f1_sdram_params->base.ddr_freq < 1200 * MHz) in dram_copy_phy_fn()
2765 if (f1_sdram_params->base.dramtype == LPDDR4) { in dram_copy_phy_fn()
2766 read_mr(dram->chan[channel].pctl, 1, 5, &mr5); in dram_copy_phy_fn()
2767 set_ds_odt(&dram->chan[channel], f1_sdram_params, 1, 0, mr5); in dram_copy_phy_fn()
2768 set_ds_odt(&dram->chan[channel], f1_sdram_params, 1, 1, mr5); in dram_copy_phy_fn()
2771 set_lp4_dq_odt(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2773 set_lp4_ca_odt(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2775 set_lp4_MR3(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2777 set_lp4_MR12(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2779 set_lp4_MR14(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2782 set_lp4_dq_odt(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2784 set_lp4_ca_odt(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2786 set_lp4_MR3(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2788 set_lp4_MR12(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2790 set_lp4_MR14(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2798 if (!((denali_phy_params[86] >> 8) in dram_copy_phy_fn()
2808 * smaller than 8 in dram_copy_phy_fn()
2813 16) & 0x1f) < 8) in dram_copy_phy_fn()
2816 8 << 16); in dram_copy_phy_fn()
2825 u32 channel; in dram_set_phy_fn() local
2827 for (channel = 0; channel < 2; channel++) in dram_set_phy_fn()
2829 channel); in dram_set_phy_fn()
2836 u32 channel; in dram_set_rate() local
2840 writel(0x70007, &dram->grf->soc_con0); in dram_set_rate()
2842 setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7)); in dram_set_rate()
2844 setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18)); in dram_set_rate()
2845 while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18)) in dram_set_rate()
2851 (fn << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0); in dram_set_rate()
2852 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) in dram_set_rate()
2855 ret_clk = clk_set_rate(&dram->ddr_clk, hz); in dram_set_rate()
2861 writel(0x20002, &dram->cic->cic_ctrl0); in dram_set_rate()
2862 while (!(readl(&dram->cic->cic_status0) & (1 << 0))) in dram_set_rate()
2866 clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18)); in dram_set_rate()
2867 while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18)) in dram_set_rate()
2871 clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7)); in dram_set_rate()
2874 if (!(sdram_params->base.dramtype == LPDDR4 && fn == 2)) { in dram_set_rate()
2875 for (channel = 0; channel < 2; channel++) { in dram_set_rate()
2876 if (!(sdram_params->ch[channel].cap_info.col)) in dram_set_rate()
2878 ret[channel] = data_training(&dram->chan[channel], in dram_set_rate()
2879 channel, sdram_params, in dram_set_rate()
2882 for (channel = 0; channel < 2; channel++) { in dram_set_rate()
2883 if (!(sdram_params->ch[channel].cap_info.col)) in dram_set_rate()
2885 if (ret[channel]) in dram_set_rate()
2886 printf("channel %d training failed!\n", in dram_set_rate()
2887 channel); in dram_set_rate()
2889 printf("channel %d training pass\n", channel); in dram_set_rate()
2928 unsigned char dramtype = sdram_params->base.dramtype; in sdram_init()
2929 unsigned int ddr_freq = sdram_params->base.ddr_freq; in sdram_init()
2930 int channel; in sdram_init() local
2942 return -E2BIG; in sdram_init()
2947 sdram_params->ch[ch].cap_info.rank = 2; in sdram_init()
2948 for (rank = 2; rank != 0; rank--) { in sdram_init()
2949 for (channel = 0; channel < 2; channel++) { in sdram_init()
2951 &dram->chan[channel]; in sdram_init()
2952 struct rk3399_cru *cru = dram->cru; in sdram_init()
2953 struct rk3399_ddr_publ_regs *publ = chan->publ; in sdram_init()
2955 phy_pctrl_reset(cru, channel); in sdram_init()
2957 pctl_cfg(chan, channel, sdram_params); in sdram_init()
2968 dram_set_cs(&dram->chan[ch], tmp, 2048, in sdram_init()
2969 sdram_params->base.dramtype); in sdram_init()
2970 sdram_params->ch[ch].cap_info.rank = rank; in sdram_init()
2971 if (sdram_params->base.dramtype == LPDDR4) { in sdram_init()
2985 if (sdram_params->base.dramtype == LPDDR3) in sdram_init()
2990 if (!(data_training(&dram->chan[ch], ch, in sdram_init()
2996 sdram_params->ch[ch].cap_info.rank = rank; in sdram_init()
2999 sdram_params->base.num_channels = 0; in sdram_init()
3000 for (channel = 0; channel < 2; channel++) { in sdram_init()
3001 const struct chan_info *chan = &dram->chan[channel]; in sdram_init()
3003 &sdram_params->ch[channel].cap_info; in sdram_init()
3005 if (cap_info->rank == 0) { in sdram_init()
3009 sdram_params->base.num_channels++; in sdram_init()
3012 printf("Channel "); in sdram_init()
3013 printf(channel ? "1: " : "0: "); in sdram_init()
3015 if (channel == 0) in sdram_init()
3016 set_ddr_stride(dram->pmusgrf, 0x17); in sdram_init()
3018 set_ddr_stride(dram->pmusgrf, 0x18); in sdram_init()
3020 if (dram_detect_cap(dram, sdram_params, channel)) { in sdram_init()
3025 sdram_print_ddr_info(cap_info, &sdram_params->base, 0); in sdram_init()
3026 set_memory_map(chan, channel, sdram_params); in sdram_init()
3027 cap_info->ddrconfig = in sdram_init()
3028 calculate_ddrconfig(sdram_params, channel); in sdram_init()
3029 if (-1 == cap_info->ddrconfig) { in sdram_init()
3033 set_ddrconfig(chan, sdram_params, channel, cap_info->ddrconfig); in sdram_init()
3034 set_cap_relate_config(chan, sdram_params, channel); in sdram_init()
3037 if (sdram_params->base.num_channels == 0) { in sdram_init()
3038 sdram_print_dram_type(sdram_params->base.dramtype); in sdram_init()
3039 printf(" %dMHz\n", sdram_params->base.ddr_freq); in sdram_init()
3040 return -1; in sdram_init()
3043 sdram_params->base.stride = calculate_stride(sdram_params); in sdram_init()
3046 if (sdram_params->base.dramtype != LPDDR4) in sdram_init()
3049 if (sdram_params->base.dramtype == LPDDR4) { in sdram_init()
3065 ret = dev_read_u32_array(dev, "rockchip,sdram-params", in rk3399_dmc_ofdata_to_platdata()
3066 (u32 *)&plat->sdram_params, in rk3399_dmc_ofdata_to_platdata()
3067 sizeof(plat->sdram_params) / sizeof(u32)); in rk3399_dmc_ofdata_to_platdata()
3069 printf("%s: Cannot read rockchip,sdram-params %d\n", in rk3399_dmc_ofdata_to_platdata()
3073 ret = regmap_init_mem(dev, &plat->map); in rk3399_dmc_ofdata_to_platdata()
3085 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; in conv_of_platdata()
3088 ret = regmap_init_mem_platdata(dev, dtplat->reg, in conv_of_platdata()
3089 ARRAY_SIZE(dtplat->reg) / 2, in conv_of_platdata()
3090 &plat->map); in conv_of_platdata()
3104 struct rk3399_sdram_params *params = &plat->sdram_params; in rk3399_dmc_init()
3106 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; in rk3399_dmc_init()
3108 (void *)dtplat->rockchip_sdram_params; in rk3399_dmc_init()
3115 priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); in rk3399_dmc_init()
3116 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3399_dmc_init()
3117 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); in rk3399_dmc_init()
3118 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); in rk3399_dmc_init()
3119 priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); in rk3399_dmc_init()
3120 priv->pmucru = rockchip_get_pmucru(); in rk3399_dmc_init()
3121 priv->cru = rockchip_get_cru(); in rk3399_dmc_init()
3122 priv->chan[0].pctl = regmap_get_range(plat->map, 0); in rk3399_dmc_init()
3123 priv->chan[0].pi = regmap_get_range(plat->map, 1); in rk3399_dmc_init()
3124 priv->chan[0].publ = regmap_get_range(plat->map, 2); in rk3399_dmc_init()
3125 priv->chan[0].msch = regmap_get_range(plat->map, 3); in rk3399_dmc_init()
3126 priv->chan[1].pctl = regmap_get_range(plat->map, 4); in rk3399_dmc_init()
3127 priv->chan[1].pi = regmap_get_range(plat->map, 5); in rk3399_dmc_init()
3128 priv->chan[1].publ = regmap_get_range(plat->map, 6); in rk3399_dmc_init()
3129 priv->chan[1].msch = regmap_get_range(plat->map, 7); in rk3399_dmc_init()
3132 priv->chan[0].pctl, priv->chan[0].pi, in rk3399_dmc_init()
3133 priv->chan[0].publ, priv->chan[0].msch, in rk3399_dmc_init()
3134 priv->chan[1].pctl, priv->chan[1].pi, in rk3399_dmc_init()
3135 priv->chan[1].publ, priv->chan[1].msch); in rk3399_dmc_init()
3136 debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru, in rk3399_dmc_init()
3137 priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu); in rk3399_dmc_init()
3139 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); in rk3399_dmc_init()
3141 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); in rk3399_dmc_init()
3147 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); in rk3399_dmc_init()
3170 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); in rk3399_dmc_probe()
3171 debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); in rk3399_dmc_probe()
3172 priv->info.base = CONFIG_SYS_SDRAM_BASE; in rk3399_dmc_probe()
3173 priv->info.size = in rk3399_dmc_probe()
3174 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2); in rk3399_dmc_probe()
3179 ddr_parem.para[0] = priv->info.base; in rk3399_dmc_probe()
3180 ddr_parem.para[1] = priv->info.size; in rk3399_dmc_probe()
3192 *info = priv->info; in rk3399_dmc_get_info()
3202 { .compatible = "rockchip,rk3399-dmc" },