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/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/isp/
H A Dprocfs.c1 // SPDX-License-Identifier: GPL-2.0
34 seq_printf(p, "%-10s %s(0x%x)\n", "DPCC0", (val & 1) ? "ON" : "OFF", val); in isp20_show()
36 seq_printf(p, "%-10s %s(0x%x)\n", "DPCC1", (val & 1) ? "ON" : "OFF", val); in isp20_show()
38 seq_printf(p, "%-10s %s(0x%x)\n", "DPCC2", (val & 1) ? "ON" : "OFF", val); in isp20_show()
40 seq_printf(p, "%-10s %s(0x%x)\n", "BLS", (val & 1) ? "ON" : "OFF", val); in isp20_show()
42 seq_printf(p, "%-10s %s(0x%x)\n", "SDG", in isp20_show()
45 seq_printf(p, "%-10s %s(0x%x)\n", "LSC", (val & 1) ? "ON" : "OFF", val); in isp20_show()
47 seq_printf(p, "%-10s %s(0x%x) (gain: 0x%08x, 0x%08x)\n", "AWBGAIN", in isp20_show()
52 seq_printf(p, "%-10s %s(0x%x)\n", "DEBAYER", (val & 1) ? "ON" : "OFF", val); in isp20_show()
54 seq_printf(p, "%-10s %s(0x%x)\n", "CCM", (val & 1) ? "ON" : "OFF", val); in isp20_show()
[all …]
/OK3568_Linux_fs/kernel/Documentation/i2c/
H A Dten-bit-addresses.rst2 I2C Ten-bit Addresses
5 The I2C protocol knows about two kinds of device addresses: normal 7 bit
6 addresses, and an extended set of 10 bit addresses. The sets of addresses
7 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
9 To avoid ambiguity, the user sees 10 bit addresses mapped to a different
10 address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
11 10 bit mode. This is used for creating device names in sysfs. It is also
12 needed when instantiating 10 bit devices via the new_device file in sysfs.
14 I2C messages to and from 10-bit address devices have a different format.
17 The current 10 bit address support is minimal. It should work, however
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/
H A Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
28 - enum:
29 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
30 - ad,ad7414
31 # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
32 - ad,adm9240
[all …]
/OK3568_Linux_fs/kernel/Documentation/gpu/
H A Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
37 reside in the least-significant bits of the corresponding linear
81 Formats which are typically multi-planar in linear layouts (e.g. YUV
111 Cross-device interoperability
115 canonical formats for use between AFBC-enabled devices. Formats which
119 .. flat-table:: AFBC formats
121 * - Fourcc code
122 - Description
[all …]
/OK3568_Linux_fs/kernel/sound/soc/rockchip/
H A Drockchip_spdifrx.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ALSA SoC Audio Layer - Rockchip SPDIF_RX Controller driver
15 #define SPDIFRX_CFGR_TWAD_STREAM BIT(1)
16 #define SPDIFRX_EN_MASK BIT(0)
17 #define SPDIFRX_EN BIT(0)
21 #define SPDIFRX_CLR_RXSC BIT(0)
24 #define SPDIFRX_CDR_CS_MASK GENMASK(10, 9)
25 #define SPDIFRX_CDR_AVGSEL_MASK BIT(1)
27 #define SPDIFRX_CDR_AVGSEL_AVG BIT(1)
28 #define SPDIFRX_CDR_BYPASS_MASK BIT(0)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/wil6210/
H A Dtxrx.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
40 * bit 10 : interrupt_en:1
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/comedi/drivers/
H A Dni_at_ao.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for NI AT-AO-6/10 boards
6 * COMEDI - Linux Control and Measurement Device Interface
12 * Description: National Instruments AT-AO-6/10
13 * Devices: [National Instruments] AT-AO-6 (at-ao-6), AT-AO-10 (at-ao-10)
19 * [0] - I/O port base address
20 * [1] - IRQ (unused)
21 * [2] - DMA (unused)
22 * [3] - analog output range, set by jumpers on hardware
23 * 0 for -10 to 10V bipolar
[all …]
H A Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/dec/tulip/
H A Dpnic2.c5 Written/copyright 1994-2001 by Donald Becker.
15 /* Understanding the PNIC_II - everything is this file is based
24 * -----
25 * Bit 24 - SCR
26 * Bit 23 - PCS
27 * Bit 22 - TTM (Trasmit Threshold Mode)
28 * Bit 18 - Port Select
29 * Bit 13 - Start - 1, Stop - 0 Transmissions
30 * Bit 11:10 - Loop Back Operation Mode
31 * Bit 9 - Full Duplex mode (Advertise 10BaseT-FD is CSR14<7> is set)
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/media/atomisp/pci/css_2401_system/hrt/
H A Dmipi_backend_common_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/media/atomisp/pci/
H A Dcss_receiver_2400_common_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
[all …]
H A Disp_acquisition_defs.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */
22 /* --------------------------------------------------*/
26 /* --------------------------------------------------*/
28 /* --------------------------------------------------*/
32 /* --------------------------------------------------*/
34 /* --------------------------------------------------*/
49 #define ACQ_FSM_STATE_INFO_REG_ID 10
80 /* bit definitions */
88 /* --------------------------------------------------*/
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
171 #define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
172 #define QCA956X_MAC_CFG1_RX_RST BIT(19)
173 #define QCA956X_MAC_CFG1_TX_RST BIT(18)
174 #define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
175 #define QCA956X_MAC_CFG1_RX_EN BIT(2)
176 #define QCA956X_MAC_CFG1_TX_EN BIT(0)
179 #define QCA956X_MAC_CFG2_IF_1000 BIT(9)
[all …]
/OK3568_Linux_fs/kernel/tools/edid/
H A Dedid.S18 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
48 ((((v1-'@')&0x1f)<<10)+(((v2-'@')&0x1f)<<5)+((v3-'@')&0x1f))
74 /* Year of manufacture, less 1990. (1990-2245)
76 year: .byte YEAR-1990
81 /* If Bit 7=1 Digital input. If set, the following bit definitions apply:
82 Bits 6-1 Reserved, must be 0
83 Bit 0 Signal is compatible with VESA DFP 1.x TMDS CRGB,
85 If Bit 7=0 Analog input. If clear, the following bit definitions apply:
86 Bits 6-5 Video white and sync levels, relative to blank
87 00=+0.7/-0.3 V; 01=+0.714/-0.286 V;
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/samsung/
H A Dphy-exynos4x12-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support
13 #include "phy-samsung-usb2.h"
20 #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0)
21 #define EXYNOS_4x12_UPHYPWR_PHY0_PWR BIT(3)
22 #define EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR BIT(4)
23 #define EXYNOS_4x12_UPHYPWR_PHY0_SLEEP BIT(5)
30 #define EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND BIT(6)
31 #define EXYNOS_4x12_UPHYPWR_PHY1_PWR BIT(7)
32 #define EXYNOS_4x12_UPHYPWR_PHY1_SLEEP BIT(8)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
[all …]
/OK3568_Linux_fs/kernel/include/linux/usb/
H A Dpd.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2015-2017 Google, Inc
25 PD_CTRL_PR_SWAP = 10,
29 /* 14-15 Reserved */
36 /* 22-31 Reserved */
49 /* 9-14 Reserved */
51 /* 16-31 Reserved */
65 PD_EXT_FW_UPDATE_REQUEST = 10,
70 /* 15-31 Reserved */
78 #define PD_HEADER_EXT_HDR BIT(15)
[all …]
/OK3568_Linux_fs/u-boot/include/power/power_delivery/
H A Dpd.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2015-2017 Google, Inc
25 PD_CTRL_PR_SWAP = 10,
29 /* 14-15 Reserved */
36 /* 22-31 Reserved */
49 /* 9-14 Reserved */
51 /* 16-31 Reserved */
65 PD_EXT_FW_UPDATE_REQUEST = 10,
70 /* 15-31 Reserved */
78 #define PD_HEADER_EXT_HDR BIT(15)
[all …]
/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h4 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
9 * SPDX-License-Identifier: GPL-2.0+
18 #ifndef BIT
19 #define BIT(nr) (1 << (nr)) macro
307 #define AR724X_PLL_REF_DIV_SHIFT 10
336 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
343 #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2)
346 #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
[all …]
/OK3568_Linux_fs/kernel/include/soc/mscc/
H A Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
/OK3568_Linux_fs/kernel/sound/firewire/oxfw/
H A Doxfw-command.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * oxfw_command.c - a part of driver for OXFW970/971 based devices
16 buf = kmalloc(len + 10, GFP_KERNEL); in avc_stream_set_format()
18 return -ENOMEM; in avc_stream_set_format()
30 memcpy(buf + 10, format, len); in avc_stream_set_format()
32 /* do transaction and check buf[1-8] are the same against command */ in avc_stream_set_format()
33 err = fcp_avc_transaction(unit, buf, len + 10, buf, len + 10, in avc_stream_set_format()
34 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_stream_set_format()
35 BIT(6) | BIT(7) | BIT(8)); in avc_stream_set_format()
38 else if (err < len + 10) in avc_stream_set_format()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc11 ---------
12 The LS1043A integrated multicore processor combines four ARM Cortex-A53
18 - Four 64-bit ARM Cortex-A53 CPUs
19 - 1 MB unified L2 Cache
20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
22 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
24 - Packet parsing, classification, and distribution (FMan)
25 - Queue management for scheduling, packet sequencing, and congestion
27 - Hardware buffer management for buffer allocation and de-allocation (BMan)
28 - Cryptography acceleration (SEC)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
14 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
15 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
30 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
31 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
32 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
33 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
34 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
37 #define MT_RXD1_NORMAL_CM BIT(23)
38 #define MT_RXD1_NORMAL_CLM BIT(24)
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_gvi.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Author: Guochun Huang <hero.huang@rock-chips.com>
39 #define SYS_CTRL0_GVI_EN BIT(0)
40 #define SYS_CTRL0_AUTO_GATING BIT(1)
41 #define SYS_CTRL0_FRM_RST_EN BIT(2)
42 #define SYS_CTRL0_FRM_RST_MODE BIT(3)
47 #define SYS_CTRL0_SECTION_NUM_MASK GENMASK(11, 10)
48 #define SYS_CTRL0_SECTION_NUM(x) UPDATE(x, 11, 10)
49 #define SYS_CTRL0_CDR_ENDIAN_SWAP BIT(12)
50 #define SYS_CTRL0_PACK_BYTE_SWAP BIT(13)
[all …]

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