1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun edid.S: EDID data template 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun Copyright (C) 2012 Carsten Emde <C.Emde@osadl.org> 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun This program is free software; you can redistribute it and/or 7*4882a593Smuzhiyun modify it under the terms of the GNU General Public License 8*4882a593Smuzhiyun as published by the Free Software Foundation; either version 2 9*4882a593Smuzhiyun of the License, or (at your option) any later version. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun This program is distributed in the hope that it will be useful, 12*4882a593Smuzhiyun but WITHOUT ANY WARRANTY; without even the implied warranty of 13*4882a593Smuzhiyun MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*4882a593Smuzhiyun GNU General Public License for more details. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun You should have received a copy of the GNU General Public License 17*4882a593Smuzhiyun along with this program; if not, write to the Free Software 18*4882a593Smuzhiyun Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19*4882a593Smuzhiyun*/ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun/* Manufacturer */ 23*4882a593Smuzhiyun#define MFG_LNX1 'L' 24*4882a593Smuzhiyun#define MFG_LNX2 'N' 25*4882a593Smuzhiyun#define MFG_LNX3 'X' 26*4882a593Smuzhiyun#define SERIAL 0 27*4882a593Smuzhiyun#define YEAR 2012 28*4882a593Smuzhiyun#define WEEK 5 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun/* EDID 1.3 standard definitions */ 31*4882a593Smuzhiyun#define XY_RATIO_16_10 0b00 32*4882a593Smuzhiyun#define XY_RATIO_4_3 0b01 33*4882a593Smuzhiyun#define XY_RATIO_5_4 0b10 34*4882a593Smuzhiyun#define XY_RATIO_16_9 0b11 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun/* Provide defaults for the timing bits */ 37*4882a593Smuzhiyun#ifndef ESTABLISHED_TIMING1_BITS 38*4882a593Smuzhiyun#define ESTABLISHED_TIMING1_BITS 0x00 39*4882a593Smuzhiyun#endif 40*4882a593Smuzhiyun#ifndef ESTABLISHED_TIMING2_BITS 41*4882a593Smuzhiyun#define ESTABLISHED_TIMING2_BITS 0x00 42*4882a593Smuzhiyun#endif 43*4882a593Smuzhiyun#ifndef ESTABLISHED_TIMING3_BITS 44*4882a593Smuzhiyun#define ESTABLISHED_TIMING3_BITS 0x00 45*4882a593Smuzhiyun#endif 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun#define mfgname2id(v1,v2,v3) \ 48*4882a593Smuzhiyun ((((v1-'@')&0x1f)<<10)+(((v2-'@')&0x1f)<<5)+((v3-'@')&0x1f)) 49*4882a593Smuzhiyun#define swap16(v1) ((v1>>8)+((v1&0xff)<<8)) 50*4882a593Smuzhiyun#define lsbs2(v1,v2) (((v1&0x0f)<<4)+(v2&0x0f)) 51*4882a593Smuzhiyun#define msbs2(v1,v2) ((((v1>>8)&0x0f)<<4)+((v2>>8)&0x0f)) 52*4882a593Smuzhiyun#define msbs4(v1,v2,v3,v4) \ 53*4882a593Smuzhiyun ((((v1>>8)&0x03)<<6)+(((v2>>8)&0x03)<<4)+\ 54*4882a593Smuzhiyun (((v3>>4)&0x03)<<2)+((v4>>4)&0x03)) 55*4882a593Smuzhiyun#define pixdpi2mm(pix,dpi) ((pix*25)/dpi) 56*4882a593Smuzhiyun#define xsize pixdpi2mm(XPIX,DPI) 57*4882a593Smuzhiyun#define ysize pixdpi2mm(YPIX,DPI) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun .data 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun/* Fixed header pattern */ 62*4882a593Smuzhiyunheader: .byte 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00 63*4882a593Smuzhiyun 64*4882a593Smuzhiyunmfg_id: .hword swap16(mfgname2id(MFG_LNX1, MFG_LNX2, MFG_LNX3)) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunprod_code: .hword 0 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun/* Serial number. 32 bits, little endian. */ 69*4882a593Smuzhiyunserial_number: .long SERIAL 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun/* Week of manufacture */ 72*4882a593Smuzhiyunweek: .byte WEEK 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun/* Year of manufacture, less 1990. (1990-2245) 75*4882a593Smuzhiyun If week=255, it is the model year instead */ 76*4882a593Smuzhiyunyear: .byte YEAR-1990 77*4882a593Smuzhiyun 78*4882a593Smuzhiyunversion: .byte VERSION /* EDID version, usually 1 (for 1.3) */ 79*4882a593Smuzhiyunrevision: .byte REVISION /* EDID revision, usually 3 (for 1.3) */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun/* If Bit 7=1 Digital input. If set, the following bit definitions apply: 82*4882a593Smuzhiyun Bits 6-1 Reserved, must be 0 83*4882a593Smuzhiyun Bit 0 Signal is compatible with VESA DFP 1.x TMDS CRGB, 84*4882a593Smuzhiyun 1 pixel per clock, up to 8 bits per color, MSB aligned, 85*4882a593Smuzhiyun If Bit 7=0 Analog input. If clear, the following bit definitions apply: 86*4882a593Smuzhiyun Bits 6-5 Video white and sync levels, relative to blank 87*4882a593Smuzhiyun 00=+0.7/-0.3 V; 01=+0.714/-0.286 V; 88*4882a593Smuzhiyun 10=+1.0/-0.4 V; 11=+0.7/0 V 89*4882a593Smuzhiyun Bit 4 Blank-to-black setup (pedestal) expected 90*4882a593Smuzhiyun Bit 3 Separate sync supported 91*4882a593Smuzhiyun Bit 2 Composite sync (on HSync) supported 92*4882a593Smuzhiyun Bit 1 Sync on green supported 93*4882a593Smuzhiyun Bit 0 VSync pulse must be serrated when somposite or 94*4882a593Smuzhiyun sync-on-green is used. */ 95*4882a593Smuzhiyunvideo_parms: .byte 0x6d 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun/* Maximum horizontal image size, in centimetres 98*4882a593Smuzhiyun (max 292 cm/115 in at 16:9 aspect ratio) */ 99*4882a593Smuzhiyunmax_hor_size: .byte xsize/10 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun/* Maximum vertical image size, in centimetres. 102*4882a593Smuzhiyun If either byte is 0, undefined (e.g. projector) */ 103*4882a593Smuzhiyunmax_vert_size: .byte ysize/10 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun/* Display gamma, minus 1, times 100 (range 1.00-3.5 */ 106*4882a593Smuzhiyungamma: .byte 120 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun/* Bit 7 DPMS standby supported 109*4882a593Smuzhiyun Bit 6 DPMS suspend supported 110*4882a593Smuzhiyun Bit 5 DPMS active-off supported 111*4882a593Smuzhiyun Bits 4-3 Display type: 00=monochrome; 01=RGB colour; 112*4882a593Smuzhiyun 10=non-RGB multicolour; 11=undefined 113*4882a593Smuzhiyun Bit 2 Standard sRGB colour space. Bytes 25-34 must contain 114*4882a593Smuzhiyun sRGB standard values. 115*4882a593Smuzhiyun Bit 1 Preferred timing mode specified in descriptor block 1. 116*4882a593Smuzhiyun Bit 0 GTF supported with default parameter values. */ 117*4882a593Smuzhiyundsp_features: .byte 0xea 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun/* Chromaticity coordinates. */ 120*4882a593Smuzhiyun/* Red and green least-significant bits 121*4882a593Smuzhiyun Bits 7-6 Red x value least-significant 2 bits 122*4882a593Smuzhiyun Bits 5-4 Red y value least-significant 2 bits 123*4882a593Smuzhiyun Bits 3-2 Green x value lst-significant 2 bits 124*4882a593Smuzhiyun Bits 1-0 Green y value least-significant 2 bits */ 125*4882a593Smuzhiyunred_green_lsb: .byte 0x5e 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun/* Blue and white least-significant 2 bits */ 128*4882a593Smuzhiyunblue_white_lsb: .byte 0xc0 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun/* Red x value most significant 8 bits. 131*4882a593Smuzhiyun 0-255 encodes 0-0.996 (255/256); 0-0.999 (1023/1024) with lsbits */ 132*4882a593Smuzhiyunred_x_msb: .byte 0xa4 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun/* Red y value most significant 8 bits */ 135*4882a593Smuzhiyunred_y_msb: .byte 0x59 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun/* Green x and y value most significant 8 bits */ 138*4882a593Smuzhiyungreen_x_y_msb: .byte 0x4a,0x98 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun/* Blue x and y value most significant 8 bits */ 141*4882a593Smuzhiyunblue_x_y_msb: .byte 0x25,0x20 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun/* Default white point x and y value most significant 8 bits */ 144*4882a593Smuzhiyunwhite_x_y_msb: .byte 0x50,0x54 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun/* Established timings */ 147*4882a593Smuzhiyun/* Bit 7 720x400 @ 70 Hz 148*4882a593Smuzhiyun Bit 6 720x400 @ 88 Hz 149*4882a593Smuzhiyun Bit 5 640x480 @ 60 Hz 150*4882a593Smuzhiyun Bit 4 640x480 @ 67 Hz 151*4882a593Smuzhiyun Bit 3 640x480 @ 72 Hz 152*4882a593Smuzhiyun Bit 2 640x480 @ 75 Hz 153*4882a593Smuzhiyun Bit 1 800x600 @ 56 Hz 154*4882a593Smuzhiyun Bit 0 800x600 @ 60 Hz */ 155*4882a593Smuzhiyunestbl_timing1: .byte ESTABLISHED_TIMING1_BITS 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun/* Bit 7 800x600 @ 72 Hz 158*4882a593Smuzhiyun Bit 6 800x600 @ 75 Hz 159*4882a593Smuzhiyun Bit 5 832x624 @ 75 Hz 160*4882a593Smuzhiyun Bit 4 1024x768 @ 87 Hz, interlaced (1024x768) 161*4882a593Smuzhiyun Bit 3 1024x768 @ 60 Hz 162*4882a593Smuzhiyun Bit 2 1024x768 @ 72 Hz 163*4882a593Smuzhiyun Bit 1 1024x768 @ 75 Hz 164*4882a593Smuzhiyun Bit 0 1280x1024 @ 75 Hz */ 165*4882a593Smuzhiyunestbl_timing2: .byte ESTABLISHED_TIMING2_BITS 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun/* Bit 7 1152x870 @ 75 Hz (Apple Macintosh II) 168*4882a593Smuzhiyun Bits 6-0 Other manufacturer-specific display mod */ 169*4882a593Smuzhiyunestbl_timing3: .byte ESTABLISHED_TIMING3_BITS 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun/* Standard timing */ 172*4882a593Smuzhiyun/* X resolution, less 31, divided by 8 (256-2288 pixels) */ 173*4882a593Smuzhiyunstd_xres: .byte (XPIX/8)-31 174*4882a593Smuzhiyun/* Y resolution, X:Y pixel ratio 175*4882a593Smuzhiyun Bits 7-6 X:Y pixel ratio: 00=16:10; 01=4:3; 10=5:4; 11=16:9. 176*4882a593Smuzhiyun Bits 5-0 Vertical frequency, less 60 (60-123 Hz) */ 177*4882a593Smuzhiyunstd_vres: .byte (XY_RATIO<<6)+VFREQ-60 178*4882a593Smuzhiyun .fill 7,2,0x0101 /* Unused */ 179*4882a593Smuzhiyun 180*4882a593Smuzhiyundescriptor1: 181*4882a593Smuzhiyun/* Pixel clock in 10 kHz units. (0.-655.35 MHz, little-endian) */ 182*4882a593Smuzhiyunclock: .hword CLOCK/10 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun/* Horizontal active pixels 8 lsbits (0-4095) */ 185*4882a593Smuzhiyunx_act_lsb: .byte XPIX&0xff 186*4882a593Smuzhiyun/* Horizontal blanking pixels 8 lsbits (0-4095) 187*4882a593Smuzhiyun End of active to start of next active. */ 188*4882a593Smuzhiyunx_blk_lsb: .byte XBLANK&0xff 189*4882a593Smuzhiyun/* Bits 7-4 Horizontal active pixels 4 msbits 190*4882a593Smuzhiyun Bits 3-0 Horizontal blanking pixels 4 msbits */ 191*4882a593Smuzhiyunx_msbs: .byte msbs2(XPIX,XBLANK) 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun/* Vertical active lines 8 lsbits (0-4095) */ 194*4882a593Smuzhiyuny_act_lsb: .byte YPIX&0xff 195*4882a593Smuzhiyun/* Vertical blanking lines 8 lsbits (0-4095) */ 196*4882a593Smuzhiyuny_blk_lsb: .byte YBLANK&0xff 197*4882a593Smuzhiyun/* Bits 7-4 Vertical active lines 4 msbits 198*4882a593Smuzhiyun Bits 3-0 Vertical blanking lines 4 msbits */ 199*4882a593Smuzhiyuny_msbs: .byte msbs2(YPIX,YBLANK) 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun/* Horizontal sync offset pixels 8 lsbits (0-1023) From blanking start */ 202*4882a593Smuzhiyunx_snc_off_lsb: .byte XOFFSET&0xff 203*4882a593Smuzhiyun/* Horizontal sync pulse width pixels 8 lsbits (0-1023) */ 204*4882a593Smuzhiyunx_snc_pls_lsb: .byte XPULSE&0xff 205*4882a593Smuzhiyun/* Bits 7-4 Vertical sync offset lines 4 lsbits (0-63) 206*4882a593Smuzhiyun Bits 3-0 Vertical sync pulse width lines 4 lsbits (0-63) */ 207*4882a593Smuzhiyuny_snc_lsb: .byte lsbs2(YOFFSET, YPULSE) 208*4882a593Smuzhiyun/* Bits 7-6 Horizontal sync offset pixels 2 msbits 209*4882a593Smuzhiyun Bits 5-4 Horizontal sync pulse width pixels 2 msbits 210*4882a593Smuzhiyun Bits 3-2 Vertical sync offset lines 2 msbits 211*4882a593Smuzhiyun Bits 1-0 Vertical sync pulse width lines 2 msbits */ 212*4882a593Smuzhiyunxy_snc_msbs: .byte msbs4(XOFFSET,XPULSE,YOFFSET,YPULSE) 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun/* Horizontal display size, mm, 8 lsbits (0-4095 mm, 161 in) */ 215*4882a593Smuzhiyunx_dsp_size: .byte xsize&0xff 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun/* Vertical display size, mm, 8 lsbits (0-4095 mm, 161 in) */ 218*4882a593Smuzhiyuny_dsp_size: .byte ysize&0xff 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun/* Bits 7-4 Horizontal display size, mm, 4 msbits 221*4882a593Smuzhiyun Bits 3-0 Vertical display size, mm, 4 msbits */ 222*4882a593Smuzhiyundsp_size_mbsb: .byte msbs2(xsize,ysize) 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun/* Horizontal border pixels (each side; total is twice this) */ 225*4882a593Smuzhiyunx_border: .byte 0 226*4882a593Smuzhiyun/* Vertical border lines (each side; total is twice this) */ 227*4882a593Smuzhiyuny_border: .byte 0 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun/* Bit 7 Interlaced 230*4882a593Smuzhiyun Bits 6-5 Stereo mode: 00=No stereo; other values depend on bit 0: 231*4882a593Smuzhiyun Bit 0=0: 01=Field sequential, sync=1 during right; 10=similar, 232*4882a593Smuzhiyun sync=1 during left; 11=4-way interleaved stereo 233*4882a593Smuzhiyun Bit 0=1 2-way interleaved stereo: 01=Right image on even lines; 234*4882a593Smuzhiyun 10=Left image on even lines; 11=side-by-side 235*4882a593Smuzhiyun Bits 4-3 Sync type: 00=Analog composite; 01=Bipolar analog composite; 236*4882a593Smuzhiyun 10=Digital composite (on HSync); 11=Digital separate 237*4882a593Smuzhiyun Bit 2 If digital separate: Vertical sync polarity (1=positive) 238*4882a593Smuzhiyun Other types: VSync serrated (HSync during VSync) 239*4882a593Smuzhiyun Bit 1 If analog sync: Sync on all 3 RGB lines (else green only) 240*4882a593Smuzhiyun Digital: HSync polarity (1=positive) 241*4882a593Smuzhiyun Bit 0 2-way line-interleaved stereo, if bits 4-3 are not 00. */ 242*4882a593Smuzhiyunfeatures: .byte 0x18+(VSYNC_POL<<2)+(HSYNC_POL<<1) 243*4882a593Smuzhiyun 244*4882a593Smuzhiyundescriptor2: .byte 0,0 /* Not a detailed timing descriptor */ 245*4882a593Smuzhiyun .byte 0 /* Must be zero */ 246*4882a593Smuzhiyun .byte 0xff /* Descriptor is monitor serial number (text) */ 247*4882a593Smuzhiyun .byte 0 /* Must be zero */ 248*4882a593Smuzhiyunstart1: .ascii "Linux #0" 249*4882a593Smuzhiyunend1: .byte 0x0a /* End marker */ 250*4882a593Smuzhiyun .fill 12-(end1-start1), 1, 0x20 /* Padded spaces */ 251*4882a593Smuzhiyundescriptor3: .byte 0,0 /* Not a detailed timing descriptor */ 252*4882a593Smuzhiyun .byte 0 /* Must be zero */ 253*4882a593Smuzhiyun .byte 0xfd /* Descriptor is monitor range limits */ 254*4882a593Smuzhiyun .byte 0 /* Must be zero */ 255*4882a593Smuzhiyunstart2: .byte VFREQ-1 /* Minimum vertical field rate (1-255 Hz) */ 256*4882a593Smuzhiyun .byte VFREQ+1 /* Maximum vertical field rate (1-255 Hz) */ 257*4882a593Smuzhiyun .byte (CLOCK/(XPIX+XBLANK))-1 /* Minimum horizontal line rate 258*4882a593Smuzhiyun (1-255 kHz) */ 259*4882a593Smuzhiyun .byte (CLOCK/(XPIX+XBLANK))+1 /* Maximum horizontal line rate 260*4882a593Smuzhiyun (1-255 kHz) */ 261*4882a593Smuzhiyun .byte (CLOCK/10000)+1 /* Maximum pixel clock rate, rounded up 262*4882a593Smuzhiyun to 10 MHz multiple (10-2550 MHz) */ 263*4882a593Smuzhiyun .byte 0 /* No extended timing information type */ 264*4882a593Smuzhiyunend2: .byte 0x0a /* End marker */ 265*4882a593Smuzhiyun .fill 12-(end2-start2), 1, 0x20 /* Padded spaces */ 266*4882a593Smuzhiyundescriptor4: .byte 0,0 /* Not a detailed timing descriptor */ 267*4882a593Smuzhiyun .byte 0 /* Must be zero */ 268*4882a593Smuzhiyun .byte 0xfc /* Descriptor is text */ 269*4882a593Smuzhiyun .byte 0 /* Must be zero */ 270*4882a593Smuzhiyunstart3: .ascii TIMING_NAME 271*4882a593Smuzhiyunend3: .byte 0x0a /* End marker */ 272*4882a593Smuzhiyun .fill 12-(end3-start3), 1, 0x20 /* Padded spaces */ 273*4882a593Smuzhiyunextensions: .byte 0 /* Number of extensions to follow */ 274*4882a593Smuzhiyunchecksum: .byte CRC /* Sum of all bytes must be 0 */ 275