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/OK3568_Linux_fs/kernel/drivers/video/rockchip/rga3/include/
H A Drga3_reg_info.h8 #define RGA3_SYS_CTRL 0x000
9 #define RGA3_CMD_CTRL 0x004
10 #define RGA3_CMD_ADDR 0x008
11 #define RGA3_MI_GROUP_CTRL 0x00c
12 #define RGA3_ARQOS_CTRL 0x010
13 #define RGA3_VERSION_NUM 0x018
14 #define RGA3_VERSION_TIM 0x01c
15 #define RGA3_INT_EN 0x020
16 #define RGA3_INT_RAW 0x024
17 #define RGA3_INT_MSK 0x028
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/isp/
H A Disp_params_v2x.h12 #define ISP2X_YUVAE_ENA BIT(0)
19 #define ISP2X_YUVAE_H_OFFSET_SET(x) ((x) & 0x1FFF)
20 #define ISP2X_YUVAE_V_OFFSET_SET(x) (((x) & 0x1FFF) << 16)
21 #define ISP2X_YUVAE_H_SIZE_SET(x) ((x) & 0x7FF)
22 #define ISP2X_YUVAE_V_SIZE_SET(x) (((x) & 0x7FF) << 16)
23 #define ISP2X_YUVAE_SUBWIN_H_OFFSET_SET(x) ((x) & 0x1FFF)
24 #define ISP2X_YUVAE_SUBWIN_V_OFFSET_SET(x) (((x) & 0x1FFF) << 16)
25 #define ISP2X_YUVAE_SUBWIN_H_SIZE_SET(x) ((x) & 0x1FFF)
26 #define ISP2X_YUVAE_SUBWIN_V_SIZE_SET(x) (((x) & 0x1FFF) << 16)
28 #define ISP2X_RAWAE_LITE_ENA BIT(0)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/ti-vpe/
H A Dcsc.h13 #define CSC_CSC00 0x00
14 #define CSC_A0_MASK 0x1fff
15 #define CSC_A0_SHIFT 0
16 #define CSC_B0_MASK 0x1fff
19 #define CSC_CSC01 0x04
20 #define CSC_C0_MASK 0x1fff
21 #define CSC_C0_SHIFT 0
22 #define CSC_A1_MASK 0x1fff
25 #define CSC_CSC02 0x08
26 #define CSC_B1_MASK 0x1fff
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/meson/
H A Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dsbc8548.dts20 reg = <0xe0000000 0x5000>;
23 ranges = <0x0 0x0 0xff800000 0x00800000 /*8MB Flash*/
24 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
25 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
26 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
27 0x6 0x0 0xec000000 0x04000000>; /*64MB Flash*/
30 flash@0,0 {
34 reg = <0x0 0x0 0x800000>;
37 partition@0 {
40 reg = <0x00000000 0x007a0000>;
[all …]
H A Dsbc8548-altflash.dts23 reg = <0xe0000000 0x5000>;
26 ranges = <0x0 0x0 0xfc000000 0x04000000 /*64MB Flash*/
27 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
28 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
29 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
30 0x6 0x0 0xef800000 0x00800000>; /*8MB Flash*/
32 flash@0,0 {
35 reg = <0x0 0x0 0x04000000>;
39 partition@0 {
42 reg = <0x00000000 0x03f00000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/davinci/
H A Ddm355_ccdc_regs.h11 #define SYNCEN 0x00
12 #define MODESET 0x04
13 #define HDWIDTH 0x08
14 #define VDWIDTH 0x0c
15 #define PPLN 0x10
16 #define LPFR 0x14
17 #define SPH 0x18
18 #define NPH 0x1c
19 #define SLV0 0x20
20 #define SLV1 0x24
[all …]
H A Disif_regs.h9 #define SYNCEN 0x00
10 #define MODESET 0x04
11 #define HDW 0x08
12 #define VDW 0x0c
13 #define PPLN 0x10
14 #define LPFR 0x14
15 #define SPH 0x18
16 #define LNH 0x1c
17 #define SLV0 0x20
18 #define SLV1 0x24
[all …]
H A Ddm644x_ccdc_regs.h11 #define CCDC_PID 0x0
12 #define CCDC_PCR 0x4
13 #define CCDC_SYN_MODE 0x8
14 #define CCDC_HD_VD_WID 0xc
15 #define CCDC_PIX_LINES 0x10
16 #define CCDC_HORZ_INFO 0x14
17 #define CCDC_VERT_START 0x18
18 #define CCDC_VERT_LINES 0x1c
19 #define CCDC_CULLING 0x20
20 #define CCDC_HSIZE_OFF 0x24
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/xilinx/
H A Dxilinx-vtc.c66 * The following registers exist in two blocks, one at 0x0020 for the detector
67 * and one at 0x0060 for the generator.
70 #define XVTC_DETECTOR_OFFSET 0x0020
71 #define XVTC_GENERATOR_OFFSET 0x0060
73 #define XVTC_ACTIVE_SIZE 0x0000
75 #define XVTC_ACTIVE_VSIZE_MASK (0x1fff << 16)
76 #define XVTC_ACTIVE_HSIZE_SHIFT 0
77 #define XVTC_ACTIVE_HSIZE_MASK (0x1fff << 0)
79 #define XVTC_TIMING_STATUS 0x0004
82 #define XVTC_TIMING_STATUS_LOCKED (1 << 0)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/exynos/
H A Dregs-decon7.h11 #define VIDCON0 0x00
16 #define VIDCON0_ENVID_F (1 << 0)
19 #define VIDOUTCON0 0x4
21 #define VIDOUTCON0_DUAL_MASK (0x3 << 24)
22 #define VIDOUTCON0_DUAL_ON (0x3 << 24)
23 #define VIDOUTCON0_DISP_IF_1_ON (0x2 << 24)
24 #define VIDOUTCON0_DISP_IF_0_ON (0x1 << 24)
25 #define VIDOUTCON0_DUAL_OFF (0x0 << 24)
27 #define VIDOUTCON0_IF_MASK (0x1 << 23)
28 #define VIDOUTCON0_RGBIF (0x0 << 23)
[all …]
H A Dregs-gsc.h14 #define GSC_ENABLE 0x00
16 #define GSC_ENABLE_PP_UPDATE_TIME_CURR (0 << 9)
21 #define GSC_ENABLE_NORM_MODE (0 << 7)
31 #define GSC_ENABLE_ON (1 << 0)
34 #define GSC_SW_RESET 0x04
35 #define GSC_SW_RESET_SRESET (1 << 0)
38 #define GSC_IRQ 0x08
43 #define GSC_IRQ_ENABLE (1 << 0)
46 #define GSC_IN_CON 0x10
63 #define GSC_IN_RGB_SD_NARROW (0 << 14)
[all …]
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Dwm8350-regmap.c23 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Reset/ID */
24 { 0x7CFF, 0x0C00, 0x0000 }, /* R1 - ID */
25 { 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
26 { 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
27 { 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */
28 { 0x80FF, 0x80FF, 0x8000 }, /* R5 - System Hibernate */
29 { 0xFB0E, 0xFB0E, 0x0000 }, /* R6 - Interface Control */
30 { 0x0000, 0x0000, 0x0000 }, /* R7 */
31 { 0xE537, 0xE537, 0xFFFF }, /* R8 - Power mgmt (1) */
32 { 0x0FF3, 0x0FF3, 0xFFFF }, /* R9 - Power mgmt (2) */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/mediatek/
H A Dmtk_dpi_regs.h9 #define DPI_EN 0x00
10 #define EN BIT(0)
12 #define DPI_RET 0x04
13 #define RST BIT(0)
15 #define DPI_INTEN 0x08
16 #define INT_VSYNC_EN BIT(0)
20 #define DPI_INTSTA 0x0C
21 #define INT_VSYNC_STA BIT(0)
25 #define DPI_CON 0x10
26 #define BG_ENABLE BIT(0)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/rc/img-ir/
H A Dimg-ir-sanyo.c31 addr = (raw >> 0) & 0x1fff; in img_ir_sanyo_scancode()
32 addr_inv = (raw >> 13) & 0x1fff; in img_ir_sanyo_scancode()
33 data = (raw >> 26) & 0xff; in img_ir_sanyo_scancode()
34 data_inv = (raw >> 34) & 0xff; in img_ir_sanyo_scancode()
36 if ((data_inv ^ data) != 0xff) in img_ir_sanyo_scancode()
39 if ((addr_inv ^ addr) != 0x1fff) in img_ir_sanyo_scancode()
55 data = in->data & 0xff; in img_ir_sanyo_filter()
56 data_m = in->mask & 0xff; in img_ir_sanyo_filter()
57 data_inv = data ^ 0xff; in img_ir_sanyo_filter()
59 if (in->data & 0xff700000) in img_ir_sanyo_filter()
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/sm750fb/
H A Dsm750_accel.h5 #define HW_ROP2_COPY 0xc
6 #define HW_ROP2_XOR 0x6
8 /* notes: below address are the offset value from de_base_address (0x100000)*/
11 #define DE_BASE_ADDR_TYPE1 0x100000
13 #define DE_BASE_ADDR_TYPE2 0x8000
15 #define DE_BASE_ADDR_TYPE3 0
18 #define DE_PORT_ADDR_TYPE1 0x110000
20 #define DE_PORT_ADDR_TYPE2 0x100000
22 #define DE_PORT_ADDR_TYPE3 0x100000
24 #define DE_SOURCE 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7722.c18 #define FRQCR 0xa4150000
19 #define VCLKCR 0xa4150004
20 #define SCLKACR 0xa4150008
21 #define SCLKBCR 0xa415000c
22 #define IRDACLKCR 0xa4150018
23 #define PLLCR 0xa4150024
24 #define MSTPCR0 0xa4150030
25 #define MSTPCR1 0xa4150034
26 #define MSTPCR2 0xa4150038
27 #define DLLFRQ 0xa4150050
[all …]
H A Dclock-sh7343.c16 #define FRQCR 0xa4150000
17 #define VCLKCR 0xa4150004
18 #define SCLKACR 0xa4150008
19 #define SCLKBCR 0xa415000c
20 #define PLLCR 0xa4150024
21 #define MSTPCR0 0xa4150030
22 #define MSTPCR1 0xa4150034
23 #define MSTPCR2 0xa4150038
24 #define DLLFRQ 0xa4150050
44 if (__raw_readl(PLLCR) & 0x1000) in dll_recalc()
[all …]
H A Dclock-sh7366.c16 #define FRQCR 0xa4150000
17 #define VCLKCR 0xa4150004
18 #define SCLKACR 0xa4150008
19 #define SCLKBCR 0xa415000c
20 #define PLLCR 0xa4150024
21 #define MSTPCR0 0xa4150030
22 #define MSTPCR1 0xa4150034
23 #define MSTPCR2 0xa4150038
24 #define DLLFRQ 0xa4150050
44 if (__raw_readl(PLLCR) & 0x1000) in dll_recalc()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dvop_rk3288.h72 check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c);
75 ARGB8888 = 0,
81 LB_YUV_3840X5 = 0x0,
82 LB_YUV_2560X8 = 0x1,
83 LB_RGB_3840X2 = 0x2,
84 LB_RGB_2560X4 = 0x3,
85 LB_RGB_1920X5 = 0x4,
86 LB_RGB_1280X8 = 0x5
90 VOP_MODE_EDP = 0,
100 #define M_FPGA_VERSION (0xffff << 16)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gvt/
H A Dfb_decoder.h43 #define _PIPE_V_SRCSZ_SHIFT 0
44 #define _PIPE_V_SRCSZ_MASK (0xfff << _PIPE_V_SRCSZ_SHIFT)
46 #define _PIPE_H_SRCSZ_MASK (0x1fff << _PIPE_H_SRCSZ_SHIFT)
49 #define _PRI_PLANE_STRIDE_MASK (0x3ff << 6)
50 #define _PRI_PLANE_X_OFF_SHIFT 0
51 #define _PRI_PLANE_X_OFF_MASK (0x1fff << _PRI_PLANE_X_OFF_SHIFT)
53 #define _PRI_PLANE_Y_OFF_MASK (0xfff << _PRI_PLANE_Y_OFF_SHIFT)
55 #define _CURSOR_MODE 0x3f
57 #define _CURSOR_ALPHA_FORCE_MASK (0x3 << _CURSOR_ALPHA_FORCE_SHIFT)
59 #define _CURSOR_ALPHA_PLANE_MASK (0x3 << _CURSOR_ALPHA_PLANE_SHIFT)
[all …]
/OK3568_Linux_fs/kernel/include/dt-bindings/pinctrl/
H A Dk3.h16 #define PULL_ENABLE (0 << PULLUDEN_SHIFT)
19 #define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE)
22 #define INPUT_DISABLE (0 << RXACTIVE_SHIFT)
32 #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
33 #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
35 #define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
36 #define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_util.c15 #define QSEED3_HW_VERSION 0x00
16 #define QSEED3_OP_MODE 0x04
17 #define QSEED3_RGB2Y_COEFF 0x08
18 #define QSEED3_PHASE_INIT 0x0C
19 #define QSEED3_PHASE_STEP_Y_H 0x10
20 #define QSEED3_PHASE_STEP_Y_V 0x14
21 #define QSEED3_PHASE_STEP_UV_H 0x18
22 #define QSEED3_PHASE_STEP_UV_V 0x1C
23 #define QSEED3_PRELOAD 0x20
24 #define QSEED3_DE_SHARPEN 0x24
[all …]
/OK3568_Linux_fs/kernel/drivers/input/gameport/
H A Dfm801-gp.c18 #define PCI_VENDOR_ID_FORTEMEDIA 0x1319
19 #define PCI_DEVICE_ID_FM801_GP 0x0802
34 *buttons = (~w >> 14) & 0x03; in fm801_gp_cooked_read()
35 axes[0] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
37 axes[1] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
39 *buttons |= ((~w >> 14) & 0x03) << 2; in fm801_gp_cooked_read()
40 axes[2] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
42 axes[3] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
43 outw(0xff, gameport->io); /* reset */ in fm801_gp_cooked_read()
45 return 0; in fm801_gp_cooked_read()
[all …]

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