1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2008-2009 Texas Instruments Inc 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef _ISIF_REGS_H 6*4882a593Smuzhiyun #define _ISIF_REGS_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* ISIF registers relative offsets */ 9*4882a593Smuzhiyun #define SYNCEN 0x00 10*4882a593Smuzhiyun #define MODESET 0x04 11*4882a593Smuzhiyun #define HDW 0x08 12*4882a593Smuzhiyun #define VDW 0x0c 13*4882a593Smuzhiyun #define PPLN 0x10 14*4882a593Smuzhiyun #define LPFR 0x14 15*4882a593Smuzhiyun #define SPH 0x18 16*4882a593Smuzhiyun #define LNH 0x1c 17*4882a593Smuzhiyun #define SLV0 0x20 18*4882a593Smuzhiyun #define SLV1 0x24 19*4882a593Smuzhiyun #define LNV 0x28 20*4882a593Smuzhiyun #define CULH 0x2c 21*4882a593Smuzhiyun #define CULV 0x30 22*4882a593Smuzhiyun #define HSIZE 0x34 23*4882a593Smuzhiyun #define SDOFST 0x38 24*4882a593Smuzhiyun #define CADU 0x3c 25*4882a593Smuzhiyun #define CADL 0x40 26*4882a593Smuzhiyun #define LINCFG0 0x44 27*4882a593Smuzhiyun #define LINCFG1 0x48 28*4882a593Smuzhiyun #define CCOLP 0x4c 29*4882a593Smuzhiyun #define CRGAIN 0x50 30*4882a593Smuzhiyun #define CGRGAIN 0x54 31*4882a593Smuzhiyun #define CGBGAIN 0x58 32*4882a593Smuzhiyun #define CBGAIN 0x5c 33*4882a593Smuzhiyun #define COFSTA 0x60 34*4882a593Smuzhiyun #define FLSHCFG0 0x64 35*4882a593Smuzhiyun #define FLSHCFG1 0x68 36*4882a593Smuzhiyun #define FLSHCFG2 0x6c 37*4882a593Smuzhiyun #define VDINT0 0x70 38*4882a593Smuzhiyun #define VDINT1 0x74 39*4882a593Smuzhiyun #define VDINT2 0x78 40*4882a593Smuzhiyun #define MISC 0x7c 41*4882a593Smuzhiyun #define CGAMMAWD 0x80 42*4882a593Smuzhiyun #define REC656IF 0x84 43*4882a593Smuzhiyun #define CCDCFG 0x88 44*4882a593Smuzhiyun /***************************************************** 45*4882a593Smuzhiyun * Defect Correction registers 46*4882a593Smuzhiyun *****************************************************/ 47*4882a593Smuzhiyun #define DFCCTL 0x8c 48*4882a593Smuzhiyun #define VDFSATLV 0x90 49*4882a593Smuzhiyun #define DFCMEMCTL 0x94 50*4882a593Smuzhiyun #define DFCMEM0 0x98 51*4882a593Smuzhiyun #define DFCMEM1 0x9c 52*4882a593Smuzhiyun #define DFCMEM2 0xa0 53*4882a593Smuzhiyun #define DFCMEM3 0xa4 54*4882a593Smuzhiyun #define DFCMEM4 0xa8 55*4882a593Smuzhiyun /**************************************************** 56*4882a593Smuzhiyun * Black Clamp registers 57*4882a593Smuzhiyun ****************************************************/ 58*4882a593Smuzhiyun #define CLAMPCFG 0xac 59*4882a593Smuzhiyun #define CLDCOFST 0xb0 60*4882a593Smuzhiyun #define CLSV 0xb4 61*4882a593Smuzhiyun #define CLHWIN0 0xb8 62*4882a593Smuzhiyun #define CLHWIN1 0xbc 63*4882a593Smuzhiyun #define CLHWIN2 0xc0 64*4882a593Smuzhiyun #define CLVRV 0xc4 65*4882a593Smuzhiyun #define CLVWIN0 0xc8 66*4882a593Smuzhiyun #define CLVWIN1 0xcc 67*4882a593Smuzhiyun #define CLVWIN2 0xd0 68*4882a593Smuzhiyun #define CLVWIN3 0xd4 69*4882a593Smuzhiyun /**************************************************** 70*4882a593Smuzhiyun * Lense Shading Correction 71*4882a593Smuzhiyun ****************************************************/ 72*4882a593Smuzhiyun #define DATAHOFST 0xd8 73*4882a593Smuzhiyun #define DATAVOFST 0xdc 74*4882a593Smuzhiyun #define LSCHVAL 0xe0 75*4882a593Smuzhiyun #define LSCVVAL 0xe4 76*4882a593Smuzhiyun #define TWODLSCCFG 0xe8 77*4882a593Smuzhiyun #define TWODLSCOFST 0xec 78*4882a593Smuzhiyun #define TWODLSCINI 0xf0 79*4882a593Smuzhiyun #define TWODLSCGRBU 0xf4 80*4882a593Smuzhiyun #define TWODLSCGRBL 0xf8 81*4882a593Smuzhiyun #define TWODLSCGROF 0xfc 82*4882a593Smuzhiyun #define TWODLSCORBU 0x100 83*4882a593Smuzhiyun #define TWODLSCORBL 0x104 84*4882a593Smuzhiyun #define TWODLSCOROF 0x108 85*4882a593Smuzhiyun #define TWODLSCIRQEN 0x10c 86*4882a593Smuzhiyun #define TWODLSCIRQST 0x110 87*4882a593Smuzhiyun /**************************************************** 88*4882a593Smuzhiyun * Data formatter 89*4882a593Smuzhiyun ****************************************************/ 90*4882a593Smuzhiyun #define FMTCFG 0x114 91*4882a593Smuzhiyun #define FMTPLEN 0x118 92*4882a593Smuzhiyun #define FMTSPH 0x11c 93*4882a593Smuzhiyun #define FMTLNH 0x120 94*4882a593Smuzhiyun #define FMTSLV 0x124 95*4882a593Smuzhiyun #define FMTLNV 0x128 96*4882a593Smuzhiyun #define FMTRLEN 0x12c 97*4882a593Smuzhiyun #define FMTHCNT 0x130 98*4882a593Smuzhiyun #define FMTAPTR_BASE 0x134 99*4882a593Smuzhiyun /* Below macro for addresses FMTAPTR0 - FMTAPTR15 */ 100*4882a593Smuzhiyun #define FMTAPTR(i) (FMTAPTR_BASE + (i * 4)) 101*4882a593Smuzhiyun #define FMTPGMVF0 0x174 102*4882a593Smuzhiyun #define FMTPGMVF1 0x178 103*4882a593Smuzhiyun #define FMTPGMAPU0 0x17c 104*4882a593Smuzhiyun #define FMTPGMAPU1 0x180 105*4882a593Smuzhiyun #define FMTPGMAPS0 0x184 106*4882a593Smuzhiyun #define FMTPGMAPS1 0x188 107*4882a593Smuzhiyun #define FMTPGMAPS2 0x18c 108*4882a593Smuzhiyun #define FMTPGMAPS3 0x190 109*4882a593Smuzhiyun #define FMTPGMAPS4 0x194 110*4882a593Smuzhiyun #define FMTPGMAPS5 0x198 111*4882a593Smuzhiyun #define FMTPGMAPS6 0x19c 112*4882a593Smuzhiyun #define FMTPGMAPS7 0x1a0 113*4882a593Smuzhiyun /************************************************ 114*4882a593Smuzhiyun * Color Space Converter 115*4882a593Smuzhiyun ************************************************/ 116*4882a593Smuzhiyun #define CSCCTL 0x1a4 117*4882a593Smuzhiyun #define CSCM0 0x1a8 118*4882a593Smuzhiyun #define CSCM1 0x1ac 119*4882a593Smuzhiyun #define CSCM2 0x1b0 120*4882a593Smuzhiyun #define CSCM3 0x1b4 121*4882a593Smuzhiyun #define CSCM4 0x1b8 122*4882a593Smuzhiyun #define CSCM5 0x1bc 123*4882a593Smuzhiyun #define CSCM6 0x1c0 124*4882a593Smuzhiyun #define CSCM7 0x1c4 125*4882a593Smuzhiyun #define OBWIN0 0x1c8 126*4882a593Smuzhiyun #define OBWIN1 0x1cc 127*4882a593Smuzhiyun #define OBWIN2 0x1d0 128*4882a593Smuzhiyun #define OBWIN3 0x1d4 129*4882a593Smuzhiyun #define OBVAL0 0x1d8 130*4882a593Smuzhiyun #define OBVAL1 0x1dc 131*4882a593Smuzhiyun #define OBVAL2 0x1e0 132*4882a593Smuzhiyun #define OBVAL3 0x1e4 133*4882a593Smuzhiyun #define OBVAL4 0x1e8 134*4882a593Smuzhiyun #define OBVAL5 0x1ec 135*4882a593Smuzhiyun #define OBVAL6 0x1f0 136*4882a593Smuzhiyun #define OBVAL7 0x1f4 137*4882a593Smuzhiyun #define CLKCTL 0x1f8 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* Masks & Shifts below */ 140*4882a593Smuzhiyun #define START_PX_HOR_MASK 0x7FFF 141*4882a593Smuzhiyun #define NUM_PX_HOR_MASK 0x7FFF 142*4882a593Smuzhiyun #define START_VER_ONE_MASK 0x7FFF 143*4882a593Smuzhiyun #define START_VER_TWO_MASK 0x7FFF 144*4882a593Smuzhiyun #define NUM_LINES_VER 0x7FFF 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* gain - offset masks */ 147*4882a593Smuzhiyun #define GAIN_INTEGER_SHIFT 9 148*4882a593Smuzhiyun #define OFFSET_MASK 0xFFF 149*4882a593Smuzhiyun #define GAIN_SDRAM_EN_SHIFT 12 150*4882a593Smuzhiyun #define GAIN_IPIPE_EN_SHIFT 13 151*4882a593Smuzhiyun #define GAIN_H3A_EN_SHIFT 14 152*4882a593Smuzhiyun #define OFST_SDRAM_EN_SHIFT 8 153*4882a593Smuzhiyun #define OFST_IPIPE_EN_SHIFT 9 154*4882a593Smuzhiyun #define OFST_H3A_EN_SHIFT 10 155*4882a593Smuzhiyun #define GAIN_OFFSET_EN_MASK 0x7700 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* Culling */ 158*4882a593Smuzhiyun #define CULL_PAT_EVEN_LINE_SHIFT 8 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* CCDCFG register */ 161*4882a593Smuzhiyun #define ISIF_YCINSWP_RAW (0x00 << 4) 162*4882a593Smuzhiyun #define ISIF_YCINSWP_YCBCR (0x01 << 4) 163*4882a593Smuzhiyun #define ISIF_CCDCFG_FIDMD_LATCH_VSYNC (0x00 << 6) 164*4882a593Smuzhiyun #define ISIF_CCDCFG_WENLOG_AND (0x00 << 8) 165*4882a593Smuzhiyun #define ISIF_CCDCFG_TRGSEL_WEN (0x00 << 9) 166*4882a593Smuzhiyun #define ISIF_CCDCFG_EXTRG_DISABLE (0x00 << 10) 167*4882a593Smuzhiyun #define ISIF_LATCH_ON_VSYNC_DISABLE (0x01 << 15) 168*4882a593Smuzhiyun #define ISIF_LATCH_ON_VSYNC_ENABLE (0x00 << 15) 169*4882a593Smuzhiyun #define ISIF_DATA_PACK_MASK 3 170*4882a593Smuzhiyun #define ISIF_DATA_PACK16 0 171*4882a593Smuzhiyun #define ISIF_DATA_PACK12 1 172*4882a593Smuzhiyun #define ISIF_DATA_PACK8 2 173*4882a593Smuzhiyun #define ISIF_PIX_ORDER_SHIFT 11 174*4882a593Smuzhiyun #define ISIF_BW656_ENABLE (0x01 << 5) 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* MODESET registers */ 177*4882a593Smuzhiyun #define ISIF_VDHDOUT_INPUT (0x00 << 0) 178*4882a593Smuzhiyun #define ISIF_INPUT_SHIFT 12 179*4882a593Smuzhiyun #define ISIF_RAW_INPUT_MODE 0 180*4882a593Smuzhiyun #define ISIF_FID_POL_SHIFT 4 181*4882a593Smuzhiyun #define ISIF_HD_POL_SHIFT 3 182*4882a593Smuzhiyun #define ISIF_VD_POL_SHIFT 2 183*4882a593Smuzhiyun #define ISIF_DATAPOL_NORMAL 0 184*4882a593Smuzhiyun #define ISIF_DATAPOL_SHIFT 6 185*4882a593Smuzhiyun #define ISIF_EXWEN_DISABLE 0 186*4882a593Smuzhiyun #define ISIF_EXWEN_SHIFT 5 187*4882a593Smuzhiyun #define ISIF_FRM_FMT_SHIFT 7 188*4882a593Smuzhiyun #define ISIF_DATASFT_SHIFT 8 189*4882a593Smuzhiyun #define ISIF_LPF_SHIFT 14 190*4882a593Smuzhiyun #define ISIF_LPF_MASK 1 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /* GAMMAWD registers */ 193*4882a593Smuzhiyun #define ISIF_ALAW_GAMMA_WD_MASK 0xF 194*4882a593Smuzhiyun #define ISIF_ALAW_GAMMA_WD_SHIFT 1 195*4882a593Smuzhiyun #define ISIF_ALAW_ENABLE 1 196*4882a593Smuzhiyun #define ISIF_GAMMAWD_CFA_SHIFT 5 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* HSIZE registers */ 199*4882a593Smuzhiyun #define ISIF_HSIZE_FLIP_MASK 1 200*4882a593Smuzhiyun #define ISIF_HSIZE_FLIP_SHIFT 12 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* MISC registers */ 203*4882a593Smuzhiyun #define ISIF_DPCM_EN_SHIFT 12 204*4882a593Smuzhiyun #define ISIF_DPCM_PREDICTOR_SHIFT 13 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun /* Black clamp related */ 207*4882a593Smuzhiyun #define ISIF_BC_MODE_COLOR_SHIFT 4 208*4882a593Smuzhiyun #define ISIF_HORZ_BC_MODE_SHIFT 1 209*4882a593Smuzhiyun #define ISIF_HORZ_BC_WIN_SEL_SHIFT 5 210*4882a593Smuzhiyun #define ISIF_HORZ_BC_PIX_LIMIT_SHIFT 6 211*4882a593Smuzhiyun #define ISIF_HORZ_BC_WIN_H_SIZE_SHIFT 8 212*4882a593Smuzhiyun #define ISIF_HORZ_BC_WIN_V_SIZE_SHIFT 12 213*4882a593Smuzhiyun #define ISIF_VERT_BC_RST_VAL_SEL_SHIFT 4 214*4882a593Smuzhiyun #define ISIF_VERT_BC_LINE_AVE_COEF_SHIFT 8 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun /* VDFC registers */ 217*4882a593Smuzhiyun #define ISIF_VDFC_EN_SHIFT 4 218*4882a593Smuzhiyun #define ISIF_VDFC_CORR_MOD_SHIFT 5 219*4882a593Smuzhiyun #define ISIF_VDFC_CORR_WHOLE_LN_SHIFT 7 220*4882a593Smuzhiyun #define ISIF_VDFC_LEVEL_SHFT_SHIFT 8 221*4882a593Smuzhiyun #define ISIF_VDFC_POS_MASK 0x1FFF 222*4882a593Smuzhiyun #define ISIF_DFCMEMCTL_DFCMARST_SHIFT 2 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /* CSC registers */ 225*4882a593Smuzhiyun #define ISIF_CSC_COEF_INTEG_MASK 7 226*4882a593Smuzhiyun #define ISIF_CSC_COEF_DECIMAL_MASK 0x1f 227*4882a593Smuzhiyun #define ISIF_CSC_COEF_INTEG_SHIFT 5 228*4882a593Smuzhiyun #define ISIF_CSCM_MSB_SHIFT 8 229*4882a593Smuzhiyun #define ISIF_DF_CSC_SPH_MASK 0x1FFF 230*4882a593Smuzhiyun #define ISIF_DF_CSC_LNH_MASK 0x1FFF 231*4882a593Smuzhiyun #define ISIF_DF_CSC_SLV_MASK 0x1FFF 232*4882a593Smuzhiyun #define ISIF_DF_CSC_LNV_MASK 0x1FFF 233*4882a593Smuzhiyun #define ISIF_DF_NUMLINES 0x7FFF 234*4882a593Smuzhiyun #define ISIF_DF_NUMPIX 0x1FFF 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun /* Offsets for LSC/DFC/Gain */ 237*4882a593Smuzhiyun #define ISIF_DATA_H_OFFSET_MASK 0x1FFF 238*4882a593Smuzhiyun #define ISIF_DATA_V_OFFSET_MASK 0x1FFF 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* Linearization */ 241*4882a593Smuzhiyun #define ISIF_LIN_CORRSFT_SHIFT 4 242*4882a593Smuzhiyun #define ISIF_LIN_SCALE_FACT_INTEG_SHIFT 10 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun /* Pattern registers */ 246*4882a593Smuzhiyun #define ISIF_PG_EN (1 << 3) 247*4882a593Smuzhiyun #define ISIF_SEL_PG_SRC (3 << 4) 248*4882a593Smuzhiyun #define ISIF_PG_VD_POL_SHIFT 0 249*4882a593Smuzhiyun #define ISIF_PG_HD_POL_SHIFT 1 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun /*random other junk*/ 252*4882a593Smuzhiyun #define ISIF_SYNCEN_VDHDEN_MASK (1 << 0) 253*4882a593Smuzhiyun #define ISIF_SYNCEN_WEN_MASK (1 << 1) 254*4882a593Smuzhiyun #define ISIF_SYNCEN_WEN_SHIFT 1 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun #endif 257