1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013 Texas Instruments Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * David Griego, <dagriego@biglakesoftware.com> 6*4882a593Smuzhiyun * Dale Farnsworth, <dale@farnsworth.org> 7*4882a593Smuzhiyun * Archit Taneja, <archit@ti.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef TI_CSC_H 10*4882a593Smuzhiyun #define TI_CSC_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* VPE color space converter regs */ 13*4882a593Smuzhiyun #define CSC_CSC00 0x00 14*4882a593Smuzhiyun #define CSC_A0_MASK 0x1fff 15*4882a593Smuzhiyun #define CSC_A0_SHIFT 0 16*4882a593Smuzhiyun #define CSC_B0_MASK 0x1fff 17*4882a593Smuzhiyun #define CSC_B0_SHIFT 16 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CSC_CSC01 0x04 20*4882a593Smuzhiyun #define CSC_C0_MASK 0x1fff 21*4882a593Smuzhiyun #define CSC_C0_SHIFT 0 22*4882a593Smuzhiyun #define CSC_A1_MASK 0x1fff 23*4882a593Smuzhiyun #define CSC_A1_SHIFT 16 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CSC_CSC02 0x08 26*4882a593Smuzhiyun #define CSC_B1_MASK 0x1fff 27*4882a593Smuzhiyun #define CSC_B1_SHIFT 0 28*4882a593Smuzhiyun #define CSC_C1_MASK 0x1fff 29*4882a593Smuzhiyun #define CSC_C1_SHIFT 16 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CSC_CSC03 0x0c 32*4882a593Smuzhiyun #define CSC_A2_MASK 0x1fff 33*4882a593Smuzhiyun #define CSC_A2_SHIFT 0 34*4882a593Smuzhiyun #define CSC_B2_MASK 0x1fff 35*4882a593Smuzhiyun #define CSC_B2_SHIFT 16 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define CSC_CSC04 0x10 38*4882a593Smuzhiyun #define CSC_C2_MASK 0x1fff 39*4882a593Smuzhiyun #define CSC_C2_SHIFT 0 40*4882a593Smuzhiyun #define CSC_D0_MASK 0x0fff 41*4882a593Smuzhiyun #define CSC_D0_SHIFT 16 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CSC_CSC05 0x14 44*4882a593Smuzhiyun #define CSC_D1_MASK 0x0fff 45*4882a593Smuzhiyun #define CSC_D1_SHIFT 0 46*4882a593Smuzhiyun #define CSC_D2_MASK 0x0fff 47*4882a593Smuzhiyun #define CSC_D2_SHIFT 16 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define CSC_BYPASS (1 << 28) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct csc_data { 52*4882a593Smuzhiyun void __iomem *base; 53*4882a593Smuzhiyun struct resource *res; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun struct platform_device *pdev; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun void csc_dump_regs(struct csc_data *csc); 59*4882a593Smuzhiyun void csc_set_coeff_bypass(struct csc_data *csc, u32 *csc_reg5); 60*4882a593Smuzhiyun void csc_set_coeff(struct csc_data *csc, u32 *csc_reg0, 61*4882a593Smuzhiyun struct v4l2_format *src_fmt, struct v4l2_format *dst_fmt); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct csc_data *csc_create(struct platform_device *pdev, const char *res_name); 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif 66