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/OK3568_Linux_fs/kernel/drivers/staging/rts5208/
H A Dms.h19 #define MS_EXTRA_SIZE 0x9
21 #define WRT_PRTCT 0x01
24 #define MS_NO_ERROR 0x00
25 #define MS_CRC16_ERROR 0x80
26 #define MS_TO_ERROR 0x40
27 #define MS_NO_CARD 0x20
28 #define MS_NO_MEMORY 0x10
29 #define MS_CMD_NK 0x08
30 #define MS_FLASH_READ_ERROR 0x04
31 #define MS_FLASH_WRITE_ERROR 0x02
[all …]
/OK3568_Linux_fs/kernel/drivers/ide/
H A Dide-generic.c24 module_param(probe_mask, int, 0);
33 static const u16 legacy_bases[] = { 0x1f0 };
36 static const u16 legacy_bases[] = { 0x1f0, 0x170, 0x1e8, 0x168 };
39 static const u16 legacy_bases[] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
50 if (pci_resource_start(p, 0) == 0x1f0) in ide_generic_check_pci_legacy_iobases()
52 if (pci_resource_start(p, 2) == 0x170) in ide_generic_check_pci_legacy_iobases()
55 /* Cyrix CS55{1,2}0 pre SFF MWDMA ATA on the bridge */ in ide_generic_check_pci_legacy_iobases()
64 pci_read_config_word(p, 0x6C, &val); in ide_generic_check_pci_legacy_iobases()
65 if (val & 0x8000) { in ide_generic_check_pci_legacy_iobases()
67 if (val & 0x4000) in ide_generic_check_pci_legacy_iobases()
[all …]
H A Dq40ide.c28 #define PCIDE_BASE1 0x1f0
29 #define PCIDE_BASE2 0x170
30 #define PCIDE_BASE3 0x1e8
31 #define PCIDE_BASE4 0x168
32 #define PCIDE_BASE5 0x1e0
33 #define PCIDE_BASE6 0x160
43 case 0x1f0: return 14; in q40ide_default_irq()
44 case 0x170: return 15; in q40ide_default_irq()
45 case 0x1e8: return 11; in q40ide_default_irq()
47 return 0; in q40ide_default_irq()
[all …]
H A Dopti621.c24 #define READ_REG 0 /* index of Read cycle timing register */
35 * is at reg_base (0x1f0 primary, 0x170 secondary,
45 outb(0x83, reg_base + 2); in write_reg()
49 * is at reg_base (0x1f0 primary, 0x170 secondary,
55 u8 ret = 0; in read_reg()
61 outb(0x83, reg_base + 2); in read_reg()
76 { 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */ in opti621_set_pio_mode()
77 { 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */ in opti621_set_pio_mode()
80 { 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */ in opti621_set_pio_mode()
81 { 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */ in opti621_set_pio_mode()
[all …]
H A Dide-legacy.c13 if (port_no == 0) { in ide_legacy_init_one()
14 base = 0x1f0; in ide_legacy_init_one()
15 ctl = 0x3f6; in ide_legacy_init_one()
18 base = 0x170; in ide_legacy_init_one()
19 ctl = 0x376; in ide_legacy_init_one()
24 printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX not free.\n", in ide_legacy_init_one()
30 printk(KERN_ERR "%s: I/O resource 0x%lX not free.\n", in ide_legacy_init_one()
47 memset(&hw, 0, sizeof(hw)); in ide_legacy_device_add()
49 if ((d->host_flags & IDE_HFLAG_QD_2ND_PORT) == 0) in ide_legacy_device_add()
50 ide_legacy_init_one(hws, &hw[0], 0, d, config); in ide_legacy_device_add()
[all …]
/OK3568_Linux_fs/kernel/arch/mips/mm/
H A Dcex-sb1.S31 * the L1 and L2) since it is fetched as 0xa0000100.
35 * (0x170-0x17f) are used to preserve k0, k1, and ra.
48 sd k0,0x170($0)
49 sd k1,0x178($0)
69 mtc0 $0,C0_CERR_D
101 andi k0,0x1fe0
108 cache Index_Invalidate_I,(0<<13)(k0)
117 ld k0,0x170($0)
118 ld k1,0x178($0)
140 bnezl $0, 1f
/OK3568_Linux_fs/kernel/Documentation/fault-injection/
H A Dnvme-fault-injection.rst33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/
H A Dzte,vou.txt79 ranges = <0 0x1440000 0x10000>;
81 dpc: dpc@0 {
83 reg = <0x0000 0x1000>, <0x1000 0x1000>,
84 <0x5000 0x1000>, <0x6000 0x1000>,
85 <0xa000 0x1000>;
98 reg = <0x8000 0x1000>;
102 zte,vga-power-control = <&sysctrl 0x170 0xe0>;
107 reg = <0xc000 0x4000>;
117 reg = <0x2000 0x1000>;
118 zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
/OK3568_Linux_fs/kernel/arch/sparc/kernel/
H A Dkprobes.c31 * - Set regs->tpc to point to kprobe->ainsn.insn[0]
52 if ((unsigned long) p->addr & 0x3UL) in arch_prepare_kprobe()
55 p->ainsn.insn[0] = *p->addr; in arch_prepare_kprobe()
56 flushi(&p->ainsn.insn[0]); in arch_prepare_kprobe()
62 return 0; in arch_prepare_kprobe()
111 regs->tpc = (unsigned long) &p->ainsn.insn[0]; in prepare_singlestep()
120 int ret = 0; in kprobe_handler()
207 if (regs->tnpc == regs->tpc + 0x4UL) in relbranch_fixup()
208 return real_pc + 0x8UL; in relbranch_fixup()
213 if ((insn & 0xc0000000) == 0x40000000 || in relbranch_fixup()
[all …]
/OK3568_Linux_fs/kernel/drivers/ata/
H A Dpata_legacy.c66 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
69 BIOS = 0,
112 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
127 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
162 struct legacy_probe *lp = &probe_list[0]; in legacy_probe_add()
166 for (i = 0; i < NR_HOST; i++) { in legacy_probe_add()
167 if (lp->port == 0 && free == NULL) in legacy_probe_add()
185 return 0; in legacy_probe_add()
213 return 0; in legacy_set_mode()
229 * do this. The mode range can be set if it is not 0x1F by setting
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/qualcomm/
H A Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/OK3568_Linux_fs/kernel/tools/testing/selftests/kvm/lib/x86_64/
H A Dsvm.c34 0x10000, 0, 0); in vcpu_alloc_svm()
38 0x10000, 0, 0); in vcpu_alloc_svm()
43 0x10000, 0, 0); in vcpu_alloc_svm()
69 asm volatile ("rep stosl" : "+c"(n), "+D"(vmcb) : "a"(0) : "memory"); in clear_vmcb()
89 asm volatile ("vmsave %0\n\t" : : "a" (vmcb_gpa) : "memory"); in generic_svm_setup()
90 vmcb_set_seg(&save->es, get_es(), 0, -1U, data_seg_attr); in generic_svm_setup()
91 vmcb_set_seg(&save->cs, get_cs(), 0, -1U, code_seg_attr); in generic_svm_setup()
92 vmcb_set_seg(&save->ss, get_ss(), 0, -1U, data_seg_attr); in generic_svm_setup()
93 vmcb_set_seg(&save->ds, get_ds(), 0, -1U, data_seg_attr); in generic_svm_setup()
94 vmcb_set_seg(&save->gdtr, 0, get_gdt().address, get_gdt().size, 0); in generic_svm_setup()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dsprd-mcdt.txt17 reg = <0 0x41490000 0 0x170>;
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/
H A Dusb.h13 /* 0x000 */
19 /* 0x010 */
24 /* 0x020 */
27 /* 0x100 */
34 /* 0x120 */
40 /* 0x130 */
43 /* 0x140 */
49 /* 0x150 */
55 /* 0x160 */
61 /* 0x170 */
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dqemu-x86.h18 #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \
19 "stdout=serial,vidconsole\0" \
20 "stderr=serial,vidconsole\0"
29 #define CONFIG_SYS_ATA_BASE_ADDR 0
30 #define CONFIG_SYS_ATA_DATA_OFFSET 0
31 #define CONFIG_SYS_ATA_REG_OFFSET 0
32 #define CONFIG_SYS_ATA_ALT_OFFSET 0
33 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
34 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
41 #define CONFIG_SPL_TEXT_BASE 0xfffd0000
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dimx6dl-pinfunc.h17 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/mips/configs/
H A Dmpc30x_defconfig53 CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73"
H A Dworkpad_defconfig65 CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M"
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/OK3568_Linux_fs/kernel/drivers/tty/serial/8250/
H A D8250_boca.c13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dfdomain_isa.c10 static int io[MAXBOARDS_PARAM] = { 0, 0, 0, 0 };
11 module_param_hw_array(io, int, ioport, NULL, 0);
12 MODULE_PARM_DESC(io, "base I/O address of controller (0x140, 0x150, 0x160, 0x170)");
14 static int irq[MAXBOARDS_PARAM] = { 0, 0, 0, 0 };
15 module_param_hw_array(irq, int, irq, NULL, 0);
16 MODULE_PARM_DESC(irq, "IRQ of controller (0=auto [default])");
18 static int scsi_id[MAXBOARDS_PARAM] = { 0, 0, 0, 0 };
19 module_param_hw_array(scsi_id, int, other, NULL, 0);
23 0xc8000,
24 0xca000,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-davinci/
H A Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]

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