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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Drockchip,rk3228-codec.txt17 reg = <0x12010000 0x1000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dhisi-crg.txt39 reg = <0x12010000 0x10000>;
47 reg = <0x12110000 0x1000>;
49 resets = <&CRG 0xe4 0>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dsysctrl.yaml58 cpu 2, reg + 0x4;
59 cpu 3, reg + 0x8;
99 ranges = <0 0x802000 0x1000>;
100 reg = <0x802000 0x1000>;
102 smp-offset = <0x31c>;
103 resume-offset = <0x308>;
104 reboot-offset = <0x4>;
106 clock: clock@0 {
108 reg = <0 0x10000>;
116 reg = <0x10000000 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dhi3519.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
28 reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
33 #clock-cells = <0>;
41 reg = <0x12010000 0x10000>;
53 reg = <0x12100000 0x1000>;
62 reg = <0x12101000 0x1000>;
71 reg = <0x12102000 0x1000>;
80 reg = <0x12103000 0x1000>;
[all …]
H A Drk3128x.dtsi32 #size-cells = <0>;
37 reg = <0xf00>;
50 reg = <0xf01>;
59 reg = <0xf02>;
68 reg = <0xf03>;
81 0 254 20
86 1 4 0
134 reg = <0x110f0000 0x4000>;
135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
180 1 5 0
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/ssv6xxx/include/
H A Dssv6200_configuration.h18 {0xce0071bc, 0x565B565B},
19 {0xce000008, 0x0000006a},
20 {0xce00000c, 0x00000064},
21 {0xce000010, 0x00007FFF},
22 {0xce000014, 0x00000003},
23 {0xce000018, 0x0055003C},
24 {0xce00001c, 0x00000064},
25 {0xce000020, 0x20000000},
26 {0xce00002c, 0x00000000},
27 {0xce000030, 0x80046072},
[all …]
H A Dssv6200_reg.h17 #define SYS_REG_BASE 0xc0000000
18 #define WBOOT_REG_BASE 0xc0000100
19 #define TU0_US_REG_BASE 0xc0000200
20 #define TU1_US_REG_BASE 0xc0000210
21 #define TU2_US_REG_BASE 0xc0000220
22 #define TU3_US_REG_BASE 0xc0000230
23 #define TM0_MS_REG_BASE 0xc0000240
24 #define TM1_MS_REG_BASE 0xc0000250
25 #define TM2_MS_REG_BASE 0xc0000260
26 #define TM3_MS_REG_BASE 0xc0000270
[all …]