Lines Matching +full:0 +full:x12010000
32 #size-cells = <0>;
37 reg = <0xf00>;
50 reg = <0xf01>;
59 reg = <0xf02>;
68 reg = <0xf03>;
81 0 254 20
86 1 4 0
134 reg = <0x110f0000 0x4000>;
135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
180 1 5 0
262 #clock-cells = <0>;
267 reg = <0x100b0000 0x4000>;
270 #size-cells = <0>;
276 pinctrl-0 = <&i2s1_bus>;
282 reg = <0x100c0000 0x4000>;
285 #size-cells = <0>;
295 reg = <0x100d0000 0x1000>;
303 pinctrl-0 = <&spdif_tx>;
309 reg = <0x100e0000 0x4000>;
312 #size-cells = <0>;
315 dmas = <&pdma 0>, <&pdma 1>;
322 reg = <0x100f0000 0x10000>;
328 pinctrl-0 = <&tsp_d0
345 reg = <0x11000000 0x1000>;
356 offset = <0x5c8>;
366 reg = <0x0760 0x0c>;
369 #clock-cells = <0>;
374 #phy-cells = <0>;
384 #phy-cells = <0>;
393 reg = <0x0800 0x0c>;
396 #clock-cells = <0>;
401 #phy-cells = <0>;
408 #phy-cells = <0>;
419 #size-cells = <0>;
441 reg = <0x11010000 0x100>;
447 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
455 reg = <0x11020000 0x100>;
461 pinctrl-0 = <&uart1_xfer>;
469 reg = <0x11030000 0x100>;
475 pinctrl-0 = <&uart21_xfer>;
483 reg = <0x11040000 0x20>;
491 reg = <0x7 0x10>;
494 reg = <0x17 0x1>;
497 reg = <0x19 0x1>;
500 reg = <0x1d 0x1>;
504 reg = <0x1d 0x1>;
511 reg = <0x11050000 0x1000>;
514 #size-cells = <0>;
518 pinctrl-0 = <&i2c0_xfer>;
524 reg = <0x11060000 0x1000>;
527 #size-cells = <0>;
531 pinctrl-0 = <&i2c1_xfer>;
537 reg = <0x11070000 0x1000>;
540 #size-cells = <0>;
544 pinctrl-0 = <&i2c2_xfer>;
550 reg = <0x11080000 0x1000>;
553 #size-cells = <0>;
557 pinctrl-0 = <&i2c3_xfer>;
563 reg = <0x11090000 0x1000>;
566 #size-cells = <0>;
568 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
576 reg = <0x110a0000 0x100>;
584 reg = <0x110b0000 0x10>;
589 pinctrl-0 = <&pwm0_pin>;
595 reg = <0x110b0010 0x10>;
600 pinctrl-0 = <&pwm1_pin>;
606 reg = <0x110b0020 0x10>;
611 pinctrl-0 = <&pwm2_pin>;
617 reg = <0x110b0030 0x10>;
623 pinctrl-0 = <&pwm3_pin>;
629 reg = <0x110c0000 0x20>;
637 reg = <0x110e0000 0x1000>;
661 thermal-sensors = <&tsadc 0>;
664 threshold: trip-point@0 {
712 reg = <0x11150000 0x100>;
721 pinctrl-0 = <&otp_gpio>;
723 #thermal-sensor-cells = <0>;
730 reg = <0x12010000 0x1000>;
739 reg = <0x12030000 0x10000>;
740 #phy-cells = <0>;
743 #clock-cells = <0>;
748 <190000000 0xaa 0x00 0x44 0x44 0x00 0x00 0x00 0x00 0x00
749 0x00 0x00 0x00 0x00 0x00>;
753 gpu: gpu@0x20001000 {
755 reg = <0x20001000 0x200>,
756 <0x20000000 0x100>,
757 <0x20003000 0x100>,
758 <0x20008000 0x1100>,
759 <0x20004000 0x100>,
760 <0x2000A000 0x1100>,
761 <0x20005000 0x100>;
805 1 5 0
833 reg = <0x20020000 0x800>;
850 reg = <0x20020800 0x40>;
856 #iommu-cells = <0>;
862 reg = <0x20030000 0x400>;
895 1 5 0
923 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
929 #iommu-cells = <0>;
935 reg = <0x20050000 0x1ffc>;
947 #size-cells = <0>;
949 vop_out_hdmi: endpoint@0 {
950 reg = <0>;
963 reg = <0x20053f00 0x100>;
968 #iommu-cells = <0>;
974 reg = <0x20060000 0x1000>;
986 reg = <0x20070000 0x800>;
997 reg = <0x20070800 0x40>;
1000 #iommu-cells = <0>;
1011 reg = <0x200a0000 0x20000>;
1019 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
1030 #size-cells = <0>;
1031 hdmi_in_vop: endpoint@0 {
1032 reg = <0>;
1041 reg = <0x20053e00 0x100>,
1042 <0x12020000 0x10000>;
1043 rockchip,saturation = <0x00305b46>;
1044 rockchip,brightcontrast = <0x00009900>;
1045 rockchip,adjtiming = <0xd6c00880>;
1046 rockchip,lumafilter0 = <0x02ff0001>;
1047 rockchip,lumafilter1 = <0xf40200fe>;
1048 rockchip,lumafilter2 = <0xf332d910>;
1049 rockchip,daclevel = <0x15>;
1050 rockchip,dac1level = <0x7>;
1058 #size-cells = <0>;
1059 tve_in_vop: endpoint@0 {
1060 reg = <0>;
1069 reg = <0x30000000 0x4000>;
1074 fifo-depth = <0x100>;
1076 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
1082 reg = <0x30010000 0x4000>;
1087 fifo-depth = <0x100>;
1089 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
1095 reg = <0x30020000 0x4000>;
1105 fifo-depth = <0x100>;
1107 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1113 reg = <0x30030000 0x4000>;
1115 nandc_id = <0>;
1124 reg = <0x30040000 0x40000>;
1140 reg = <0x30080000 0x20000>;
1151 reg = <0x300a0000 0x20000>;
1162 reg = <0x300c0000 0x20000>;
1173 reg = <0x300e0000 0x20000>;
1184 reg = <0x30100000 0x20000>;
1195 reg = <0x30120000 0x20000>;
1206 reg = <0x30200000 0x10000>;
1225 reg = <0x31040000 0x20>;
1230 reg = <0x31070000 0x20>;
1235 reg = <0x31070080 0x20>;
1242 #address-cells = <0>;
1244 reg = <0x32011000 0x1000>,
1245 <0x32012000 0x2000>,
1246 <0x32014000 0x2000>,
1247 <0x32016000 0x2000>;
1260 reg = <0x11110000 0x100>;
1273 reg = <0x11120000 0x100>;
1286 reg = <0x11130000 0x100>;
1299 reg = <0x11140000 0x100>;
1421 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
1425 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1426 <0 RK_PA7 2 &pcfg_pull_none>;
1430 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1436 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1437 <0 RK_PA1 1 &pcfg_pull_none>;
1443 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1444 <0 RK_PA3 1 &pcfg_pull_none>;
1457 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1458 <0 RK_PA7 1 &pcfg_pull_none>;
1501 spi-0 {
1503 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1506 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1509 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1512 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1521 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1539 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1540 <0 RK_PB1 1 &pcfg_pull_none>,
1541 <0 RK_PB3 1 &pcfg_pull_none>,
1542 <0 RK_PB4 1 &pcfg_pull_none>,
1543 <0 RK_PB5 1 &pcfg_pull_none>,
1544 <0 RK_PB6 1 &pcfg_pull_none>,
1567 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1571 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>;
1575 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>;
1615 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1619 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1634 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1679 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1683 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1703 rockchip,virtual-poweroff = <0>;
1705 (0