1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <dt-bindings/clock/hi3519-clock.h> 7*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h> 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun #address-cells = <1>; 10*4882a593Smuzhiyun #size-cells = <1>; 11*4882a593Smuzhiyun chosen { }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpus { 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <0>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpu@0 { 18*4882a593Smuzhiyun device_type = "cpu"; 19*4882a593Smuzhiyun compatible = "arm,cortex-a7"; 20*4882a593Smuzhiyun reg = <0>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun gic: interrupt-controller@10300000 { 25*4882a593Smuzhiyun compatible = "arm,cortex-a7-gic"; 26*4882a593Smuzhiyun #interrupt-cells = <3>; 27*4882a593Smuzhiyun interrupt-controller; 28*4882a593Smuzhiyun reg = <0x10301000 0x1000>, <0x10302000 0x1000>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun clk_3m: clk_3m { 32*4882a593Smuzhiyun compatible = "fixed-clock"; 33*4882a593Smuzhiyun #clock-cells = <0>; 34*4882a593Smuzhiyun clock-frequency = <3000000>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun crg: clock-reset-controller@12010000 { 38*4882a593Smuzhiyun compatible = "hisilicon,hi3519-crg"; 39*4882a593Smuzhiyun #clock-cells = <1>; 40*4882a593Smuzhiyun #reset-cells = <2>; 41*4882a593Smuzhiyun reg = <0x12010000 0x10000>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun soc { 45*4882a593Smuzhiyun #address-cells = <1>; 46*4882a593Smuzhiyun #size-cells = <1>; 47*4882a593Smuzhiyun compatible = "simple-bus"; 48*4882a593Smuzhiyun interrupt-parent = <&gic>; 49*4882a593Smuzhiyun ranges; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun uart0: serial@12100000 { 52*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 53*4882a593Smuzhiyun reg = <0x12100000 0x1000>; 54*4882a593Smuzhiyun interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 55*4882a593Smuzhiyun clocks = <&crg HI3519_UART0_CLK>; 56*4882a593Smuzhiyun clock-names = "apb_pclk"; 57*4882a593Smuzhiyun status = "disable"; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun uart1: serial@12101000 { 61*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 62*4882a593Smuzhiyun reg = <0x12101000 0x1000>; 63*4882a593Smuzhiyun interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 64*4882a593Smuzhiyun clocks = <&crg HI3519_UART1_CLK>; 65*4882a593Smuzhiyun clock-names = "apb_pclk"; 66*4882a593Smuzhiyun status = "disable"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun uart2: serial@12102000 { 70*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 71*4882a593Smuzhiyun reg = <0x12102000 0x1000>; 72*4882a593Smuzhiyun interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 73*4882a593Smuzhiyun clocks = <&crg HI3519_UART2_CLK>; 74*4882a593Smuzhiyun clock-names = "apb_pclk"; 75*4882a593Smuzhiyun status = "disable"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun uart3: serial@12103000 { 79*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 80*4882a593Smuzhiyun reg = <0x12103000 0x1000>; 81*4882a593Smuzhiyun interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 82*4882a593Smuzhiyun clocks = <&crg HI3519_UART3_CLK>; 83*4882a593Smuzhiyun clock-names = "apb_pclk"; 84*4882a593Smuzhiyun status = "disable"; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun uart4: serial@12104000 { 88*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 89*4882a593Smuzhiyun reg = <0x12104000 0x1000>; 90*4882a593Smuzhiyun interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 91*4882a593Smuzhiyun clocks = <&crg HI3519_UART4_CLK>; 92*4882a593Smuzhiyun clock-names = "apb_pclk"; 93*4882a593Smuzhiyun status = "disable"; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun dual_timer0: timer@12000000 { 97*4882a593Smuzhiyun compatible = "arm,sp804", "arm,primecell"; 98*4882a593Smuzhiyun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 99*4882a593Smuzhiyun <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 100*4882a593Smuzhiyun reg = <0x12000000 0x1000>; 101*4882a593Smuzhiyun clocks = <&clk_3m>; 102*4882a593Smuzhiyun clock-names = "apb_pclk"; 103*4882a593Smuzhiyun status = "disable"; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun dual_timer1: timer@12001000 { 107*4882a593Smuzhiyun compatible = "arm,sp804", "arm,primecell"; 108*4882a593Smuzhiyun interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 109*4882a593Smuzhiyun <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 110*4882a593Smuzhiyun reg = <0x12001000 0x1000>; 111*4882a593Smuzhiyun clocks = <&clk_3m>; 112*4882a593Smuzhiyun clock-names = "apb_pclk"; 113*4882a593Smuzhiyun status = "disable"; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun dual_timer2: timer@12002000 { 117*4882a593Smuzhiyun compatible = "arm,sp804", "arm,primecell"; 118*4882a593Smuzhiyun interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 119*4882a593Smuzhiyun <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 120*4882a593Smuzhiyun reg = <0x12002000 0x1000>; 121*4882a593Smuzhiyun clocks = <&clk_3m>; 122*4882a593Smuzhiyun clock-names = "apb_pclk"; 123*4882a593Smuzhiyun status = "disable"; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun spi_bus0: spi@12120000 { 127*4882a593Smuzhiyun compatible = "arm,pl022", "arm,primecell"; 128*4882a593Smuzhiyun reg = <0x12120000 0x1000>; 129*4882a593Smuzhiyun interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 130*4882a593Smuzhiyun clocks = <&crg HI3519_SPI0_CLK>; 131*4882a593Smuzhiyun clock-names = "apb_pclk"; 132*4882a593Smuzhiyun num-cs = <1>; 133*4882a593Smuzhiyun #address-cells = <1>; 134*4882a593Smuzhiyun #size-cells = <0>; 135*4882a593Smuzhiyun status = "disable"; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun spi_bus1: spi@12121000 { 139*4882a593Smuzhiyun compatible = "arm,pl022", "arm,primecell"; 140*4882a593Smuzhiyun reg = <0x12121000 0x1000>; 141*4882a593Smuzhiyun interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 142*4882a593Smuzhiyun clocks = <&crg HI3519_SPI1_CLK>; 143*4882a593Smuzhiyun clock-names = "apb_pclk"; 144*4882a593Smuzhiyun num-cs = <1>; 145*4882a593Smuzhiyun #address-cells = <1>; 146*4882a593Smuzhiyun #size-cells = <0>; 147*4882a593Smuzhiyun status = "disable"; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun spi_bus2: spi@12122000 { 151*4882a593Smuzhiyun compatible = "arm,pl022", "arm,primecell"; 152*4882a593Smuzhiyun reg = <0x12122000 0x1000>; 153*4882a593Smuzhiyun interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 154*4882a593Smuzhiyun clocks = <&crg HI3519_SPI2_CLK>; 155*4882a593Smuzhiyun clock-names = "apb_pclk"; 156*4882a593Smuzhiyun num-cs = <1>; 157*4882a593Smuzhiyun #address-cells = <1>; 158*4882a593Smuzhiyun #size-cells = <0>; 159*4882a593Smuzhiyun status = "disable"; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun sysctrl: system-controller@12020000 { 163*4882a593Smuzhiyun compatible = "hisilicon,hi3519-sysctrl", "syscon"; 164*4882a593Smuzhiyun reg = <0x12020000 0x1000>; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun reboot { 168*4882a593Smuzhiyun compatible = "syscon-reboot"; 169*4882a593Smuzhiyun regmap = <&sysctrl>; 170*4882a593Smuzhiyun offset = <0x4>; 171*4882a593Smuzhiyun mask = <0xdeadbeef>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun}; 175