xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Hisilicon system controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Wei Xu <xuwei5@hisilicon.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription: |
13*4882a593Smuzhiyun  The Hisilicon system controller is used on many Hisilicon boards, it can be
14*4882a593Smuzhiyun  used to assist the slave core startup, reboot the system, etc.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun  There are some variants of the Hisilicon system controller, such as HiP01,
17*4882a593Smuzhiyun  Hi3519, Hi6220 system controller, each of them is mostly compatible with the
18*4882a593Smuzhiyun  Hisilicon system controller, but some same registers located at different
19*4882a593Smuzhiyun  offset. In addition, the HiP01 system controller has some specific control
20*4882a593Smuzhiyun  registers for HIP01 SoC family, such as slave core boot.
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun  The compatible names of each system controller are as follows:
23*4882a593Smuzhiyun  Hisilicon system controller   --> hisilicon,sysctrl
24*4882a593Smuzhiyun  HiP01     system controller   --> hisilicon,hip01-sysctrl
25*4882a593Smuzhiyun  Hi6220    system controller   --> hisilicon,hi6220-sysctrl
26*4882a593Smuzhiyun  Hi3519    system controller   --> hisilicon,hi3519-sysctrl
27*4882a593Smuzhiyun
28*4882a593SmuzhiyunallOf:
29*4882a593Smuzhiyun  - if:
30*4882a593Smuzhiyun      properties:
31*4882a593Smuzhiyun        compatible:
32*4882a593Smuzhiyun          contains:
33*4882a593Smuzhiyun            const: hisilicon,hi6220-sysctrl
34*4882a593Smuzhiyun    then:
35*4882a593Smuzhiyun      required:
36*4882a593Smuzhiyun        - '#clock-cells'
37*4882a593Smuzhiyun
38*4882a593Smuzhiyunproperties:
39*4882a593Smuzhiyun  compatible:
40*4882a593Smuzhiyun    oneOf:
41*4882a593Smuzhiyun      - items:
42*4882a593Smuzhiyun          - enum:
43*4882a593Smuzhiyun              - hisilicon,sysctrl
44*4882a593Smuzhiyun              - hisilicon,hi6220-sysctrl
45*4882a593Smuzhiyun              - hisilicon,hi3519-sysctrl
46*4882a593Smuzhiyun          - const: syscon
47*4882a593Smuzhiyun      - items:
48*4882a593Smuzhiyun          - const: hisilicon,hip01-sysctrl
49*4882a593Smuzhiyun          - const: hisilicon,sysctrl
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun  reg:
52*4882a593Smuzhiyun    maxItems: 1
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun  smp-offset:
55*4882a593Smuzhiyun    description: |
56*4882a593Smuzhiyun      offset in sysctrl for notifying slave cpu booting
57*4882a593Smuzhiyun      cpu 1, reg;
58*4882a593Smuzhiyun      cpu 2, reg + 0x4;
59*4882a593Smuzhiyun      cpu 3, reg + 0x8;
60*4882a593Smuzhiyun      If reg value is not zero, cpun exit wfi and go
61*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun  resume-offset:
64*4882a593Smuzhiyun    description: offset in sysctrl for notifying cpu0 when resume
65*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun  reboot-offset:
68*4882a593Smuzhiyun    description: offset in sysctrl for system reboot
69*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun  '#clock-cells':
72*4882a593Smuzhiyun    const: 1
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun  '#reset-cells':
75*4882a593Smuzhiyun    const: 1
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun  '#address-cells':
78*4882a593Smuzhiyun    const: 1
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun  '#size-cells':
81*4882a593Smuzhiyun    const: 1
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun  ranges: true
84*4882a593Smuzhiyun
85*4882a593Smuzhiyunrequired:
86*4882a593Smuzhiyun  - compatible
87*4882a593Smuzhiyun  - reg
88*4882a593Smuzhiyun
89*4882a593SmuzhiyunadditionalProperties:
90*4882a593Smuzhiyun  type: object
91*4882a593Smuzhiyun
92*4882a593Smuzhiyunexamples:
93*4882a593Smuzhiyun  - |
94*4882a593Smuzhiyun    /* Hisilicon system controller */
95*4882a593Smuzhiyun    system-controller@802000 {
96*4882a593Smuzhiyun        compatible = "hisilicon,sysctrl", "syscon";
97*4882a593Smuzhiyun        #address-cells = <1>;
98*4882a593Smuzhiyun        #size-cells = <1>;
99*4882a593Smuzhiyun        ranges = <0 0x802000 0x1000>;
100*4882a593Smuzhiyun        reg = <0x802000 0x1000>;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun        smp-offset = <0x31c>;
103*4882a593Smuzhiyun        resume-offset = <0x308>;
104*4882a593Smuzhiyun        reboot-offset = <0x4>;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun        clock: clock@0 {
107*4882a593Smuzhiyun            compatible = "hisilicon,hi3620-clock";
108*4882a593Smuzhiyun            reg = <0 0x10000>;
109*4882a593Smuzhiyun            #clock-cells = <1>;
110*4882a593Smuzhiyun        };
111*4882a593Smuzhiyun    };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun    /* HiP01 system controller */
114*4882a593Smuzhiyun    system-controller@10000000 {
115*4882a593Smuzhiyun        compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
116*4882a593Smuzhiyun        reg = <0x10000000 0x1000>;
117*4882a593Smuzhiyun        reboot-offset = <0x4>;
118*4882a593Smuzhiyun    };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun    /* Hi6220 system controller */
121*4882a593Smuzhiyun    system-controller@f7030000 {
122*4882a593Smuzhiyun        compatible = "hisilicon,hi6220-sysctrl", "syscon";
123*4882a593Smuzhiyun        reg = <0xf7030000 0x2000>;
124*4882a593Smuzhiyun        #clock-cells = <1>;
125*4882a593Smuzhiyun    };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun    /* Hi3519 system controller */
128*4882a593Smuzhiyun    system-controller@12010000 {
129*4882a593Smuzhiyun        compatible = "hisilicon,hi3519-sysctrl", "syscon";
130*4882a593Smuzhiyun        reg = <0x12010000 0x1000>;
131*4882a593Smuzhiyun    };
132*4882a593Smuzhiyun...
133