Searched +full:0 +full:x00000bff (Results 1 – 5 of 5) sorted by relevance
15 determine if a logic module is connected at index 0, 1, 2 or 3. The logic35 "^bus(@[0-9a-f]*)?$":37 and are named with bus. The first module is at 0xc0000000, the second38 at 0xd0000000 and so on until the top of the memory of the system at39 0xffffffff. All information about the memory used by the module is55 ranges = <0xc0000000 0xc0000000 0x40000000>;60 ranges = <0x00000000 0xc0000000 0x10000000>;61 /* The Logic Modules sees the Core Module 0 RAM @80000000 */62 dma-ranges = <0x00000000 0x80000000 0x10000000>;68 reg = <0x00100000 0x1000>;[all …]
21 reg = <0xc2000000 0x00100000>;28 syscon@0 {30 reg = <0x00000000 0x1000>;34 #clock-cells = <0>;35 lock-offset = <0x08>;36 vco-offset = <0x00>;43 #clock-cells = <0>;44 lock-offset = <0x08>;45 vco-offset = <0x04>;54 #clock-cells = <0>;[all …]
24 memory@0 {25 reg = <0x00000000 0x20000000>;51 pinctrl-0 = <&state_default>;287 reg = <0x1e>;300 reg = <0x7000c500 0x100>;303 #size-cells = <0>;317 emc-tables@0 {318 nvidia,ram-code = <0x0>;320 #size-cells = <0>;326 nvidia,emc-registers = <0x0000000a 0x00000016[all …]
32 #define QUIRK_ALWAYS_ON BIT(0)88 if (ret < 0) in rockchip_sai_runtime_suspend()110 return 0; in rockchip_sai_runtime_suspend()139 return 0; in rockchip_sai_runtime_resume()173 rockchip_sai_fifo_xrun_detect(sai, stream, 0); in rockchip_sai_dma_ctrl()220 unsigned int val = 0; in rockchip_sai_clear()221 int ret = 0; in rockchip_sai_clear()226 if (ret < 0) { in rockchip_sai_clear()231 return 0; in rockchip_sai_clear()236 return 0; in rockchip_sai_clear()[all …]
26 #define VNMC_REG 0x00 /* Video n Main Control Register */27 #define VNMS_REG 0x04 /* Video n Module Status Register */28 #define VNFC_REG 0x08 /* Video n Frame Capture Register */29 #define VNSLPRC_REG 0x0C /* Video n Start Line Pre-Clip Register */30 #define VNELPRC_REG 0x10 /* Video n End Line Pre-Clip Register */31 #define VNSPPRC_REG 0x14 /* Video n Start Pixel Pre-Clip Register */32 #define VNEPPRC_REG 0x18 /* Video n End Pixel Pre-Clip Register */33 #define VNIS_REG 0x2C /* Video n Image Stride Register */34 #define VNMB_REG(m) (0x30 + ((m) << 2)) /* Video n Memory Base m Register */35 #define VNIE_REG 0x40 /* Video n Interrupt Enable Register */[all …]