1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ALSA SoC Audio Layer - Rockchip SAI Controller driver
4 *
5 * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
6 */
7
8 #include <linux/module.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/delay.h>
11 #include <linux/of_gpio.h>
12 #include <linux/of_device.h>
13 #include <linux/clk.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
17 #include <sound/pcm_params.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/tlv.h>
20
21 #include "rockchip_sai.h"
22
23 #define DRV_NAME "rockchip-sai"
24
25 #define FW_RATIO_MAX 8
26 #define FW_RATIO_MIN 1
27 #define MAXBURST_PER_FIFO 8
28
29 #define DEFAULT_FS 48000
30 #define TIMEOUT_US 1000
31 #define WAIT_TIME_MS_MAX 10000
32 #define QUIRK_ALWAYS_ON BIT(0)
33
34 enum fpw_mode {
35 FPW_ONE_BCLK_WIDTH,
36 FPW_ONE_SLOT_WIDTH,
37 FPW_HALF_FRAME_WIDTH,
38 };
39
40 struct rk_sai_dev {
41 struct device *dev;
42 struct clk *hclk;
43 struct clk *mclk;
44 struct regmap *regmap;
45 struct reset_control *rst_h;
46 struct reset_control *rst_m;
47 struct snd_dmaengine_dai_dma_data capture_dma_data;
48 struct snd_dmaengine_dai_dma_data playback_dma_data;
49 struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
50 unsigned int wait_time[SNDRV_PCM_STREAM_LAST + 1];
51 unsigned int tx_lanes;
52 unsigned int rx_lanes;
53 unsigned int quirks;
54 enum fpw_mode fpw;
55 int fw_ratio;
56 bool has_capture;
57 bool has_playback;
58 bool is_master_mode;
59 bool is_tdm;
60 bool is_clk_auto;
61 };
62
63 static const struct sai_of_quirks {
64 char *quirk;
65 int id;
66 } of_quirks[] = {
67 {
68 .quirk = "rockchip,always-on",
69 .id = QUIRK_ALWAYS_ON,
70 },
71 };
72
rockchip_sai_runtime_suspend(struct device * dev)73 static int rockchip_sai_runtime_suspend(struct device *dev)
74 {
75 struct rk_sai_dev *sai = dev_get_drvdata(dev);
76 unsigned int val;
77 int ret;
78
79 if (sai->is_master_mode)
80 regmap_update_bits(sai->regmap, SAI_XFER,
81 SAI_XFER_CLK_MASK |
82 SAI_XFER_FSS_MASK,
83 SAI_XFER_CLK_DIS |
84 SAI_XFER_FSS_DIS);
85
86 ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val,
87 (val & SAI_XFER_FS_IDLE), 10, TIMEOUT_US);
88 if (ret < 0)
89 dev_warn(sai->dev, "Failed to idle FS\n");
90
91 regcache_cache_only(sai->regmap, true);
92 /*
93 * After FS idle, should wait at least 2 BCLK cycle to make sure
94 * the CLK gate operation done, and then disable mclk.
95 *
96 * Otherwise, the BCLK is still ungated. once the mclk is enabled,
97 * there maybe a risk that a few BCLK cycle leak. especially for
98 * low speed situation, such as 8k samplerate.
99 *
100 * The best way is to use delay per samplerate, but, the max time
101 * is quite a tiny value, so, let's make it simple to use the max
102 * time.
103 *
104 * The max BCLK cycle time is: 31us @ 8K-8Bit (64K BCLK)
105 */
106 udelay(40);
107 clk_disable_unprepare(sai->mclk);
108 clk_disable_unprepare(sai->hclk);
109
110 return 0;
111 }
112
rockchip_sai_runtime_resume(struct device * dev)113 static int rockchip_sai_runtime_resume(struct device *dev)
114 {
115 struct rk_sai_dev *sai = dev_get_drvdata(dev);
116 int ret;
117
118 ret = clk_prepare_enable(sai->hclk);
119 if (ret)
120 goto err_hclk;
121
122 ret = clk_prepare_enable(sai->mclk);
123 if (ret)
124 goto err_mclk;
125
126 regcache_cache_only(sai->regmap, false);
127 regcache_mark_dirty(sai->regmap);
128 ret = regcache_sync(sai->regmap);
129 if (ret)
130 goto err_regmap;
131
132 if (sai->quirks & QUIRK_ALWAYS_ON && sai->is_master_mode)
133 regmap_update_bits(sai->regmap, SAI_XFER,
134 SAI_XFER_CLK_MASK |
135 SAI_XFER_FSS_MASK,
136 SAI_XFER_CLK_EN |
137 SAI_XFER_FSS_EN);
138
139 return 0;
140
141 err_regmap:
142 clk_disable_unprepare(sai->mclk);
143 err_mclk:
144 clk_disable_unprepare(sai->hclk);
145 err_hclk:
146 return ret;
147 }
148
rockchip_sai_fifo_xrun_detect(struct rk_sai_dev * sai,int stream,bool en)149 static void rockchip_sai_fifo_xrun_detect(struct rk_sai_dev *sai,
150 int stream, bool en)
151 {
152 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
153 /* clear irq status which was asserted before TXUIE enabled */
154 regmap_update_bits(sai->regmap, SAI_INTCR,
155 SAI_INTCR_TXUIC, SAI_INTCR_TXUIC);
156 regmap_update_bits(sai->regmap, SAI_INTCR,
157 SAI_INTCR_TXUIE_MASK,
158 SAI_INTCR_TXUIE(en));
159 } else {
160 /* clear irq status which was asserted before RXOIE enabled */
161 regmap_update_bits(sai->regmap, SAI_INTCR,
162 SAI_INTCR_RXOIC, SAI_INTCR_RXOIC);
163 regmap_update_bits(sai->regmap, SAI_INTCR,
164 SAI_INTCR_RXOIE_MASK,
165 SAI_INTCR_RXOIE(en));
166 }
167 }
168
rockchip_sai_dma_ctrl(struct rk_sai_dev * sai,int stream,bool en)169 static void rockchip_sai_dma_ctrl(struct rk_sai_dev *sai,
170 int stream, bool en)
171 {
172 if (!en)
173 rockchip_sai_fifo_xrun_detect(sai, stream, 0);
174
175 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
176 regmap_update_bits(sai->regmap, SAI_DMACR,
177 SAI_DMACR_TDE_MASK,
178 SAI_DMACR_TDE(en));
179 } else {
180 regmap_update_bits(sai->regmap, SAI_DMACR,
181 SAI_DMACR_RDE_MASK,
182 SAI_DMACR_RDE(en));
183 }
184
185 if (en)
186 rockchip_sai_fifo_xrun_detect(sai, stream, 1);
187 }
188
rockchip_sai_reset(struct rk_sai_dev * sai)189 static void rockchip_sai_reset(struct rk_sai_dev *sai)
190 {
191 /*
192 * Suggest to do reset hclk domain and then do mclk
193 * domain, especially for SLAVE mode without CLK in.
194 *
195 * It will be failed for mclk domain reset on SLAVE mode
196 * without CLK in, we workaround this by do hclk reset
197 * to bring controller back to master, and then do
198 * mclk domain reset, at last, recover regmap config.
199 */
200 reset_control_assert(sai->rst_h);
201 /* delay for reset assert done */
202 udelay(10);
203 reset_control_deassert(sai->rst_h);
204 /* delay for reset assert done */
205 udelay(10);
206 reset_control_assert(sai->rst_m);
207 /* delay for reset deassert done */
208 udelay(10);
209 reset_control_deassert(sai->rst_m);
210 /* delay for reset deassert done */
211 udelay(10);
212
213 /* recover regmap config */
214 regcache_mark_dirty(sai->regmap);
215 regcache_sync(sai->regmap);
216 }
217
rockchip_sai_clear(struct rk_sai_dev * sai,unsigned int clr)218 static int rockchip_sai_clear(struct rk_sai_dev *sai, unsigned int clr)
219 {
220 unsigned int val = 0;
221 int ret = 0;
222
223 regmap_update_bits(sai->regmap, SAI_CLR, clr, clr);
224 ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_CLR, val,
225 !(val & clr), 10, TIMEOUT_US);
226 if (ret < 0) {
227 dev_warn(sai->dev, "Failed to clear %u\n", clr);
228 goto reset;
229 }
230
231 return 0;
232
233 reset:
234 rockchip_sai_reset(sai);
235
236 return 0;
237 }
238
rockchip_sai_xfer_start(struct rk_sai_dev * sai,int stream)239 static void rockchip_sai_xfer_start(struct rk_sai_dev *sai, int stream)
240 {
241 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
242 regmap_update_bits(sai->regmap, SAI_XFER,
243 SAI_XFER_TXS_MASK,
244 SAI_XFER_TXS_EN);
245 } else {
246 regmap_update_bits(sai->regmap, SAI_XFER,
247 SAI_XFER_RXS_MASK,
248 SAI_XFER_RXS_EN);
249 }
250 }
251
rockchip_sai_xfer_stop(struct rk_sai_dev * sai,int stream)252 static void rockchip_sai_xfer_stop(struct rk_sai_dev *sai, int stream)
253 {
254 unsigned int msk, val, clr, idle;
255 int ret;
256
257 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
258 msk = SAI_XFER_TXS_MASK;
259 val = SAI_XFER_TXS_DIS;
260 clr = SAI_CLR_TXC;
261 idle = SAI_XFER_TX_IDLE;
262 } else {
263 msk = SAI_XFER_RXS_MASK;
264 val = SAI_XFER_RXS_DIS;
265 clr = SAI_CLR_RXC;
266 idle = SAI_XFER_RX_IDLE;
267 }
268
269 regmap_update_bits(sai->regmap, SAI_XFER, msk, val);
270 ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val,
271 (val & idle), 10, TIMEOUT_US);
272 if (ret < 0)
273 dev_warn(sai->dev, "Failed to idle stream %d\n", stream);
274
275 rockchip_sai_clear(sai, clr);
276 }
277
rockchip_sai_start(struct rk_sai_dev * sai,int stream)278 static void rockchip_sai_start(struct rk_sai_dev *sai, int stream)
279 {
280 rockchip_sai_dma_ctrl(sai, stream, 1);
281 rockchip_sai_xfer_start(sai, stream);
282 }
283
rockchip_sai_stop(struct rk_sai_dev * sai,int stream)284 static void rockchip_sai_stop(struct rk_sai_dev *sai, int stream)
285 {
286 rockchip_sai_dma_ctrl(sai, stream, 0);
287 rockchip_sai_xfer_stop(sai, stream);
288 }
289
rockchip_sai_fmt_create(struct rk_sai_dev * sai,unsigned int fmt)290 static void rockchip_sai_fmt_create(struct rk_sai_dev *sai, unsigned int fmt)
291 {
292 unsigned int xcr_mask = 0, xcr_val = 0, xsft_mask = 0, xsft_val = 0;
293 unsigned int fscr_mask = 0, fscr_val = 0;
294
295 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
296 case SND_SOC_DAIFMT_RIGHT_J:
297 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
298 xcr_val = SAI_XCR_VDJ_R | SAI_XCR_EDGE_SHIFT_0;
299 xsft_mask = SAI_XSHIFT_SEL_MASK;
300 xsft_val = SAI_XSHIFT_SEL(0);
301 fscr_mask = SAI_FSCR_EDGE_MASK;
302 fscr_val = SAI_FSCR_EDGE_DUAL;
303 sai->fpw = FPW_HALF_FRAME_WIDTH;
304 break;
305 case SND_SOC_DAIFMT_LEFT_J:
306 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
307 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0;
308 xsft_mask = SAI_XSHIFT_SEL_MASK;
309 xsft_val = SAI_XSHIFT_SEL(0);
310 fscr_mask = SAI_FSCR_EDGE_MASK;
311 fscr_val = SAI_FSCR_EDGE_DUAL;
312 sai->fpw = FPW_HALF_FRAME_WIDTH;
313 break;
314 case SND_SOC_DAIFMT_I2S:
315 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
316 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_1;
317 xsft_mask = SAI_XSHIFT_SEL_MASK;
318 xsft_val = SAI_XSHIFT_SEL(2);
319 fscr_mask = SAI_FSCR_EDGE_MASK;
320 fscr_val = SAI_FSCR_EDGE_DUAL;
321 sai->fpw = FPW_HALF_FRAME_WIDTH;
322 break;
323 case SND_SOC_DAIFMT_DSP_A:
324 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
325 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0;
326 xsft_mask = SAI_XSHIFT_SEL_MASK;
327 xsft_val = SAI_XSHIFT_SEL(2);
328 fscr_mask = SAI_FSCR_EDGE_MASK;
329 fscr_val = SAI_FSCR_EDGE_RISING;
330 sai->fpw = FPW_ONE_BCLK_WIDTH;
331 break;
332 case SND_SOC_DAIFMT_DSP_B:
333 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK;
334 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0;
335 xsft_mask = SAI_XSHIFT_SEL_MASK;
336 xsft_val = SAI_XSHIFT_SEL(0);
337 fscr_mask = SAI_FSCR_EDGE_MASK;
338 fscr_val = SAI_FSCR_EDGE_RISING;
339 sai->fpw = FPW_ONE_BCLK_WIDTH;
340 break;
341 default:
342 dev_err(sai->dev, "Unsupported fmt %u\n", fmt);
343 break;
344 }
345
346 regmap_update_bits(sai->regmap, SAI_TXCR, xcr_mask, xcr_val);
347 regmap_update_bits(sai->regmap, SAI_RXCR, xcr_mask, xcr_val);
348 regmap_update_bits(sai->regmap, SAI_TX_SHIFT, xsft_mask, xsft_val);
349 regmap_update_bits(sai->regmap, SAI_RX_SHIFT, xsft_mask, xsft_val);
350 regmap_update_bits(sai->regmap, SAI_FSCR, fscr_mask, fscr_val);
351 }
352
rockchip_sai_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)353 static int rockchip_sai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
354 {
355 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
356 unsigned int mask = 0, val = 0;
357 int ret = 0;
358
359 pm_runtime_get_sync(dai->dev);
360 mask = SAI_CKR_MSS_MASK;
361 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
362 case SND_SOC_DAIFMT_CBS_CFS:
363 val = SAI_CKR_MSS_MASTER;
364 sai->is_master_mode = true;
365 break;
366 case SND_SOC_DAIFMT_CBM_CFM:
367 val = SAI_CKR_MSS_SLAVE;
368 sai->is_master_mode = false;
369 break;
370 default:
371 ret = -EINVAL;
372 goto err_pm_put;
373 }
374
375 regmap_update_bits(sai->regmap, SAI_CKR, mask, val);
376
377 mask = SAI_CKR_CKP_MASK | SAI_CKR_FSP_MASK;
378 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
379 case SND_SOC_DAIFMT_NB_NF:
380 val = SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_NORMAL;
381 break;
382 case SND_SOC_DAIFMT_NB_IF:
383 val = SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_INVERTED;
384 break;
385 case SND_SOC_DAIFMT_IB_NF:
386 val = SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_NORMAL;
387 break;
388 case SND_SOC_DAIFMT_IB_IF:
389 val = SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_INVERTED;
390 break;
391 default:
392 ret = -EINVAL;
393 goto err_pm_put;
394 }
395
396 regmap_update_bits(sai->regmap, SAI_CKR, mask, val);
397
398 rockchip_sai_fmt_create(sai, fmt);
399
400 err_pm_put:
401 pm_runtime_put(dai->dev);
402
403 return ret;
404 }
405
rockchip_sai_lanes_auto(struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)406 static unsigned int rockchip_sai_lanes_auto(struct snd_pcm_hw_params *params,
407 struct snd_soc_dai *dai)
408 {
409 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
410 unsigned int lanes = 1;
411
412 if (!sai->is_tdm)
413 lanes = DIV_ROUND_UP(params_channels(params), 2);
414
415 return lanes;
416 }
417
rockchip_sai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)418 static int rockchip_sai_hw_params(struct snd_pcm_substream *substream,
419 struct snd_pcm_hw_params *params,
420 struct snd_soc_dai *dai)
421 {
422 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
423 struct snd_dmaengine_dai_dma_data *dma_data;
424 unsigned int mclk_rate, bclk_rate, div_bclk;
425 unsigned int ch_per_lane, lanes, slot_width;
426 unsigned int val, fscr, reg;
427
428 dma_data = snd_soc_dai_get_dma_data(dai, substream);
429 dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
430
431 lanes = rockchip_sai_lanes_auto(params, dai);
432
433 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
434 reg = SAI_TXCR;
435 if (sai->tx_lanes)
436 lanes = sai->tx_lanes;
437 } else {
438 reg = SAI_RXCR;
439 if (sai->rx_lanes)
440 lanes = sai->rx_lanes;
441 }
442
443 switch (params_format(params)) {
444 case SNDRV_PCM_FORMAT_S8:
445 case SNDRV_PCM_FORMAT_U8:
446 val = SAI_XCR_VDW(8);
447 break;
448 case SNDRV_PCM_FORMAT_S16_LE:
449 val = SAI_XCR_VDW(16);
450 break;
451 case SNDRV_PCM_FORMAT_S24_LE:
452 val = SAI_XCR_VDW(24);
453 break;
454 case SNDRV_PCM_FORMAT_S32_LE:
455 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
456 val = SAI_XCR_VDW(32);
457 break;
458 default:
459 return -EINVAL;
460 }
461
462 val |= SAI_XCR_CSR(lanes);
463
464 regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK | SAI_XCR_CSR_MASK, val);
465
466 regmap_read(sai->regmap, reg, &val);
467
468 slot_width = SAI_XCR_SBW_V(val);
469 ch_per_lane = params_channels(params) / lanes;
470
471 regmap_update_bits(sai->regmap, reg, SAI_XCR_SNB_MASK,
472 SAI_XCR_SNB(ch_per_lane));
473
474 fscr = SAI_FSCR_FW(sai->fw_ratio * slot_width * ch_per_lane);
475
476 switch (sai->fpw) {
477 case FPW_ONE_BCLK_WIDTH:
478 fscr |= SAI_FSCR_FPW(1);
479 break;
480 case FPW_ONE_SLOT_WIDTH:
481 fscr |= SAI_FSCR_FPW(slot_width);
482 break;
483 case FPW_HALF_FRAME_WIDTH:
484 fscr |= SAI_FSCR_FPW(sai->fw_ratio * slot_width * ch_per_lane / 2);
485 break;
486 default:
487 dev_err(sai->dev, "Invalid Frame Pulse Width %d\n", sai->fpw);
488 return -EINVAL;
489 }
490
491 regmap_update_bits(sai->regmap, SAI_FSCR,
492 SAI_FSCR_FW_MASK | SAI_FSCR_FPW_MASK, fscr);
493
494 if (sai->is_master_mode) {
495 bclk_rate = sai->fw_ratio * slot_width * ch_per_lane * params_rate(params);
496 if (sai->is_clk_auto)
497 clk_set_rate(sai->mclk, bclk_rate);
498 mclk_rate = clk_get_rate(sai->mclk);
499 if (mclk_rate < bclk_rate) {
500 dev_err(sai->dev, "Mismatch mclk: %u, expected %u at least\n",
501 mclk_rate, bclk_rate);
502 return -EINVAL;
503 }
504
505 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
506
507 regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
508 SAI_CKR_MDIV(div_bclk));
509 }
510
511 return 0;
512 }
513
rockchip_sai_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)514 static int rockchip_sai_prepare(struct snd_pcm_substream *substream,
515 struct snd_soc_dai *dai)
516 {
517 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
518
519 if (sai->is_master_mode) {
520 /*
521 * Should wait for one BCLK ready after DIV and then ungate
522 * output clk to achieve the clean clk.
523 *
524 * The best way is to use delay per samplerate, but, the max time
525 * is quite a tiny value, so, let's make it simple to use the max
526 * time.
527 *
528 * The max BCLK cycle time is: 15.6us @ 8K-8Bit (64K BCLK)
529 */
530 udelay(20);
531 regmap_update_bits(sai->regmap, SAI_XFER,
532 SAI_XFER_CLK_MASK |
533 SAI_XFER_FSS_MASK,
534 SAI_XFER_CLK_EN |
535 SAI_XFER_FSS_EN);
536 }
537
538 return 0;
539 }
540
rockchip_sai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)541 static int rockchip_sai_trigger(struct snd_pcm_substream *substream,
542 int cmd, struct snd_soc_dai *dai)
543 {
544 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
545 int ret = 0;
546
547 switch (cmd) {
548 case SNDRV_PCM_TRIGGER_START:
549 case SNDRV_PCM_TRIGGER_RESUME:
550 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
551 rockchip_sai_start(sai, substream->stream);
552 break;
553 case SNDRV_PCM_TRIGGER_SUSPEND:
554 case SNDRV_PCM_TRIGGER_STOP:
555 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
556 rockchip_sai_stop(sai, substream->stream);
557 break;
558 default:
559 ret = -EINVAL;
560 break;
561 }
562
563 return ret;
564 }
565
rockchip_sai_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)566 static int rockchip_sai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
567 unsigned int freq, int dir)
568 {
569 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
570 int ret;
571
572 if (!freq || sai->is_clk_auto)
573 return 0;
574
575 ret = clk_set_rate(sai->mclk, freq);
576 if (ret)
577 dev_err(sai->dev, "Failed to set mclk %d\n", ret);
578
579 return ret;
580 }
581
rockchip_sai_dai_probe(struct snd_soc_dai * dai)582 static int rockchip_sai_dai_probe(struct snd_soc_dai *dai)
583 {
584 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
585
586 snd_soc_dai_init_dma_data(dai,
587 sai->has_playback ? &sai->playback_dma_data : NULL,
588 sai->has_capture ? &sai->capture_dma_data : NULL);
589
590 return 0;
591 }
592
rockchip_sai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)593 static int rockchip_sai_startup(struct snd_pcm_substream *substream,
594 struct snd_soc_dai *dai)
595 {
596 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
597 int stream = substream->stream;
598
599 if (sai->substreams[stream])
600 return -EBUSY;
601
602 if (sai->wait_time[stream])
603 substream->wait_time = msecs_to_jiffies(sai->wait_time[stream]);
604
605 sai->substreams[stream] = substream;
606
607 return 0;
608 }
609
rockchip_sai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)610 static void rockchip_sai_shutdown(struct snd_pcm_substream *substream,
611 struct snd_soc_dai *dai)
612 {
613 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
614
615 sai->substreams[substream->stream] = NULL;
616 }
617
rockchip_sai_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)618 static int rockchip_sai_set_tdm_slot(struct snd_soc_dai *dai,
619 unsigned int tx_mask, unsigned int rx_mask,
620 int slots, int slot_width)
621 {
622 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
623
624 pm_runtime_get_sync(dai->dev);
625 regmap_update_bits(sai->regmap, SAI_TXCR, SAI_XCR_SBW_MASK,
626 SAI_XCR_SBW(slot_width));
627 regmap_update_bits(sai->regmap, SAI_RXCR, SAI_XCR_SBW_MASK,
628 SAI_XCR_SBW(slot_width));
629 pm_runtime_put(dai->dev);
630
631 sai->is_tdm = true;
632
633 return 0;
634 }
635
636 static const struct snd_soc_dai_ops rockchip_sai_dai_ops = {
637 .startup = rockchip_sai_startup,
638 .shutdown = rockchip_sai_shutdown,
639 .hw_params = rockchip_sai_hw_params,
640 .set_sysclk = rockchip_sai_set_sysclk,
641 .set_fmt = rockchip_sai_set_fmt,
642 .prepare = rockchip_sai_prepare,
643 .trigger = rockchip_sai_trigger,
644 .set_tdm_slot = rockchip_sai_set_tdm_slot,
645 };
646
647 static struct snd_soc_dai_driver rockchip_sai_dai = {
648 .probe = rockchip_sai_dai_probe,
649 .ops = &rockchip_sai_dai_ops,
650 .symmetric_rates = 1,
651 };
652
rockchip_sai_wr_reg(struct device * dev,unsigned int reg)653 static bool rockchip_sai_wr_reg(struct device *dev, unsigned int reg)
654 {
655 switch (reg) {
656 case SAI_TXCR:
657 case SAI_FSCR:
658 case SAI_RXCR:
659 case SAI_MONO_CR:
660 case SAI_XFER:
661 case SAI_CLR:
662 case SAI_CKR:
663 case SAI_DMACR:
664 case SAI_INTCR:
665 case SAI_TXDR:
666 case SAI_PATH_SEL:
667 case SAI_TX_SLOT_MASK0:
668 case SAI_TX_SLOT_MASK1:
669 case SAI_TX_SLOT_MASK2:
670 case SAI_TX_SLOT_MASK3:
671 case SAI_RX_SLOT_MASK0:
672 case SAI_RX_SLOT_MASK1:
673 case SAI_RX_SLOT_MASK2:
674 case SAI_RX_SLOT_MASK3:
675 case SAI_TX_SHIFT:
676 case SAI_RX_SHIFT:
677 return true;
678 default:
679 return false;
680 }
681 }
682
rockchip_sai_rd_reg(struct device * dev,unsigned int reg)683 static bool rockchip_sai_rd_reg(struct device *dev, unsigned int reg)
684 {
685 switch (reg) {
686 case SAI_TXCR:
687 case SAI_FSCR:
688 case SAI_RXCR:
689 case SAI_MONO_CR:
690 case SAI_XFER:
691 case SAI_CLR:
692 case SAI_CKR:
693 case SAI_TXFIFOLR:
694 case SAI_RXFIFOLR:
695 case SAI_DMACR:
696 case SAI_INTCR:
697 case SAI_INTSR:
698 case SAI_TXDR:
699 case SAI_RXDR:
700 case SAI_PATH_SEL:
701 case SAI_TX_SLOT_MASK0:
702 case SAI_TX_SLOT_MASK1:
703 case SAI_TX_SLOT_MASK2:
704 case SAI_TX_SLOT_MASK3:
705 case SAI_RX_SLOT_MASK0:
706 case SAI_RX_SLOT_MASK1:
707 case SAI_RX_SLOT_MASK2:
708 case SAI_RX_SLOT_MASK3:
709 case SAI_TX_DATA_CNT:
710 case SAI_RX_DATA_CNT:
711 case SAI_TX_SHIFT:
712 case SAI_RX_SHIFT:
713 case SAI_VERSION:
714 return true;
715 default:
716 return false;
717 }
718 }
719
rockchip_sai_volatile_reg(struct device * dev,unsigned int reg)720 static bool rockchip_sai_volatile_reg(struct device *dev, unsigned int reg)
721 {
722 switch (reg) {
723 case SAI_XFER:
724 case SAI_INTCR:
725 case SAI_INTSR:
726 case SAI_CLR:
727 case SAI_TXFIFOLR:
728 case SAI_RXFIFOLR:
729 case SAI_TXDR:
730 case SAI_RXDR:
731 case SAI_TX_DATA_CNT:
732 case SAI_RX_DATA_CNT:
733 return true;
734 default:
735 return false;
736 }
737 }
738
rockchip_sai_precious_reg(struct device * dev,unsigned int reg)739 static bool rockchip_sai_precious_reg(struct device *dev, unsigned int reg)
740 {
741 switch (reg) {
742 case SAI_RXDR:
743 return true;
744 default:
745 return false;
746 }
747 }
748
749 static const struct reg_default rockchip_sai_reg_defaults[] = {
750 { SAI_TXCR, 0x00000bff },
751 { SAI_FSCR, 0x0001f03f },
752 { SAI_RXCR, 0x00000bff },
753 { SAI_PATH_SEL, 0x0000e4e4 },
754 };
755
756 static const struct regmap_config rockchip_sai_regmap_config = {
757 .reg_bits = 32,
758 .reg_stride = 4,
759 .val_bits = 32,
760 .max_register = SAI_VERSION,
761 .reg_defaults = rockchip_sai_reg_defaults,
762 .num_reg_defaults = ARRAY_SIZE(rockchip_sai_reg_defaults),
763 .writeable_reg = rockchip_sai_wr_reg,
764 .readable_reg = rockchip_sai_rd_reg,
765 .volatile_reg = rockchip_sai_volatile_reg,
766 .precious_reg = rockchip_sai_precious_reg,
767 .cache_type = REGCACHE_FLAT,
768 };
769
770 static const struct of_device_id rockchip_sai_match[] __maybe_unused = {
771 { .compatible = "rockchip,sai-v1", },
772 {},
773 };
774
rockchip_sai_init_dai(struct rk_sai_dev * sai,struct resource * res,struct snd_soc_dai_driver ** dp)775 static int rockchip_sai_init_dai(struct rk_sai_dev *sai, struct resource *res,
776 struct snd_soc_dai_driver **dp)
777 {
778 struct device_node *node = sai->dev->of_node;
779 struct snd_soc_dai_driver *dai;
780 struct property *dma_names;
781 const char *dma_name;
782
783 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
784 if (!strcmp(dma_name, "tx"))
785 sai->has_playback = true;
786 if (!strcmp(dma_name, "rx"))
787 sai->has_capture = true;
788 }
789
790 dai = devm_kmemdup(sai->dev, &rockchip_sai_dai,
791 sizeof(*dai), GFP_KERNEL);
792 if (!dai)
793 return -ENOMEM;
794
795 if (sai->has_playback) {
796 dai->playback.stream_name = "Playback";
797 dai->playback.channels_min = 1;
798 dai->playback.channels_max = 128;
799 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
800 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
801 SNDRV_PCM_FMTBIT_S16_LE |
802 SNDRV_PCM_FMTBIT_S24_LE |
803 SNDRV_PCM_FMTBIT_S32_LE |
804 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
805
806 sai->playback_dma_data.addr = res->start + SAI_TXDR;
807 sai->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
808 sai->playback_dma_data.maxburst = MAXBURST_PER_FIFO;
809 }
810
811 if (sai->has_capture) {
812 dai->capture.stream_name = "Capture";
813 dai->capture.channels_min = 1;
814 dai->capture.channels_max = 128;
815 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
816 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
817 SNDRV_PCM_FMTBIT_S16_LE |
818 SNDRV_PCM_FMTBIT_S24_LE |
819 SNDRV_PCM_FMTBIT_S32_LE |
820 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
821
822 sai->capture_dma_data.addr = res->start + SAI_RXDR;
823 sai->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
824 sai->capture_dma_data.maxburst = MAXBURST_PER_FIFO;
825 }
826
827 regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_TDL_MASK,
828 SAI_DMACR_TDL(16));
829 regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_RDL_MASK,
830 SAI_DMACR_RDL(16));
831
832 if (dp)
833 *dp = dai;
834
835 return 0;
836 }
837
838 static const char * const tx_lanes_text[] = { "Auto", "SDOx1", "SDOx2", "SDOx3", "SDOx4" };
839 static const char * const rx_lanes_text[] = { "Auto", "SDIx1", "SDIx2", "SDIx3", "SDIx4" };
840 static const char * const edge_text[] = { "Rising Edge", "Dual Edge" };
841 static const char * const edge_shift_text[] = { "Normal", "Shift 1 Edge" };
842
843 static const char * const fpw_text[] = {
844 "One Bclk Width", "One Slot Width", "Half Frame Width" };
845 static const char * const fw_ratio_text[] = {
846 "1", "2", "3", "4", "5", "6", "7", "8" };
847
848 static const char * const sjm_text[] = { "Right J", "Left J" };
849 static const char * const fbm_text[] = { "MSB", "LSB" };
850 static const char * const vdj_text[] = { "Right J", "Left J" };
851
852 static const char * const sbw_text[] = {
853 "0", "0", "0", "0", "0", "0", "0", "8",
854 "9", "10", "11", "12", "13", "14", "15", "16",
855 "17", "18", "19", "20", "21", "22", "23", "24",
856 "25", "26", "27", "28", "29", "30", "31", "32", };
857
858 static const char * const mono_text[] = { "Disable", "Enable" };
859
860 static DECLARE_TLV_DB_SCALE(rmss_tlv, 0, 128, 0);
861
862 static const char * const mss_text[] = { "Slave", "Master" };
863
864 static const char * const ckp_text[] = { "Normal", "Inverted" };
865
866 static const char * const lpx_text[] = {
867 "From SDO0", "From SDO1", "From SDO2", "From SDO3" };
868
869 static const char * const lps_text[] = { "Disable", "Enable" };
870 static const char * const sync_out_text[] = { "External", "Internal" };
871 static const char * const sync_in_text[] = { "External", "Internal" };
872
873 static const char * const rpaths_text[] = {
874 "From SDI0", "From SDI1", "From SDI2", "From SDI3" };
875
876 static const char * const tpaths_text[] = {
877 "To SDO0", "To SDO1", "To SDO2", "To SDO3" };
878
879 /* TXCR */
880 static SOC_ENUM_SINGLE_DECL(tsft_enum, SAI_TXCR, 22, edge_shift_text);
881 static const struct soc_enum tx_lanes_enum =
882 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_lanes_text), tx_lanes_text);
883 static SOC_ENUM_SINGLE_DECL(tsjm_enum, SAI_TXCR, 19, sjm_text);
884 static SOC_ENUM_SINGLE_DECL(tfbm_enum, SAI_TXCR, 18, fbm_text);
885 static SOC_ENUM_SINGLE_DECL(tvdj_enum, SAI_TXCR, 10, vdj_text);
886 static SOC_ENUM_SINGLE_DECL(tsbw_enum, SAI_TXCR, 5, sbw_text);
887
888 /* FSCR */
889 static SOC_ENUM_SINGLE_DECL(edge_enum, SAI_FSCR, 24, edge_text);
890 static const struct soc_enum fpw_enum =
891 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fpw_text), fpw_text);
892 static const struct soc_enum fw_ratio_enum =
893 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fw_ratio_text), fw_ratio_text);
894
895 /* RXCR */
896 static SOC_ENUM_SINGLE_DECL(rsft_enum, SAI_RXCR, 22, edge_shift_text);
897 static const struct soc_enum rx_lanes_enum =
898 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_lanes_text), rx_lanes_text);
899 static SOC_ENUM_SINGLE_DECL(rsjm_enum, SAI_RXCR, 19, sjm_text);
900 static SOC_ENUM_SINGLE_DECL(rfbm_enum, SAI_RXCR, 18, fbm_text);
901 static SOC_ENUM_SINGLE_DECL(rvdj_enum, SAI_RXCR, 10, vdj_text);
902 static SOC_ENUM_SINGLE_DECL(rsbw_enum, SAI_RXCR, 5, sbw_text);
903
904 /* MONO_CR */
905 static SOC_ENUM_SINGLE_DECL(rmono_switch, SAI_MONO_CR, 1, mono_text);
906 static SOC_ENUM_SINGLE_DECL(tmono_switch, SAI_MONO_CR, 0, mono_text);
907
908 /* CKR */
909 static const struct soc_enum mss_switch =
910 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mss_text), mss_text);
911 static SOC_ENUM_SINGLE_DECL(sp_switch, SAI_CKR, 1, ckp_text);
912 static SOC_ENUM_SINGLE_DECL(fp_switch, SAI_CKR, 0, ckp_text);
913
914 /* PATH_SEL */
915 static SOC_ENUM_SINGLE_DECL(lp3_enum, SAI_PATH_SEL, 28, lpx_text);
916 static SOC_ENUM_SINGLE_DECL(lp2_enum, SAI_PATH_SEL, 26, lpx_text);
917 static SOC_ENUM_SINGLE_DECL(lp1_enum, SAI_PATH_SEL, 24, lpx_text);
918 static SOC_ENUM_SINGLE_DECL(lp0_enum, SAI_PATH_SEL, 22, lpx_text);
919 static SOC_ENUM_SINGLE_DECL(lp3_switch, SAI_PATH_SEL, 21, lps_text);
920 static SOC_ENUM_SINGLE_DECL(lp2_switch, SAI_PATH_SEL, 20, lps_text);
921 static SOC_ENUM_SINGLE_DECL(lp1_switch, SAI_PATH_SEL, 19, lps_text);
922 static SOC_ENUM_SINGLE_DECL(lp0_switch, SAI_PATH_SEL, 18, lps_text);
923 static SOC_ENUM_SINGLE_DECL(sync_out_switch, SAI_PATH_SEL, 17, sync_out_text);
924 static SOC_ENUM_SINGLE_DECL(sync_in_switch, SAI_PATH_SEL, 16, sync_in_text);
925 static SOC_ENUM_SINGLE_DECL(rpath3_enum, SAI_PATH_SEL, 14, rpaths_text);
926 static SOC_ENUM_SINGLE_DECL(rpath2_enum, SAI_PATH_SEL, 12, rpaths_text);
927 static SOC_ENUM_SINGLE_DECL(rpath1_enum, SAI_PATH_SEL, 10, rpaths_text);
928 static SOC_ENUM_SINGLE_DECL(rpath0_enum, SAI_PATH_SEL, 8, rpaths_text);
929 static SOC_ENUM_SINGLE_DECL(tpath3_enum, SAI_PATH_SEL, 6, tpaths_text);
930 static SOC_ENUM_SINGLE_DECL(tpath2_enum, SAI_PATH_SEL, 4, tpaths_text);
931 static SOC_ENUM_SINGLE_DECL(tpath1_enum, SAI_PATH_SEL, 2, tpaths_text);
932 static SOC_ENUM_SINGLE_DECL(tpath0_enum, SAI_PATH_SEL, 0, tpaths_text);
933
rockchip_sai_fpw_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)934 static int rockchip_sai_fpw_get(struct snd_kcontrol *kcontrol,
935 struct snd_ctl_elem_value *ucontrol)
936 {
937 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
938 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
939
940 ucontrol->value.enumerated.item[0] = sai->fpw;
941
942 return 0;
943 }
944
rockchip_sai_fpw_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)945 static int rockchip_sai_fpw_put(struct snd_kcontrol *kcontrol,
946 struct snd_ctl_elem_value *ucontrol)
947 {
948 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
949 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
950 int num;
951
952 num = ucontrol->value.enumerated.item[0];
953 if (num >= ARRAY_SIZE(fpw_text))
954 return -EINVAL;
955
956 sai->fpw = num;
957
958 return 1;
959 }
960
rockchip_sai_fw_ratio_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)961 static int rockchip_sai_fw_ratio_get(struct snd_kcontrol *kcontrol,
962 struct snd_ctl_elem_value *ucontrol)
963 {
964 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
965 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
966
967 ucontrol->value.enumerated.item[0] = sai->fw_ratio - 1;
968
969 return 0;
970 }
971
rockchip_sai_fw_ratio_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)972 static int rockchip_sai_fw_ratio_put(struct snd_kcontrol *kcontrol,
973 struct snd_ctl_elem_value *ucontrol)
974 {
975 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
976 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
977 int ratio = ucontrol->value.enumerated.item[0] + 1;
978
979 if (ratio > FW_RATIO_MAX || ratio < FW_RATIO_MIN)
980 return -EINVAL;
981
982 sai->fw_ratio = ratio;
983
984 return 1;
985 }
986
rockchip_sai_tx_lanes_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)987 static int rockchip_sai_tx_lanes_get(struct snd_kcontrol *kcontrol,
988 struct snd_ctl_elem_value *ucontrol)
989 {
990 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
991 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
992
993 ucontrol->value.enumerated.item[0] = sai->tx_lanes;
994
995 return 0;
996 }
997
rockchip_sai_tx_lanes_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)998 static int rockchip_sai_tx_lanes_put(struct snd_kcontrol *kcontrol,
999 struct snd_ctl_elem_value *ucontrol)
1000 {
1001 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1002 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1003 int num;
1004
1005 num = ucontrol->value.enumerated.item[0];
1006 if (num >= ARRAY_SIZE(tx_lanes_text))
1007 return -EINVAL;
1008
1009 sai->tx_lanes = num;
1010
1011 return 1;
1012 }
1013
rockchip_sai_rx_lanes_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1014 static int rockchip_sai_rx_lanes_get(struct snd_kcontrol *kcontrol,
1015 struct snd_ctl_elem_value *ucontrol)
1016 {
1017 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1018 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1019
1020 ucontrol->value.enumerated.item[0] = sai->rx_lanes;
1021
1022 return 0;
1023 }
1024
rockchip_sai_rx_lanes_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1025 static int rockchip_sai_rx_lanes_put(struct snd_kcontrol *kcontrol,
1026 struct snd_ctl_elem_value *ucontrol)
1027 {
1028 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1029 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1030 int num;
1031
1032 num = ucontrol->value.enumerated.item[0];
1033 if (num >= ARRAY_SIZE(rx_lanes_text))
1034 return -EINVAL;
1035
1036 sai->rx_lanes = num;
1037
1038 return 1;
1039 }
1040
rockchip_sai_mss_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1041 static int rockchip_sai_mss_get(struct snd_kcontrol *kcontrol,
1042 struct snd_ctl_elem_value *ucontrol)
1043 {
1044 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1045 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1046
1047 ucontrol->value.enumerated.item[0] = sai->is_master_mode;
1048
1049 return 0;
1050 }
1051
rockchip_sai_mss_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1052 static int rockchip_sai_mss_put(struct snd_kcontrol *kcontrol,
1053 struct snd_ctl_elem_value *ucontrol)
1054 {
1055 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1056 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1057 bool mss;
1058
1059 /* MUST: do not update mode while stream is running */
1060 if (snd_soc_component_active(component))
1061 return -EPERM;
1062
1063 mss = !!ucontrol->value.enumerated.item[0];
1064 if (mss == sai->is_master_mode)
1065 return 0;
1066
1067 sai->is_master_mode = mss;
1068
1069 pm_runtime_get_sync(sai->dev);
1070 if (sai->is_master_mode) {
1071 /* Switch from Slave to Master */
1072 regmap_update_bits(sai->regmap, SAI_CKR,
1073 SAI_CKR_MSS_MASK,
1074 SAI_CKR_MSS_MASTER);
1075 regmap_update_bits(sai->regmap, SAI_XFER,
1076 SAI_XFER_CLK_MASK |
1077 SAI_XFER_FSS_MASK,
1078 SAI_XFER_CLK_EN |
1079 SAI_XFER_FSS_EN);
1080 } else {
1081 /* Switch from Master to Slave */
1082 regmap_update_bits(sai->regmap, SAI_CKR,
1083 SAI_CKR_MSS_MASK,
1084 SAI_CKR_MSS_SLAVE);
1085 regmap_update_bits(sai->regmap, SAI_XFER,
1086 SAI_XFER_CLK_MASK |
1087 SAI_XFER_FSS_MASK,
1088 SAI_XFER_CLK_DIS |
1089 SAI_XFER_FSS_DIS);
1090 }
1091 pm_runtime_put(sai->dev);
1092
1093 return 1;
1094 }
1095
rockchip_sai_clk_auto_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1096 static int rockchip_sai_clk_auto_get(struct snd_kcontrol *kcontrol,
1097 struct snd_ctl_elem_value *ucontrol)
1098 {
1099 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1100 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1101
1102 ucontrol->value.integer.value[0] = sai->is_clk_auto;
1103
1104 return 0;
1105 }
1106
rockchip_sai_clk_auto_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1107 static int rockchip_sai_clk_auto_put(struct snd_kcontrol *kcontrol,
1108 struct snd_ctl_elem_value *ucontrol)
1109 {
1110 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1111 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1112 bool clk_auto = ucontrol->value.integer.value[0];
1113
1114 if (clk_auto == sai->is_clk_auto)
1115 return 0;
1116
1117 sai->is_clk_auto = clk_auto;
1118
1119 return 1;
1120 }
1121
rockchip_sai_wait_time_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1122 static int rockchip_sai_wait_time_info(struct snd_kcontrol *kcontrol,
1123 struct snd_ctl_elem_info *uinfo)
1124 {
1125 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1126 uinfo->count = 1;
1127 uinfo->value.integer.min = 0;
1128 uinfo->value.integer.max = WAIT_TIME_MS_MAX;
1129 uinfo->value.integer.step = 1;
1130
1131 return 0;
1132 }
1133
rockchip_sai_rd_wait_time_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1134 static int rockchip_sai_rd_wait_time_get(struct snd_kcontrol *kcontrol,
1135 struct snd_ctl_elem_value *ucontrol)
1136 {
1137 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1138 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1139
1140 ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_CAPTURE];
1141
1142 return 0;
1143 }
1144
rockchip_sai_rd_wait_time_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1145 static int rockchip_sai_rd_wait_time_put(struct snd_kcontrol *kcontrol,
1146 struct snd_ctl_elem_value *ucontrol)
1147 {
1148 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1149 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1150
1151 if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
1152 return -EINVAL;
1153
1154 sai->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0];
1155
1156 return 1;
1157 }
1158
rockchip_sai_wr_wait_time_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1159 static int rockchip_sai_wr_wait_time_get(struct snd_kcontrol *kcontrol,
1160 struct snd_ctl_elem_value *ucontrol)
1161 {
1162 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1163 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1164
1165 ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK];
1166
1167 return 0;
1168 }
1169
rockchip_sai_wr_wait_time_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1170 static int rockchip_sai_wr_wait_time_put(struct snd_kcontrol *kcontrol,
1171 struct snd_ctl_elem_value *ucontrol)
1172 {
1173 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1174 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1175
1176 if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
1177 return -EINVAL;
1178
1179 sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0];
1180
1181 return 1;
1182 }
1183
1184 #define SAI_PCM_WAIT_TIME(xname, xhandler_get, xhandler_put) \
1185 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, \
1186 .info = rockchip_sai_wait_time_info, \
1187 .get = xhandler_get, .put = xhandler_put }
1188
1189 static DECLARE_TLV_DB_SCALE(fs_shift_tlv, 0, 8192, 0);
1190
1191 static const struct snd_kcontrol_new rockchip_sai_controls[] = {
1192
1193 SOC_ENUM("Transmit Edge Shift", tsft_enum),
1194 SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
1195 rockchip_sai_tx_lanes_get, rockchip_sai_tx_lanes_put),
1196 SOC_ENUM("Transmit Store Justified Mode", tsjm_enum),
1197 SOC_ENUM("Transmit First Bit Mode", tfbm_enum),
1198 SOC_ENUM("Transmit Valid Data Justified", tvdj_enum),
1199 SOC_ENUM("Transmit Slot Bit Width", tsbw_enum),
1200
1201 SOC_ENUM("Receive Edge Shift", rsft_enum),
1202 SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
1203 rockchip_sai_rx_lanes_get, rockchip_sai_rx_lanes_put),
1204 SOC_ENUM("Receive Store Justified Mode", rsjm_enum),
1205 SOC_ENUM("Receive First Bit Mode", rfbm_enum),
1206 SOC_ENUM("Receive Valid Data Justified", rvdj_enum),
1207 SOC_ENUM("Receive Slot Bit Width", rsbw_enum),
1208
1209 SOC_ENUM("Frame Edge Switch", edge_enum),
1210 SOC_ENUM_EXT("Frame Sync Pulse Width", fpw_enum,
1211 rockchip_sai_fpw_get, rockchip_sai_fpw_put),
1212 SOC_ENUM_EXT("Frame Width Ratio", fw_ratio_enum,
1213 rockchip_sai_fw_ratio_get, rockchip_sai_fw_ratio_put),
1214
1215 SOC_SINGLE_TLV("Receive Mono Slot Select", SAI_MONO_CR,
1216 2, 128, 0, rmss_tlv),
1217 SOC_ENUM("Receive Mono Switch", rmono_switch),
1218 SOC_ENUM("Transmit Mono Switch", tmono_switch),
1219
1220 SOC_ENUM_EXT("Master / Slave Mode Select", mss_switch,
1221 rockchip_sai_mss_get, rockchip_sai_mss_put),
1222 SOC_ENUM("Sclk Polarity", sp_switch),
1223 SOC_ENUM("Frame Sync Polarity", fp_switch),
1224
1225 SOC_ENUM("SDI3 Loopback Src Select", lp3_enum),
1226 SOC_ENUM("SDI2 Loopback Src Select", lp2_enum),
1227 SOC_ENUM("SDI1 Loopback Src Select", lp1_enum),
1228 SOC_ENUM("SDI0 Loopback Src Select", lp0_enum),
1229 SOC_ENUM("SDI3 Loopback Switch", lp3_switch),
1230 SOC_ENUM("SDI2 Loopback Switch", lp2_switch),
1231 SOC_ENUM("SDI1 Loopback Switch", lp1_switch),
1232 SOC_ENUM("SDI0 Loopback Switch", lp0_switch),
1233 SOC_ENUM("Sync Out Switch", sync_out_switch),
1234 SOC_ENUM("Sync In Switch", sync_in_switch),
1235 SOC_ENUM("Receive PATH3 Source Select", rpath3_enum),
1236 SOC_ENUM("Receive PATH2 Source Select", rpath2_enum),
1237 SOC_ENUM("Receive PATH1 Source Select", rpath1_enum),
1238 SOC_ENUM("Receive PATH0 Source Select", rpath0_enum),
1239 SOC_ENUM("Transmit PATH3 Sink Select", tpath3_enum),
1240 SOC_ENUM("Transmit PATH2 Sink Select", tpath2_enum),
1241 SOC_ENUM("Transmit PATH1 Sink Select", tpath1_enum),
1242 SOC_ENUM("Transmit PATH0 Sink Select", tpath0_enum),
1243
1244 SOC_SINGLE_TLV("Transmit Frame Shift Select", SAI_TX_SHIFT,
1245 0, 8192, 0, fs_shift_tlv),
1246 SOC_SINGLE_TLV("Receive Frame Shift Select", SAI_RX_SHIFT,
1247 0, 8192, 0, fs_shift_tlv),
1248
1249 SOC_SINGLE_BOOL_EXT("Clk Auto Switch", 0,
1250 rockchip_sai_clk_auto_get,
1251 rockchip_sai_clk_auto_put),
1252
1253 SAI_PCM_WAIT_TIME("PCM Read Wait Time MS",
1254 rockchip_sai_rd_wait_time_get,
1255 rockchip_sai_rd_wait_time_put),
1256 SAI_PCM_WAIT_TIME("PCM Write Wait Time MS",
1257 rockchip_sai_wr_wait_time_get,
1258 rockchip_sai_wr_wait_time_put),
1259 };
1260
1261 static const struct snd_soc_component_driver rockchip_sai_component = {
1262 .name = DRV_NAME,
1263 .controls = rockchip_sai_controls,
1264 .num_controls = ARRAY_SIZE(rockchip_sai_controls),
1265 };
1266
rockchip_sai_isr(int irq,void * devid)1267 static irqreturn_t rockchip_sai_isr(int irq, void *devid)
1268 {
1269 struct rk_sai_dev *sai = (struct rk_sai_dev *)devid;
1270 struct snd_pcm_substream *substream;
1271 u32 val;
1272
1273 regmap_read(sai->regmap, SAI_INTSR, &val);
1274 if (val & SAI_INTSR_TXUI_ACT) {
1275 dev_warn_ratelimited(sai->dev, "TX FIFO Underrun\n");
1276 regmap_update_bits(sai->regmap, SAI_INTCR,
1277 SAI_INTCR_TXUIC, SAI_INTCR_TXUIC);
1278 substream = sai->substreams[SNDRV_PCM_STREAM_PLAYBACK];
1279 if (substream)
1280 snd_pcm_stop_xrun(substream);
1281 }
1282
1283 if (val & SAI_INTSR_RXOI_ACT) {
1284 dev_warn_ratelimited(sai->dev, "RX FIFO Overrun\n");
1285 regmap_update_bits(sai->regmap, SAI_INTCR,
1286 SAI_INTCR_RXOIC, SAI_INTCR_RXOIC);
1287 substream = sai->substreams[SNDRV_PCM_STREAM_CAPTURE];
1288 if (substream)
1289 snd_pcm_stop_xrun(substream);
1290 }
1291
1292 return IRQ_HANDLED;
1293 }
1294
rockchip_sai_keep_clk_always_on(struct rk_sai_dev * sai)1295 static int rockchip_sai_keep_clk_always_on(struct rk_sai_dev *sai)
1296 {
1297 unsigned int mclk_rate, bclk_rate, div_bclk;
1298
1299 sai->is_master_mode = true;
1300
1301 /* init I2S fmt default */
1302 rockchip_sai_fmt_create(sai, SND_SOC_DAIFMT_I2S);
1303
1304 regmap_update_bits(sai->regmap, SAI_FSCR,
1305 SAI_FSCR_FW_MASK |
1306 SAI_FSCR_FPW_MASK,
1307 SAI_FSCR_FW(64) |
1308 SAI_FSCR_FPW(32));
1309
1310 mclk_rate = clk_get_rate(sai->mclk);
1311 bclk_rate = DEFAULT_FS * 64;
1312 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
1313
1314 regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
1315 SAI_CKR_MDIV(div_bclk));
1316
1317 pm_runtime_forbid(sai->dev);
1318
1319 dev_info(sai->dev, "CLK-ALWAYS-ON: mclk: %d, bclk: %d, fsync: %d\n",
1320 mclk_rate, bclk_rate, DEFAULT_FS);
1321
1322 return 0;
1323 }
1324
rockchip_sai_parse_quirks(struct rk_sai_dev * sai)1325 static int rockchip_sai_parse_quirks(struct rk_sai_dev *sai)
1326 {
1327 int ret = 0, i = 0;
1328
1329 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
1330 if (device_property_read_bool(sai->dev, of_quirks[i].quirk))
1331 sai->quirks |= of_quirks[i].id;
1332
1333 if (sai->quirks & QUIRK_ALWAYS_ON)
1334 ret = rockchip_sai_keep_clk_always_on(sai);
1335
1336 return ret;
1337 }
1338
rockchip_sai_probe(struct platform_device * pdev)1339 static int rockchip_sai_probe(struct platform_device *pdev)
1340 {
1341 struct device_node *node = pdev->dev.of_node;
1342 struct rk_sai_dev *sai;
1343 struct snd_soc_dai_driver *dai;
1344 struct resource *res;
1345 void __iomem *regs;
1346 int ret, irq;
1347
1348 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1349 if (!sai)
1350 return -ENOMEM;
1351
1352 sai->dev = &pdev->dev;
1353 sai->fw_ratio = 1;
1354 /* match to register default */
1355 sai->is_master_mode = true;
1356 dev_set_drvdata(&pdev->dev, sai);
1357
1358 sai->rst_h = devm_reset_control_get_optional_exclusive(&pdev->dev, "h");
1359 if (IS_ERR(sai->rst_h))
1360 return PTR_ERR(sai->rst_h);
1361
1362 sai->rst_m = devm_reset_control_get_optional_exclusive(&pdev->dev, "m");
1363 if (IS_ERR(sai->rst_m))
1364 return PTR_ERR(sai->rst_m);
1365
1366 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1367 if (IS_ERR(regs))
1368 return PTR_ERR(regs);
1369
1370 sai->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1371 &rockchip_sai_regmap_config);
1372 if (IS_ERR(sai->regmap))
1373 return PTR_ERR(sai->regmap);
1374
1375 irq = platform_get_irq_optional(pdev, 0);
1376 if (irq > 0) {
1377 ret = devm_request_irq(&pdev->dev, irq, rockchip_sai_isr,
1378 IRQF_SHARED, node->name, sai);
1379 if (ret) {
1380 dev_err(&pdev->dev, "Failed to request irq %d\n", irq);
1381 return ret;
1382 }
1383 }
1384
1385 sai->mclk = devm_clk_get(&pdev->dev, "mclk");
1386 if (IS_ERR(sai->mclk)) {
1387 dev_err(&pdev->dev, "Failed to get mclk\n");
1388 return PTR_ERR(sai->mclk);
1389 }
1390
1391 sai->hclk = devm_clk_get(&pdev->dev, "hclk");
1392 if (IS_ERR(sai->hclk)) {
1393 dev_err(&pdev->dev, "Failed to get hclk\n");
1394 return PTR_ERR(sai->hclk);
1395 }
1396
1397 ret = rockchip_sai_parse_quirks(sai);
1398 if (ret)
1399 return ret;
1400
1401 pm_runtime_enable(&pdev->dev);
1402 if (!pm_runtime_enabled(&pdev->dev)) {
1403 ret = rockchip_sai_runtime_resume(&pdev->dev);
1404 if (ret)
1405 goto err_runtime_disable;
1406 }
1407
1408 ret = rockchip_sai_init_dai(sai, res, &dai);
1409 if (ret)
1410 goto err_runtime_suspend;
1411
1412 ret = devm_snd_soc_register_component(&pdev->dev,
1413 &rockchip_sai_component,
1414 dai, 1);
1415 if (ret)
1416 goto err_runtime_suspend;
1417
1418 if (device_property_read_bool(&pdev->dev, "rockchip,no-dmaengine")) {
1419 dev_info(&pdev->dev, "Used for Multi-DAI\n");
1420 return 0;
1421 }
1422
1423 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1424 if (ret)
1425 goto err_runtime_suspend;
1426
1427 return 0;
1428
1429 err_runtime_suspend:
1430 if (!pm_runtime_status_suspended(&pdev->dev))
1431 rockchip_sai_runtime_suspend(&pdev->dev);
1432 err_runtime_disable:
1433 pm_runtime_disable(&pdev->dev);
1434
1435 return ret;
1436 }
1437
rockchip_sai_remove(struct platform_device * pdev)1438 static int rockchip_sai_remove(struct platform_device *pdev)
1439 {
1440 pm_runtime_disable(&pdev->dev);
1441 if (!pm_runtime_status_suspended(&pdev->dev))
1442 rockchip_sai_runtime_suspend(&pdev->dev);
1443
1444 return 0;
1445 }
1446
1447 static const struct dev_pm_ops rockchip_sai_pm_ops = {
1448 SET_RUNTIME_PM_OPS(rockchip_sai_runtime_suspend, rockchip_sai_runtime_resume, NULL)
1449 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1450 };
1451
1452 static struct platform_driver rockchip_sai_driver = {
1453 .probe = rockchip_sai_probe,
1454 .remove = rockchip_sai_remove,
1455 .driver = {
1456 .name = DRV_NAME,
1457 .of_match_table = of_match_ptr(rockchip_sai_match),
1458 .pm = &rockchip_sai_pm_ops,
1459 },
1460 };
1461 module_platform_driver(rockchip_sai_driver);
1462
1463 MODULE_DESCRIPTION("Rockchip SAI ASoC Interface");
1464 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1465 MODULE_LICENSE("GPL");
1466 MODULE_ALIAS("platform:" DRV_NAME);
1467 MODULE_DEVICE_TABLE(of, rockchip_sai_match);
1468