1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree for the ARM Integrator/AP platform 4*4882a593Smuzhiyun * with the IM-PD1 example logical module mounted. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "integratorap.dts" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "ARM Integrator/AP with IM-PD1"; 11*4882a593Smuzhiyun compatible = "arm,integrator-ap"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun reserved-memory { 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <1>; 16*4882a593Smuzhiyun ranges; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun impd1_ram: vram@c2000000 { 19*4882a593Smuzhiyun /* 1 MB of designated video RAM on the IM-PD1 */ 20*4882a593Smuzhiyun compatible = "shared-dma-pool"; 21*4882a593Smuzhiyun reg = <0xc2000000 0x00100000>; 22*4882a593Smuzhiyun no-map; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&lm0 { 28*4882a593Smuzhiyun syscon@0 { 29*4882a593Smuzhiyun compatible = "arm,im-pd1-syscon", "syscon"; 30*4882a593Smuzhiyun reg = <0x00000000 0x1000>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun vco1: clock@00 { 33*4882a593Smuzhiyun compatible = "arm,impd1-vco1"; 34*4882a593Smuzhiyun #clock-cells = <0>; 35*4882a593Smuzhiyun lock-offset = <0x08>; 36*4882a593Smuzhiyun vco-offset = <0x00>; 37*4882a593Smuzhiyun clocks = <&sysclk>; 38*4882a593Smuzhiyun clock-output-names = "IM-PD1-VCO1"; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun vco2: clock@04 { 42*4882a593Smuzhiyun compatible = "arm,impd1-vco2"; 43*4882a593Smuzhiyun #clock-cells = <0>; 44*4882a593Smuzhiyun lock-offset = <0x08>; 45*4882a593Smuzhiyun vco-offset = <0x04>; 46*4882a593Smuzhiyun clocks = <&sysclk>; 47*4882a593Smuzhiyun clock-output-names = "IM-PD1-VCO2"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Also used for the Smart Card Interface SCI */ 52*4882a593Smuzhiyun impd1_uartclk: clock@1_4 { 53*4882a593Smuzhiyun compatible = "fixed-factor-clock"; 54*4882a593Smuzhiyun #clock-cells = <0>; 55*4882a593Smuzhiyun clock-div = <4>; 56*4882a593Smuzhiyun clock-mult = <1>; 57*4882a593Smuzhiyun clocks = <&vco2>; 58*4882a593Smuzhiyun clock-output-names = "VCO2_DIV4"; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* For the SSP the clock is divided by 64 */ 62*4882a593Smuzhiyun impd1_sspclk: clock@1_64 { 63*4882a593Smuzhiyun compatible = "fixed-factor-clock"; 64*4882a593Smuzhiyun #clock-cells = <0>; 65*4882a593Smuzhiyun clock-div = <64>; 66*4882a593Smuzhiyun clock-mult = <1>; 67*4882a593Smuzhiyun clocks = <&vco2>; 68*4882a593Smuzhiyun clock-output-names = "VCO2_DIV64"; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Fixed regulator for the MMC */ 72*4882a593Smuzhiyun impd1_3v3: regulator { 73*4882a593Smuzhiyun compatible = "regulator-fixed"; 74*4882a593Smuzhiyun regulator-name = "3V3"; 75*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 76*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 77*4882a593Smuzhiyun regulator-always-on; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Push buttons on the IM-PD1 */ 81*4882a593Smuzhiyun gpio_keys { 82*4882a593Smuzhiyun compatible = "gpio-keys"; 83*4882a593Smuzhiyun #address-cells = <1>; 84*4882a593Smuzhiyun #size-cells = <0>; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun button@0 { 87*4882a593Smuzhiyun debounce-interval = <50>; 88*4882a593Smuzhiyun linux,code = <KEY_UP>; 89*4882a593Smuzhiyun label = "UP"; 90*4882a593Smuzhiyun gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun button@1 { 93*4882a593Smuzhiyun debounce-interval = <50>; 94*4882a593Smuzhiyun linux,code = <KEY_DOWN>; 95*4882a593Smuzhiyun label = "DOWN"; 96*4882a593Smuzhiyun gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun button@2 { 99*4882a593Smuzhiyun debounce-interval = <50>; 100*4882a593Smuzhiyun linux,code = <KEY_LEFT>; 101*4882a593Smuzhiyun label = "LEFT"; 102*4882a593Smuzhiyun gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun button@3 { 105*4882a593Smuzhiyun debounce-interval = <50>; 106*4882a593Smuzhiyun linux,code = <KEY_RIGHT>; 107*4882a593Smuzhiyun label = "UP"; 108*4882a593Smuzhiyun gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun button@4 { 111*4882a593Smuzhiyun debounce-interval = <50>; 112*4882a593Smuzhiyun linux,code = <KEY_ESC>; 113*4882a593Smuzhiyun label = "ESC"; 114*4882a593Smuzhiyun gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun button@5 { 117*4882a593Smuzhiyun debounce-interval = <50>; 118*4882a593Smuzhiyun linux,code = <KEY_ENTER>; 119*4882a593Smuzhiyun label = "ENTER"; 120*4882a593Smuzhiyun gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun bridge { 126*4882a593Smuzhiyun compatible = "ti,ths8134b", "ti,ths8134"; 127*4882a593Smuzhiyun #address-cells = <1>; 128*4882a593Smuzhiyun #size-cells = <0>; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun ports { 131*4882a593Smuzhiyun #address-cells = <1>; 132*4882a593Smuzhiyun #size-cells = <0>; 133*4882a593Smuzhiyun port@0 { 134*4882a593Smuzhiyun reg = <0>; 135*4882a593Smuzhiyun vga_bridge_in: endpoint { 136*4882a593Smuzhiyun remote-endpoint = <&clcd_pads_vga_dac>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun port@1 { 141*4882a593Smuzhiyun reg = <1>; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun vga_bridge_out: endpoint { 144*4882a593Smuzhiyun remote-endpoint = <&vga_con_in>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun vga { 151*4882a593Smuzhiyun compatible = "vga-connector"; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun port { 154*4882a593Smuzhiyun vga_con_in: endpoint { 155*4882a593Smuzhiyun remote-endpoint = <&vga_bridge_out>; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun uart@100000 { 161*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 162*4882a593Smuzhiyun reg = <0x00100000 0x1000>; 163*4882a593Smuzhiyun interrupts-extended = <&impd1_vic 1>; 164*4882a593Smuzhiyun clocks = <&impd1_uartclk>, <&sysclk>; 165*4882a593Smuzhiyun clock-names = "uartclk", "apb_pclk"; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun uart@200000 { 169*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 170*4882a593Smuzhiyun reg = <0x00200000 0x1000>; 171*4882a593Smuzhiyun interrupts-extended = <&impd1_vic 2>; 172*4882a593Smuzhiyun clocks = <&impd1_uartclk>, <&sysclk>; 173*4882a593Smuzhiyun clock-names = "uartclk", "apb_pclk"; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun ssp@300000 { 177*4882a593Smuzhiyun compatible = "arm,pl022", "arm,primecell"; 178*4882a593Smuzhiyun reg = <0x00300000 0x1000>; 179*4882a593Smuzhiyun interrupts-extended = <&impd1_vic 3>; 180*4882a593Smuzhiyun clocks = <&impd1_sspclk>, <&sysclk>; 181*4882a593Smuzhiyun clock-names = "spiclk", "apb_pclk"; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun impd1_gpio0: gpio@400000 { 185*4882a593Smuzhiyun compatible = "arm,pl061", "arm,primecell"; 186*4882a593Smuzhiyun reg = <0x00400000 0x1000>; 187*4882a593Smuzhiyun gpio-controller; 188*4882a593Smuzhiyun #gpio-cells = <2>; 189*4882a593Smuzhiyun interrupt-controller; 190*4882a593Smuzhiyun #interrupt-cells = <2>; 191*4882a593Smuzhiyun interrupts-extended = <&impd1_vic 4>; 192*4882a593Smuzhiyun clocks = <&sysclk>; 193*4882a593Smuzhiyun clock-names = "apb_pclk"; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun impd1_gpio1: gpio@500000 { 197*4882a593Smuzhiyun compatible = "arm,pl061", "arm,primecell"; 198*4882a593Smuzhiyun reg = <0x00500000 0x1000>; 199*4882a593Smuzhiyun gpio-controller; 200*4882a593Smuzhiyun #gpio-cells = <2>; 201*4882a593Smuzhiyun interrupt-controller; 202*4882a593Smuzhiyun #interrupt-cells = <2>; 203*4882a593Smuzhiyun interrupts-extended = <&impd1_vic 5>; 204*4882a593Smuzhiyun clocks = <&sysclk>; 205*4882a593Smuzhiyun clock-names = "apb_pclk"; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun rtc@600000 { 209*4882a593Smuzhiyun compatible = "arm,pl030", "arm,primecell"; 210*4882a593Smuzhiyun reg = <0x00600000 0x1000>; 211*4882a593Smuzhiyun interrupts-extended = <&impd1_vic 6>; 212*4882a593Smuzhiyun clocks = <&sysclk>; 213*4882a593Smuzhiyun clock-names = "apb_pclk"; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun mmc@700000 { 217*4882a593Smuzhiyun compatible = "arm,pl181", "arm,primecell"; 218*4882a593Smuzhiyun reg = <0x00700000 0x1000>; 219*4882a593Smuzhiyun interrupts-extended = <&impd1_vic 7>, 220*4882a593Smuzhiyun <&impd1_vic 8>; 221*4882a593Smuzhiyun clocks = <&sysclk>, <&sysclk>; 222*4882a593Smuzhiyun clock-names = "mclk", "apb_pclk"; 223*4882a593Smuzhiyun bus-width = <1>; 224*4882a593Smuzhiyun max-frequency = <515633>; 225*4882a593Smuzhiyun vmmc-supply = <&impd1_3v3>; 226*4882a593Smuzhiyun wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>; 227*4882a593Smuzhiyun cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun aaci@800000 { 231*4882a593Smuzhiyun compatible = "arm,pl041", "arm,primecell"; 232*4882a593Smuzhiyun reg = <0x00800000 0x1000>; 233*4882a593Smuzhiyun interrupts-extended = <&impd1_vic 9>; 234*4882a593Smuzhiyun clocks = <&sysclk>; 235*4882a593Smuzhiyun clock-names = "apb_pclk"; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun display@1000000 { 239*4882a593Smuzhiyun compatible = "arm,pl110", "arm,primecell"; 240*4882a593Smuzhiyun reg = <0x01000000 0x1000>; 241*4882a593Smuzhiyun interrupts-extended = <&impd1_vic 11>; 242*4882a593Smuzhiyun clocks = <&vco1>, <&sysclk>; 243*4882a593Smuzhiyun clock-names = "clcdclk", "apb_pclk"; 244*4882a593Smuzhiyun /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ 245*4882a593Smuzhiyun max-memory-bandwidth = <40000000>; 246*4882a593Smuzhiyun memory-region = <&impd1_ram>; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun port@0 { 249*4882a593Smuzhiyun #address-cells = <1>; 250*4882a593Smuzhiyun #size-cells = <0>; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun clcd_pads_vga_dac: endpoint@0 { 253*4882a593Smuzhiyun reg = <0>; 254*4882a593Smuzhiyun remote-endpoint = <&vga_bridge_in>; 255*4882a593Smuzhiyun arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun impd1_vic: interrupt-controller@3000000 { 261*4882a593Smuzhiyun compatible = "arm,pl192-vic"; 262*4882a593Smuzhiyun interrupt-controller; 263*4882a593Smuzhiyun #interrupt-cells = <1>; 264*4882a593Smuzhiyun reg = <0x03000000 0x1000>; 265*4882a593Smuzhiyun /* Valid interrupts, 0-9 and 11 */ 266*4882a593Smuzhiyun valid-mask = <0x00000bff>; 267*4882a593Smuzhiyun /* LM site 0 has IRQ 9 on the PIC */ 268*4882a593Smuzhiyun interrupts-extended = <&pic 9>; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun}; 271