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/rk3399_rockchip-uboot/include/andestech/
H A Dandes_pcu.h5 * SPDX-License-Identifier: GPL-2.0+
25 unsigned int rev; /* 0x00 - PCU Revision */
26 unsigned int spinfo; /* 0x04 - Scratch Pad Info */
27 unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */
28 unsigned int soc_id; /* 0x10 - SoC ID */
29 unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */
30 unsigned int soc_apb; /* 0x18 - SoC APB configuration */
32 unsigned int dcsrcr0; /* 0x20 - Driving Capability
34 unsigned int dcsrcr1; /* 0x24 - Driving Capability
36 unsigned int dcsrcr2; /* 0x28 - Driving Capability
[all …]
/rk3399_rockchip-uboot/cmd/
H A Datags.c1 // SPDX-License-Identifier: GPL-2.0+
26 if (atags_bad_magic(t->hdr.magic)) in atags_stat()
29 in_use += (t->hdr.size << 2); in atags_stat()
32 in_available = ATAGS_SIZE - in_use; in atags_stat()
35 printf(" addr = 0x%08x ~ 0x%08x\n", start, end); in atags_stat()
36 printf(" Total size = 0x%08x\n", ATAGS_SIZE); in atags_stat()
37 printf(" in use size = 0x%08x\n", in_use); in atags_stat()
38 printf(" available size = 0x%08x\n", in_available); in atags_stat()
48 switch (t->hdr.magic) { in atags_print_tag()
51 printf(" magic = 0x%x\n", t->hdr.magic); in atags_print_tag()
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx7ulp/
H A Dimx_lpi2c.h6 * SPDX-License-Identifier: GPL-2.0+
80 /* ----------------------------------------------------------------------------
81 -- LPI2C Register Masks
82 ---------------------------------------------------------------------------- */
89 /*! @name VERID - Version ID Register */
92 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATUR… argument
95 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_… argument
98 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_… argument
100 /*! @name PARAM - Parameter Register */
103 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIF… argument
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Dopcodes.h4 * SPDX-License-Identifier: GPL-2.0
25 #define ___asm_opcode_swab32(x) ( \ argument
26 (((x) << 24) & 0xFF000000) \
27 | (((x) << 8) & 0x00FF0000) \
28 | (((x) >> 8) & 0x0000FF00) \
29 | (((x) >> 24) & 0x000000FF) \
31 #define ___asm_opcode_swab16(x) ( \ argument
32 (((x) << 8) & 0xFF00) \
33 | (((x) >> 8) & 0x00FF) \
35 #define ___asm_opcode_swahb32(x) ( \ argument
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap3/
H A Domap3-regs.h4 * SPDX-License-Identifier: GPL-2.0+
15 * GPMC_CONFIG1 - GPMC_CONFIG7
18 /* Values for GPMC_CONFIG1 - signal control parameters */
24 #define CLKACTIVATIONTIME(x) (((x) & 3) << 25) argument
25 #define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) argument
28 #define WAITMONITORINGTIME(x) (((x) & 3) << 18) argument
29 #define WAITPINSELECT(x) (((x) & 3) << 16) argument
30 #define DEVICESIZE(x) (((x) & 3) << 12) argument
33 #define DEVICETYPE(x) (((x) & 3) << 10) argument
38 #define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) argument
[all …]
/rk3399_rockchip-uboot/include/faraday/
H A Dftsdmc021.h3 * Po-Yu Chuang <ratbert@faraday-tech.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 * FTSDMC021 - SDRAM Controller
19 unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */
20 unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */
21 unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */
22 unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */
23 unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */
24 unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */
25 unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */
[all …]
/rk3399_rockchip-uboot/drivers/net/
H A Dmcffec.c2 * (C) Copyright 2000-2004
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * SPDX-License-Identifier: GPL-2.0+
31 #define LAST_PKTBUFSRX PKTBUFSRX - 1
44 -1, /* phy_addr */
54 (struct fec_info_s *)-1,
63 -1, /* phy_addr */
77 (struct fec_info_s *)-1,
91 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | in setFecDuplexSpeed()
93 fecp->tcr = FEC_TCR_FDEN; in setFecDuplexSpeed()
[all …]
/rk3399_rockchip-uboot/drivers/video/rk_eink/
H A Drk_ebc_tcon.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wenping Zhang <wenping.zhang@rock-chips.com>
20 #include <irq-generic.h>
34 #define HIWORD_UPDATE(x, l, h) (((x) << (l)) | (GENMASK(h, l) << 16)) argument
35 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) argument
43 #define EBC_DSP_HTIMING0 0x000c //H-Timing setting register0
44 #define EBC_DSP_HTIMING1 0x0010 //H-Timing setting register1
45 #define EBC_DSP_VTIMING0 0x0014 //V-Timing setting register0
46 #define EBC_DSP_VTIMING1 0x0018 //V-Timing setting register1
65 #define DSP_HTOTAL(x) UPDATE(x, 27, 16) argument
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xx/
H A Dreginfo.c5 * SPDX-License-Identifier: GPL-2.0+
16 memctl8xx_t __iomem *memctl = &immap->im_memctl; in print_reginfo()
17 sysconf8xx_t __iomem *sysconf = &immap->im_siu_conf; in print_reginfo()
18 sit8xx_t __iomem *timers = &immap->im_sit; in print_reginfo()
25 "\tIMMR\t0x%08X\n", get_immr(0)); in print_reginfo()
27 printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr)); in print_reginfo()
28 printf("\tSYPCR\t0x%08X\n", in_be32(&sysconf->sc_sypcr)); in print_reginfo()
30 printf("\tSWT\t0x%08X", in_be32(&sysconf->sc_swt)); in print_reginfo()
31 printf("\tSWSR\t0x%04X\n", in_be16(&sysconf->sc_swsr)); in print_reginfo()
33 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n", in print_reginfo()
[all …]
/rk3399_rockchip-uboot/include/linux/byteorder/
H A Dswab.h6 * Byte-swapping, independently from CPU endianness
9 * Francois-Rene Rideau <fare@tunes.org> 19971205
11 * to clean up support for bizarre-endian architectures.
13 * See asm-i386/byteorder.h and suches for examples of how to provide
14 * architecture-dependent optimized versions
21 #define ___swab16(x) \ argument
23 (((__u16)(x) & (__u16)0x00ffU) << 8) | \
24 (((__u16)(x) & (__u16)0xff00U) >> 8) ))
25 #define ___swab32(x) \ argument
27 (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
[all …]
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <asm-generic/gpio.h>
15 #include <dm/uclass-id.h>
24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) argument
30 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26) argument
32 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25) argument
34 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22) argument
36 #define SW_EDID_MODE(x) UPDATE(x, 21, 21) argument
38 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10) argument
42 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8) argument
[all …]
H A Drk628_hdmirx.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Author: Guochun Huang <hero.huang@rock-chips.com>
13 #define HDMIRX_REG(x) ((x) + 0x30000) argument
15 /* --------- EDID and HDCP KEY ------- */
22 #define HOT_PLUG_DETECT(x) UPDATE(x, 0, 0) argument
37 #define SEL_PIXCLKSRC(x) UPDATE(x, 19, 18) argument
50 #define PREAMBLE_CNT_LIMIT(x) UPDATE(x, 31, 27) argument
52 #define OESSCTL3_THR(x) UPDATE(x, 20, 19) argument
54 #define SPIKE_FILTER_EN(x) UPDATE(x, 18, 18) argument
56 #define DVI_MODE_HYST(x) UPDATE(x, 17, 13) argument
[all …]
/rk3399_rockchip-uboot/drivers/ufs/
H A Dufs-rockchip-usbplug.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <dm/device-internal.h>
18 #include <asm/dma-mapping.h>
22 #include "ufs-rockchip-usbplug.h"
36 printf("---------------------------\n"); in ufs_info_show_dev_desc()
37 printf("---UFS Device Descriptor---\n"); in ufs_info_show_dev_desc()
38 printf("---------------------------\n"); in ufs_info_show_dev_desc()
39 printf("bLength: 0x%x\n", dev->b_length); in ufs_info_show_dev_desc()
40 printf("bDescriptorIDN: 0x%x\n", dev->b_descriptor_idn); in ufs_info_show_dev_desc()
41 printf("bDevice: 0x%x\n", dev->b_device); in ufs_info_show_dev_desc()
[all …]
/rk3399_rockchip-uboot/include/
H A Dfsl_dspi.h4 * Copyright (C) 2004-2007, 2015 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * SPDX-License-Identifier: GPL-2.0+
20 u32 ctar[8]; /* 0x0C - 0x28 */
23 u32 tfr; /* 0x34 - PUSHR */
24 u32 rfr; /* 0x38 - POPR */
38 #define DSPI_MCR_DCONF(x) (((x) & 0x03) << 28) argument
43 #define DSPI_MCR_PCSIS(x) (1 << (16 + (x))) argument
59 #define DSPI_MCR_SMPL_PT(x) (((x) & 0x03) << 8) argument
65 #define DSPI_TCR_SPI_TCNT(x) (((x) & 0x0000FFFF) << 16) argument
[all …]
H A Dflash.h2 * (C) Copyright 2000-2005
5 * SPDX-License-Identifier: GPL-2.0+
15 /*-----------------------------------------------------------------------
46 const char *name; /* human-readable name */
51 #ifdef CONFIG_CFI_FLASH /* DM-specific parts */
121 /*-----------------------------------------------------------------------
135 /*-----------------------------------------------------------------------
141 /*-----------------------------------------------------------------------
146 /*-----------------------------------------------------------------------
154 #define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/
H A Dpsc_defs.h2 * (C) Copyright 2012-2014
5 * SPDX-License-Identifier: GPL-2.0+
24 #define PSC_REG_PDSTAT(x) (0x200 + (4 * (x))) argument
25 #define PSC_REG_PDCTL(x) (0x300 + (4 * (x))) argument
26 #define PSC_REG_MDCFG(x) (0x600 + (4 * (x))) argument
27 #define PSC_REG_MDSTAT(x) (0x800 + (4 * (x))) argument
28 #define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) argument
31 static inline u32 _boot_bit_mask(u32 x, u32 y) in _boot_bit_mask() argument
33 u32 val = (1 << (x - y + 1)) - 1; in _boot_bit_mask()
37 static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y) in boot_read_bitfield() argument
[all …]
/rk3399_rockchip-uboot/arch/mips/include/asm/mach-generic/
H A Dmangle-port.h4 * SPDX-License-Identifier: GPL-2.0
21 * variations of functions: non-prefixed ones that preserve the value
28 # define ioswabb(a, x) (x) argument
29 # define __mem_ioswabb(a, x) (x) argument
30 # define ioswabw(a, x) le16_to_cpu(x) argument
31 # define __mem_ioswabw(a, x) (x) argument
32 # define ioswabl(a, x) le32_to_cpu(x) argument
33 # define __mem_ioswabl(a, x) (x) argument
34 # define ioswabq(a, x) le64_to_cpu(x) argument
35 # define __mem_ioswabq(a, x) (x) argument
[all …]
/rk3399_rockchip-uboot/drivers/video/drm/
H A Drockchip_lvds.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/media-bus-format.h>
29 #define PX30_LVDS_SELECT(x) HIWORD_UPDATE(x, 14, 13) argument
30 #define PX30_LVDS_MODE_EN(x) HIWORD_UPDATE(x, 12, 12) argument
31 #define PX30_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 11, 11) argument
32 #define PX30_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 6, 6) argument
33 #define PX30_LVDS_VOP_SEL(x) HIWORD_UPDATE(x, 1, 1) argument
36 #define RK3126_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 9, 9) argument
37 #define RK3126_LVDS_MODE_EN(x) HIWORD_UPDATE(x, 6, 6) argument
[all …]
/rk3399_rockchip-uboot/board/armadeus/apf27/
H A Dapf27.h2 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
4 * SPDX-License-Identifier: GPL-2.0+
67 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
91 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
92 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
104 #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
137 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
138 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
150 #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
183 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
[all …]
/rk3399_rockchip-uboot/include/linux/
H A Dkernel.h9 #define SHRT_MIN ((s16)(-SHRT_MAX - 1))
11 #define INT_MIN (-INT_MAX - 1)
14 #define LONG_MIN (-LONG_MAX - 1)
17 #define LLONG_MIN (-LLONG_MAX - 1)
25 #define S8_MIN ((s8)(-S8_MAX - 1))
28 #define S16_MIN ((s16)(-S16_MAX - 1))
31 #define S32_MIN ((s32)(-S32_MAX - 1))
34 #define S64_MIN ((s64)(-S64_MAX - 1))
38 #define REPEAT_BYTE(x) ((~0ul / 0xff) * (x)) argument
40 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) argument
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-at91/include/mach/
H A Dsama5d3_smc.h4 * Static Memory Controllers (SMC) - System peripherals registers.
7 * SPDX-License-Identifier: GPL-2.0+
34 #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) argument
35 #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) argument
36 #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) argument
37 #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) argument
39 #define AT91_SMC_PULSE_NWE(x) (x & 0x3f) argument
40 #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x3f) << 8) argument
41 #define AT91_SMC_PULSE_NRD(x) ((x & 0x3f) << 16) argument
42 #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x3f) << 24) argument
[all …]
/rk3399_rockchip-uboot/arch/m68k/include/asm/
H A Dm520x.h2 * m520x.h -- Definitions for Freescale Coldfire 520x
4 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
14 #define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) argument
15 #define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) argument
16 #define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) argument
21 #define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) argument
22 #define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) argument
23 #define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) argument
[all …]
/rk3399_rockchip-uboot/include/synopsys/
H A Ddwcddr21mctl.h5 * SPDX-License-Identifier: GPL-2.0+
9 * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
48 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) argument
49 #define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) argument
50 #define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) argument
51 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) argument
52 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) argument
53 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) argument
54 #define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) argument
55 #define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) argument
[all …]
/rk3399_rockchip-uboot/board/freescale/c29xpcie/
H A Dcpld.c6 * SPDX-License-Identifier: GPL-2.0+
8 * This file provides support for the board-specific CPLD used on some Freescale
13 * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
31 reg11 = in_8(&cpld_data->flhcsr); in cpld_set_altbank()
35 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) in cpld_set_altbank()
39 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) in cpld_set_altbank()
43 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) in cpld_set_altbank()
47 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) in cpld_set_altbank()
51 printf("Invalid value! [1-4]\n"); in cpld_set_altbank()
72 printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1)); in cpld_dump_regs()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/include/mach/
H A Dsromc.h5 * SPDX-License-Identifier: GPL-2.0+
16 #define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) argument
17 #define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ argument
18 /* 1-> Byte base address*/
19 #define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) argument
20 #define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) argument
22 #define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ argument
23 #define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ argument
24 #define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ argument
25 #define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ argument
[all …]

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