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/rk3399_rockchip-uboot/cmd/
H A Dbdinfo.c5 * SPDX-License-Identifier: GPL-2.0+
20 printf("%-12s= 0x%08lX\n", name, value); in print_num()
34 printf("%-12s= %s\n", name, val); in print_eth()
47 printf("eth%dname = %s\n", i, dev->name); in print_eths()
61 printf("%-12s= 0x%.8llX\n", name, value); in print_lnum()
69 printf("%-12s= %6s MHz\n", name, strmhz(buf, hz)); in print_mhz()
73 static inline void print_bi_boot_params(const bd_t *bd) in print_bi_boot_params() argument
75 print_num("boot_params", (ulong)bd->bi_boot_params); in print_bi_boot_params()
78 static inline void print_bi_mem(const bd_t *bd) in print_bi_mem() argument
81 print_num("mem start ", (ulong)bd->bi_memstart); in print_bi_mem()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/
H A Dinit.h2 * Copyright (C) 2015-2016 Socionext Inc.
5 * SPDX-License-Identifier: GPL-2.0+
31 int uniphier_ld4_init(const struct uniphier_board_data *bd);
32 int uniphier_pro4_init(const struct uniphier_board_data *bd);
33 int uniphier_sld8_init(const struct uniphier_board_data *bd);
34 int uniphier_pro5_init(const struct uniphier_board_data *bd);
35 int uniphier_pxs2_init(const struct uniphier_board_data *bd);
65 void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
67 int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd);
68 int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd);
[all …]
H A Dmemconf.c2 * Copyright (C) 2011-2015 Panasonic Corporation
6 * SPDX-License-Identifier: GPL-2.0+
14 #include "sg-regs.h"
17 static int __uniphier_memconf_init(const struct uniphier_board_data *bd, in __uniphier_memconf_init() argument
24 switch (bd->dram_ch[0].width) { in __uniphier_memconf_init()
27 size_per_word = bd->dram_ch[0].size; in __uniphier_memconf_init()
31 size_per_word = bd->dram_ch[0].size >> 1; in __uniphier_memconf_init()
35 return -EINVAL; in __uniphier_memconf_init()
56 return -EINVAL; in __uniphier_memconf_init()
60 switch (bd->dram_ch[1].width) { in __uniphier_memconf_init()
[all …]
H A Dspl_board_init.c2 * Copyright (C) 2015-2016 Socionext Inc.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include "micro-support-card.h"
14 #include "soc-info.h"
18 void (*bcu_init)(const struct uniphier_board_data *bd);
20 int (*dpll_init)(const struct uniphier_board_data *bd);
21 int (*memconf_init)(const struct uniphier_board_data *bd);
23 int (*umc_init)(const struct uniphier_board_data *bd);
94 const struct uniphier_board_data *bd; in UNIPHIER_DEFINE_SOCDATA_FUNC() local
102 bd = uniphier_get_board_param(); in UNIPHIER_DEFINE_SOCDATA_FUNC()
[all …]
/rk3399_rockchip-uboot/arch/nds32/lib/
H A Dbootm.c6 * SPDX-License-Identifier: GPL-2.0+
12 #include <u-boot/zlib.h>
24 static void setup_start_tag(bd_t *bd);
27 static void setup_memory_tags(bd_t *bd);
29 static void setup_commandline_tag(bd_t *bd, char *commandline);
32 static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
34 static void setup_end_tag(bd_t *bd);
41 bd_t *bd = gd->bd; in do_bootm_linux() local
43 int machid = bd->bi_arch_number; in do_bootm_linux()
59 theKernel = (void (*)(int, int, uint))images->ep; in do_bootm_linux()
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/rk3399_rockchip-uboot/drivers/net/
H A Dethoc.c4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 * Thierry Reding <thierry.reding@avionic-design.de>
10 * SPDX-License-Identifier: GPL-2.0
55 #define MODER_NBO (1 << 8) /* no back-off */
169 * struct ethoc - driver-private device structure
193 * struct ethoc_bd - buffer descriptor
204 return priv->iobase + offset; in ethoc_reg()
218 struct ethoc_bd *bd) in ethoc_read_bd() argument
221 bd->stat = ethoc_read(priv, offset + 0); in ethoc_read_bd()
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H A Dfec_mxc.h14 * SPDX-License-Identifier: GPL-2.0+
24 /* Control and status Registers (offset 000-1FF) */
32 uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
35 uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
38 uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */
41 uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */
43 uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */
45 uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */
50 uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */
55 uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dcpu.c3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
22 #include <fsl-mc/fsl_mc.h>
41 svr = gur_in32(&gur->svr); in cpu_name()
64 * levels of translation tables here to cover 40-bit address space.
75 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; in early_mmu_setup()
76 gd->arch.tlb_fillptr = gd->arch.tlb_addr; in early_mmu_setup()
77 gd->arch.tlb_size = EARLY_PGTABLE_SIZE; in early_mmu_setup()
83 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, in early_mmu_setup()
98 svr = gur_in32(&gur->svr); in fix_pcie_mmu_map()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/
H A Dfdt.c4 * SPDX-License-Identifier: GPL-2.0
17 void ft_cpu_setup(void *blob, bd_t *bd) in ft_cpu_setup() argument
25 "timebase-frequency", bd->bi_busfreq / 4, 1); in ft_cpu_setup()
27 "bus-frequency", bd->bi_busfreq, 1); in ft_cpu_setup()
29 "clock-frequency", bd->bi_intfreq, 1); in ft_cpu_setup()
31 "bus-frequency", bd->bi_busfreq, 1); in ft_cpu_setup()
33 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); in ft_cpu_setup()
37 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); in ft_cpu_setup()
/rk3399_rockchip-uboot/api/
H A Dapi_platform-powerpc.c6 * SPDX-License-Identifier: GPL-2.0+
8 * This file contains routines that fetch data from PowerPC-dependent sources
16 #include <asm/u-boot.h>
25 * include/asm-ppc/u-boot.h and include/asm-ppc/global_data.h, so any changes
30 si->clk_bus = gd->bus_clk; in platform_sys_info()
31 si->clk_cpu = gd->cpu_clk; in platform_sys_info()
40 si->bar = gd->bd->bi_bar; in platform_sys_info()
43 si->bar = 0; in platform_sys_info()
46 platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM); in platform_sys_info()
47 platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH); in platform_sys_info()
[all …]
/rk3399_rockchip-uboot/board/freescale/ls2080a/
H A Dls2080a.c4 * SPDX-License-Identifier: GPL-2.0+
15 #include <fsl-mc/fsl_mc.h>
26 gd->env_addr = (ulong)&default_environment[0]; in board_init()
41 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); in detail_board_ddr_info()
44 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { in detail_board_ddr_info()
45 puts("\nDP-DDR "); in detail_board_ddr_info()
46 print_size(gd->bd->bi_dram[2].size, ""); in detail_board_ddr_info()
78 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); in fdt_fixup_board_enet()
82 * with old DT node (/fsl-mc) is no longer needed. in fdt_fixup_board_enet()
85 offset = fdt_path_offset(fdt, "/fsl-mc"); in fdt_fixup_board_enet()
[all …]
/rk3399_rockchip-uboot/board/AndesTech/adp-ae3xx/
H A Dadp-ae3xx.c6 * SPDX-License-Identifier: GPL-2.0+
29 gd->bd->bi_arch_number = MACH_TYPE_ADPAE3XX; in board_init()
30 gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; in board_init()
40 gd->ram_size = actual_size; in dram_init()
51 gd->bd->bi_dram[0].start = PHYS_SDRAM_0; in dram_init_banksize()
52 gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; in dram_init_banksize()
53 gd->bd->bi_dram[1].start = PHYS_SDRAM_1; in dram_init_banksize()
54 gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE; in dram_init_banksize()
60 int board_eth_init(bd_t *bd) in board_eth_init() argument
62 return ftmac100_initialize(bd); in board_eth_init()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xx/
H A Dfdt.c6 * SPDX-License-Identifier: GPL-2.0+
15 void ft_cpu_setup(void *blob, bd_t *bd) in ft_cpu_setup() argument
18 "timebase-frequency", get_tbclk(), 1); in ft_cpu_setup()
20 "bus-frequency", bd->bi_busfreq, 1); in ft_cpu_setup()
22 "clock-frequency", bd->bi_intfreq, 1); in ft_cpu_setup()
23 do_fixup_by_compat_u32(blob, "fsl,pq1-soc", "clock-frequency", in ft_cpu_setup()
24 bd->bi_intfreq, 1); in ft_cpu_setup()
25 do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", in ft_cpu_setup()
26 gd->arch.brg_clk, 1); in ft_cpu_setup()
28 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); in ft_cpu_setup()
/rk3399_rockchip-uboot/board/synopsys/axs10x/
H A Dnand.c2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
27 #define B_WFR (1 << 19) /* 1b - Wait for ready */
28 #define B_LC (1 << 18) /* 1b - Last cycle */
29 #define B_IWC (1 << 13) /* 1b - Interrupt when complete */
73 static struct nand_bd *bd; /* DMA buffer descriptors */ variable
76 * axs101_nand_write_buf - write buffer to chip
97 * axs101_nand_write_buf - write buffer to chip
110 writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status); in axs101_nand_write_buf()
111 writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes); in axs101_nand_write_buf()
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/rk3399_rockchip-uboot/board/AndesTech/adp-ag101p/
H A Dadp-ag101p.c6 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/mach-types.h>
33 gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P; in board_init()
34 gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; in board_init()
47 gd->ram_size = actual_size; in dram_init()
59 gd->bd->bi_dram[0].start = PHYS_SDRAM_0; in dram_init_banksize()
60 gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; in dram_init_banksize()
61 gd->bd->bi_dram[1].start = PHYS_SDRAM_1; in dram_init_banksize()
62 gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE; in dram_init_banksize()
68 int board_eth_init(bd_t *bd) in board_eth_init() argument
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/rk3399_rockchip-uboot/arch/arm/mach-omap2/am33xx/
H A Dfdt.c4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch-am33xx/sys_proto.h>
17 static void ft_hs_fixups(void *fdt, bd_t *bd) in ft_hs_fixups() argument
21 if ((ft_hs_disable_rng(fdt, bd) == 0) && in ft_hs_fixups()
22 (ft_hs_fixup_dram(fdt, bd) == 0) && in ft_hs_fixups()
23 (ft_hs_add_tee(fdt, bd) == 0)) in ft_hs_fixups()
32 static void ft_hs_fixups(void *fdt, bd_t *bd) { } in ft_hs_fixups() argument
40 void ft_cpu_setup(void *fdt, bd_t *bd) in ft_cpu_setup() argument
42 ft_hs_fixups(fdt, bd); in ft_cpu_setup()
/rk3399_rockchip-uboot/board/freescale/t4rdb/
H A Dspl.c6 * SPDX-License-Identifier: GPL-2.0+
59 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; in board_init_f()
72 bd_t *bd; in board_init_r() local
74 bd = (bd_t *)(gd + sizeof(gd_t)); in board_init_r()
75 memset(bd, 0, sizeof(bd_t)); in board_init_r()
76 gd->bd = bd; in board_init_r()
77 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; in board_init_r()
78 bd->bi_memsize = CONFIG_SYS_L3_SIZE; in board_init_r()
84 gd->flags |= GD_FLG_FULL_MALLOC_INIT; in board_init_r()
86 mmc_initialize(bd); in board_init_r()
[all …]
/rk3399_rockchip-uboot/board/freescale/c29xpcie/
H A Dspl.c3 * SPDX-License-Identifier: GPL-2.0+
30 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; in board_init_f()
32 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; in board_init_f()
35 gd->bus_clk / 16 / CONFIG_BAUDRATE); in board_init_f()
37 /* copy code to RAM and jump to it - this should not return */ in board_init_f()
38 /* NOTE - code has to be copied out of NAND buffer before in board_init_f()
48 bd_t *bd; in board_init_r() local
51 bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); in board_init_r()
52 memset(bd, 0, sizeof(bd_t)); in board_init_r()
53 gd->bd = bd; in board_init_r()
[all …]
/rk3399_rockchip-uboot/board/freescale/t208xrdb/
H A Dspl.c3 * SPDX-License-Identifier: GPL-2.0+
50 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; in board_init_f()
69 bd_t *bd; in board_init_r() local
71 bd = (bd_t *)(gd + sizeof(gd_t)); in board_init_r()
72 memset(bd, 0, sizeof(bd_t)); in board_init_r()
73 gd->bd = bd; in board_init_r()
74 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; in board_init_r()
75 bd->bi_memsize = CONFIG_SYS_L3_SIZE; in board_init_r()
81 gd->flags |= GD_FLG_FULL_MALLOC_INIT; in board_init_r()
88 mmc_initialize(bd); in board_init_r()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Dfdt.c7 * SPDX-License-Identifier: GPL-2.0+
28 data[1] = QE_MURAM_SIZE - 2 * sizeof(unsigned long); in fdt_fixup_muram()
29 do_fixup_by_compat(blob, "fsl,qe-muram-data", "reg", in fdt_fixup_muram()
34 void ft_cpu_setup(void *blob, bd_t *bd) in ft_cpu_setup() argument
37 int spridr = immr->sysconf.spridr; in ft_cpu_setup()
40 * delete crypto node if not on an E-processor in ft_cpu_setup()
62 if (REVID_MAJOR(immr->sysconf.spridr) >= 2) { in ft_cpu_setup()
100 "timebase-frequency", (bd->bi_busfreq / 4), 1); in ft_cpu_setup()
102 "bus-frequency", bd->bi_busfreq, 1); in ft_cpu_setup()
104 "clock-frequency", gd->arch.core_clk, 1); in ft_cpu_setup()
[all …]
/rk3399_rockchip-uboot/board/freescale/mpc837xemds/
H A Dmpc837xemds.c5 * SPDX-License-Identifier: GPL-2.0+
21 #include "../common/pq-mds-pib.h"
36 u32 spridr = in_be32(&immr->sysconf.spridr); in board_early_init_f()
64 int board_mmc_init(bd_t *bd) in board_mmc_init() argument
76 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); in board_mmc_init()
77 clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI, in board_mmc_init()
80 return fsl_esdhc_mmc_init(bd); in board_mmc_init()
85 int board_eth_init(bd_t *bd) in board_eth_init() argument
90 u32 rcwh = in_be32(&im->reset.rcwh); in board_eth_init()
136 fsl_pq_mdio_init(bd, &mdio_info); in board_eth_init()
[all …]
/rk3399_rockchip-uboot/board/freescale/p1_p2_rdb_pc/
H A Dspl.c4 * SPDX-License-Identifier: GPL-2.0+
34 setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); in board_init_f()
35 setbits_be32(&gur->pmuxcr, in board_init_f()
36 in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); in board_init_f()
39 in_be32(&gur->pmuxcr); in board_init_f()
42 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); in board_init_f()
46 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; in board_init_f()
49 gd->bus_clk = bus_clk; in board_init_f()
59 /* copy code to RAM and jump to it - this should not return */ in board_init_f()
60 /* NOTE - code has to be copied out of NAND buffer before in board_init_f()
[all …]
/rk3399_rockchip-uboot/board/freescale/p1010rdb/
H A Dspl.c3 * SPDX-License-Identifier: GPL-2.0+
34 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); in board_init_f()
37 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); in board_init_f()
41 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; in board_init_f()
43 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; in board_init_f()
46 gd->bus_clk / 16 / CONFIG_BAUDRATE); in board_init_f()
53 /* copy code to RAM and jump to it - this should not return */ in board_init_f()
54 /* NOTE - code has to be copied out of NAND buffer before in board_init_f()
64 bd_t *bd; in board_init_r() local
67 bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); in board_init_r()
[all …]
/rk3399_rockchip-uboot/board/freescale/t208xqds/
H A Dspl.c3 * SPDX-License-Identifier: GPL-2.0+
80 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; in board_init_f()
99 bd_t *bd; in board_init_r() local
101 bd = (bd_t *)(gd + sizeof(gd_t)); in board_init_r()
102 memset(bd, 0, sizeof(bd_t)); in board_init_r()
103 gd->bd = bd; in board_init_r()
104 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; in board_init_r()
105 bd->bi_memsize = CONFIG_SYS_L3_SIZE; in board_init_r()
111 gd->flags |= GD_FLG_FULL_MALLOC_INIT; in board_init_r()
118 mmc_initialize(bd); in board_init_r()
[all …]
/rk3399_rockchip-uboot/board/Arcturus/ucp1020/
H A Dspl.c2 * Copyright 2013-2015 Arcturus Networks, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
42 setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); in board_init_f()
43 setbits_be32(&gur->pmuxcr, in board_init_f()
44 in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); in board_init_f()
47 in_be32(&gur->pmuxcr); in board_init_f()
50 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); in board_init_f()
54 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; in board_init_f()
57 gd->bus_clk = bus_clk; in board_init_f()
67 /* copy code to RAM and jump to it - this should not return */ in board_init_f()
[all …]

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