16cb144bcSMacpaul Lin /*
26cb144bcSMacpaul Lin * Copyright (C) 2011 Andes Technology Corporation
36cb144bcSMacpaul Lin * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
46cb144bcSMacpaul Lin * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
56cb144bcSMacpaul Lin *
61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+
76cb144bcSMacpaul Lin */
86cb144bcSMacpaul Lin
96cb144bcSMacpaul Lin #include <common.h>
10be71a179Srick #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
116cb144bcSMacpaul Lin #include <netdev.h>
12b841b6e9Srick #endif
13b841b6e9Srick #include <linux/io.h>
14*3a53e99cSSimon Glass #include <asm/io.h>
15*3a53e99cSSimon Glass #include <asm/mach-types.h>
166cb144bcSMacpaul Lin
176cb144bcSMacpaul Lin #include <faraday/ftsdc010.h>
186cb144bcSMacpaul Lin #include <faraday/ftsmc020.h>
196cb144bcSMacpaul Lin
206cb144bcSMacpaul Lin DECLARE_GLOBAL_DATA_PTR;
216cb144bcSMacpaul Lin
226cb144bcSMacpaul Lin /*
236cb144bcSMacpaul Lin * Miscellaneous platform dependent initializations
246cb144bcSMacpaul Lin */
256cb144bcSMacpaul Lin
board_init(void)266cb144bcSMacpaul Lin int board_init(void)
276cb144bcSMacpaul Lin {
286cb144bcSMacpaul Lin /*
296cb144bcSMacpaul Lin * refer to BOOT_PARAMETER_PA_BASE within
306cb144bcSMacpaul Lin * "linux/arch/nds32/include/asm/misc_spec.h"
316cb144bcSMacpaul Lin */
32b841b6e9Srick printf("Board: %s\n" , CONFIG_SYS_BOARD);
336cb144bcSMacpaul Lin gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
346cb144bcSMacpaul Lin gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
356cb144bcSMacpaul Lin
366cb144bcSMacpaul Lin return 0;
376cb144bcSMacpaul Lin }
386cb144bcSMacpaul Lin
dram_init(void)396cb144bcSMacpaul Lin int dram_init(void)
406cb144bcSMacpaul Lin {
416cb144bcSMacpaul Lin unsigned long sdram_base = PHYS_SDRAM_0;
423c016704Sken kuo unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
436cb144bcSMacpaul Lin unsigned long actual_size;
446cb144bcSMacpaul Lin
456cb144bcSMacpaul Lin actual_size = get_ram_size((void *)sdram_base, expected_size);
466cb144bcSMacpaul Lin
476cb144bcSMacpaul Lin gd->ram_size = actual_size;
486cb144bcSMacpaul Lin
496cb144bcSMacpaul Lin if (expected_size != actual_size) {
506cb144bcSMacpaul Lin printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
516cb144bcSMacpaul Lin actual_size >> 20, expected_size >> 20);
526cb144bcSMacpaul Lin }
536cb144bcSMacpaul Lin
546cb144bcSMacpaul Lin return 0;
556cb144bcSMacpaul Lin }
566cb144bcSMacpaul Lin
dram_init_banksize(void)5776b00acaSSimon Glass int dram_init_banksize(void)
583c016704Sken kuo {
593c016704Sken kuo gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
603c016704Sken kuo gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
613c016704Sken kuo gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
623c016704Sken kuo gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
6376b00acaSSimon Glass
6476b00acaSSimon Glass return 0;
653c016704Sken kuo }
663c016704Sken kuo
67be71a179Srick #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
board_eth_init(bd_t * bd)686cb144bcSMacpaul Lin int board_eth_init(bd_t *bd)
696cb144bcSMacpaul Lin {
706cb144bcSMacpaul Lin return ftmac100_initialize(bd);
716cb144bcSMacpaul Lin }
72b841b6e9Srick #endif
736cb144bcSMacpaul Lin
board_flash_get_legacy(ulong base,int banknum,flash_info_t * info)746cb144bcSMacpaul Lin ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
756cb144bcSMacpaul Lin {
766cb144bcSMacpaul Lin if (banknum == 0) { /* non-CFI boot flash */
776cb144bcSMacpaul Lin info->portwidth = FLASH_CFI_8BIT;
786cb144bcSMacpaul Lin info->chipwidth = FLASH_CFI_BY8;
796cb144bcSMacpaul Lin info->interface = FLASH_CFI_X8;
806cb144bcSMacpaul Lin return 1;
816cb144bcSMacpaul Lin } else {
826cb144bcSMacpaul Lin return 0;
836cb144bcSMacpaul Lin }
846cb144bcSMacpaul Lin }
856cb144bcSMacpaul Lin
board_mmc_init(bd_t * bis)866cb144bcSMacpaul Lin int board_mmc_init(bd_t *bis)
876cb144bcSMacpaul Lin {
88b841b6e9Srick #ifdef CONFIG_FTSDC010
896cb144bcSMacpaul Lin ftsdc010_mmc_init(0);
90b841b6e9Srick #endif
916cb144bcSMacpaul Lin return 0;
926cb144bcSMacpaul Lin }
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