xref: /rk3399_rockchip-uboot/board/AndesTech/adp-ae3xx/adp-ae3xx.c (revision 8dc1b17f14c9201c7d0da0f33e404a7e051b2ec6)
1b841b6e9Srick /*
2b841b6e9Srick  * Copyright (C) 2011 Andes Technology Corporation
3b841b6e9Srick  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4b841b6e9Srick  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5b841b6e9Srick  *
6b841b6e9Srick  * SPDX-License-Identifier:	GPL-2.0+
7b841b6e9Srick  */
8b841b6e9Srick 
9b841b6e9Srick #include <common.h>
10*be71a179Srick #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
11b841b6e9Srick #include <netdev.h>
12b841b6e9Srick #endif
13b841b6e9Srick #include <linux/io.h>
14b841b6e9Srick #include <faraday/ftsdc010.h>
15b841b6e9Srick #include <faraday/ftsmc020.h>
16b841b6e9Srick 
17b841b6e9Srick DECLARE_GLOBAL_DATA_PTR;
18b841b6e9Srick 
19b841b6e9Srick /*
20b841b6e9Srick  * Miscellaneous platform dependent initializations
21b841b6e9Srick  */
board_init(void)22b841b6e9Srick int board_init(void)
23b841b6e9Srick {
24b841b6e9Srick 	/*
25b841b6e9Srick 	 * refer to BOOT_PARAMETER_PA_BASE within
26b841b6e9Srick 	 * "linux/arch/nds32/include/asm/misc_spec.h"
27b841b6e9Srick 	 */
28b841b6e9Srick 	printf("Board: %s\n" , CONFIG_SYS_BOARD);
29b841b6e9Srick 	gd->bd->bi_arch_number = MACH_TYPE_ADPAE3XX;
30b841b6e9Srick 	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
31b841b6e9Srick 	return 0;
32b841b6e9Srick }
33b841b6e9Srick 
dram_init(void)34b841b6e9Srick int dram_init(void)
35b841b6e9Srick {
36b841b6e9Srick 	unsigned long sdram_base = PHYS_SDRAM_0;
37b841b6e9Srick 	unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
38b841b6e9Srick 	unsigned long actual_size;
39b841b6e9Srick 	actual_size = get_ram_size((void *)sdram_base, expected_size);
40b841b6e9Srick 	gd->ram_size = actual_size;
41b841b6e9Srick 	if (expected_size != actual_size) {
42b841b6e9Srick 		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
43b841b6e9Srick 				actual_size >> 20, expected_size >> 20);
44b841b6e9Srick 	}
45b841b6e9Srick 
46b841b6e9Srick 	return 0;
47b841b6e9Srick }
48b841b6e9Srick 
dram_init_banksize(void)49b841b6e9Srick int dram_init_banksize(void)
50b841b6e9Srick {
51b841b6e9Srick 	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
52b841b6e9Srick 	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
53b841b6e9Srick 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
54b841b6e9Srick 	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
55b841b6e9Srick 
56b841b6e9Srick 	return 0;
57b841b6e9Srick }
58b841b6e9Srick 
59*be71a179Srick #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
board_eth_init(bd_t * bd)60b841b6e9Srick int board_eth_init(bd_t *bd)
61b841b6e9Srick {
62b841b6e9Srick 	return ftmac100_initialize(bd);
63b841b6e9Srick }
64b841b6e9Srick #endif
65b841b6e9Srick 
board_flash_get_legacy(ulong base,int banknum,flash_info_t * info)66b841b6e9Srick ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
67b841b6e9Srick {
68b841b6e9Srick 	if (banknum == 0) {	/* non-CFI boot flash */
69b841b6e9Srick 		info->portwidth = FLASH_CFI_8BIT;
70b841b6e9Srick 		info->chipwidth = FLASH_CFI_BY8;
71b841b6e9Srick 		info->interface = FLASH_CFI_X8;
72b841b6e9Srick 		return 1;
73b841b6e9Srick 	} else {
74b841b6e9Srick 		return 0;
75b841b6e9Srick 	}
76b841b6e9Srick }
77b841b6e9Srick 
board_mmc_init(bd_t * bis)78b841b6e9Srick int board_mmc_init(bd_t *bis)
79b841b6e9Srick {
80b841b6e9Srick #ifndef CONFIG_DM_MMC
81b841b6e9Srick #ifdef CONFIG_FTSDC010
82b841b6e9Srick 	ftsdc010_mmc_init(0);
83b841b6e9Srick #endif
84b841b6e9Srick #endif
85b841b6e9Srick 	return 0;
86b841b6e9Srick }
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