2  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4  * SPDX-License-Identifier:	GPL-2.0+
27 #define B_WFR		(1 << 19)	/* 1b - Wait for ready		*/
28 #define B_LC		(1 << 18)	/* 1b - Last cycle		*/
29 #define B_IWC		(1 << 13)	/* 1b - Interrupt when complete	*/
73 static struct nand_bd *bd;	/* DMA buffer descriptors	*/  variable
76  * axs101_nand_write_buf -  write buffer to chip
97  * axs101_nand_write_buf -  write buffer to chip
110 	writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);  in axs101_nand_write_buf()
111 	writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);  in axs101_nand_write_buf()
112 	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);  in axs101_nand_write_buf()
113 	writel(0, &bd->buffer_ptr1);  in axs101_nand_write_buf()
116 	flush_dcache_range((unsigned long)bd,  in axs101_nand_write_buf()
117 			   (unsigned long)bd + sizeof(struct nand_bd));  in axs101_nand_write_buf()
120 	NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));  in axs101_nand_write_buf()
132  * axs101_nand_read_buf -  read chip data into buffer
144 	writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);  in axs101_nand_read_buf()
145 	writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);  in axs101_nand_read_buf()
146 	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);  in axs101_nand_read_buf()
147 	writel(0, &bd->buffer_ptr1);  in axs101_nand_read_buf()
150 	flush_dcache_range((unsigned long)bd,  in axs101_nand_read_buf()
151 			   (unsigned long)bd + sizeof(struct nand_bd));  in axs101_nand_read_buf()
154 	NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));  in axs101_nand_read_buf()
166  * axs101_nand_read_byte -  read one byte from the chip
178  * axs101_nand_read_word -  read one word from the chip
190  * axs101_nand_hwcontrol - NAND control functions wrapper.
225 	bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,  in board_nand_init()
229 	NAND_REG_WRITE(IDMAC_BDADDR, bd);  in board_nand_init()
231 	nand->ecc.mode = NAND_ECC_SOFT;  in board_nand_init()
232 	nand->cmd_ctrl = axs101_nand_hwcontrol;  in board_nand_init()
233 	nand->read_byte = axs101_nand_read_byte;  in board_nand_init()
234 	nand->read_word = axs101_nand_read_word;  in board_nand_init()
235 	nand->write_buf = axs101_nand_write_buf;  in board_nand_init()
236 	nand->read_buf = axs101_nand_read_buf;  in board_nand_init()
238 	/* MBv3 has NAND IC with 16-bit data bus */  in board_nand_init()
239 	if (gd->board_type == AXS_MB_V3)  in board_nand_init()
240 		nand->options |= NAND_BUSWIDTH_16;  in board_nand_init()