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/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Ddram_regs.h75 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
76 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
78 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) argument
79 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) argument
80 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) argument
81 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) argument
82 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) argument
83 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) argument
84 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1)) argument
85 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) argument
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/secure/
H A Dsecure.h13 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) argument
14 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) argument
15 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) argument
16 #define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\ argument
20 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) argument
21 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) argument
22 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) argument
23 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) argument
55 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) argument
57 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) argument
[all …]
/rk3399_ARM-atf/fdts/
H A Dfvp-defs-dynamiq.dtsi30 #define CPU(n, r) \ argument
41 #define THREAD(n) \ argument
46 #define CORE(n) \ argument
53 #define CORE(n) \ argument
68 #define CLUSTER(n) \ argument
85 #define CLUSTER(n) \ argument
106 #define CLUSTER(n) \ argument
131 #define CLUSTER(n) \ argument
160 #define CLUSTER(n) \ argument
193 #define CLUSTER(n) \ argument
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H A Dfvp-defs.dtsi34 #define CLS(n) (n / CPUS_PER_CLUSTER) argument
37 #define POS(n) (n % CPUS_PER_CLUSTER) argument
39 #define ADR(n, c, p) \ argument
61 #define CPU(n, c, p) \ argument
314 #define CORE(n) \ argument
321 #define CLUSTER(n) \ argument
326 #define CLUSTER(n) \ argument
333 #define CLUSTER(n) \ argument
341 #define CLUSTER(n) \ argument
/rk3399_ARM-atf/plat/allwinner/common/include/
H A Dsunxi_cpucfg_ncat.h20 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) argument
21 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) argument
23 #define SUNXI_C0_CPU_CTRL_REG(n) (SUNXI_CPUCFG_BASE + 0x0060 + (n) * 4) argument
25 #define SUNXI_CPU_CTRL_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x20 + (n) * 4) argument
26 #define SUNXI_ALT_RVBAR_LO_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x40 + (n) * 8) argument
27 #define SUNXI_ALT_RVBAR_HI_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x44 + (n) * 8) argument
31 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ argument
33 #define SUNXI_CPU_UNK_REG(n) (SUNXI_R_CPUCFG_BASE + 0x0070 + (n) * 4) argument
H A Dsunxi_cpucfg_ncat2.h20 #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) argument
21 #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) argument
25 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ argument
/rk3399_ARM-atf/include/drivers/rpi3/gpio/
H A Drpi3_gpio.h18 #define RPI3_GPIO_GPFSEL(n) ((n) * U(0x04)) argument
19 #define RPI3_GPIO_GPSET(n) (((n) * U(0x04)) + U(0x1C)) argument
20 #define RPI3_GPIO_GPCLR(n) (((n) * U(0x04)) + U(0x28)) argument
21 #define RPI3_GPIO_GPLEV(n) (((n) * U(0x04)) + U(0x34)) argument
23 #define RPI3_GPIO_GPPUDCLK(n) (((n) * U(0x04)) + U(0x98)) argument
/rk3399_ARM-atf/drivers/arm/gic/v2/
H A Dgicdv2_helpers.c24 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr() local
35 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler() local
46 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler() local
57 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr() local
68 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr() local
79 unsigned int n = id >> ISACTIVER_SHIFT; in gicd_read_isactiver() local
90 unsigned int n = id >> ICACTIVER_SHIFT; in gicd_read_icactiver() local
101 unsigned int n = id >> IPRIORITYR_SHIFT; in gicd_read_ipriorityr() local
112 unsigned int n = id >> ICFGR_SHIFT; in gicd_read_icfgr() local
123 unsigned int n = id >> NSACR_SHIFT; in gicd_read_nsacr() local
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H A Dgicv2_helpers.c25 unsigned n = id >> ITARGETSR_SHIFT; in gicd_read_itargetsr() local
35 unsigned n = id >> CPENDSGIR_SHIFT; in gicd_read_cpendsgir() local
45 unsigned n = id >> SPENDSGIR_SHIFT; in gicd_read_spendsgir() local
55 unsigned n = id >> ITARGETSR_SHIFT; in gicd_write_itargetsr() local
65 unsigned n = id >> CPENDSGIR_SHIFT; in gicd_write_cpendsgir() local
75 unsigned n = id >> SPENDSGIR_SHIFT; in gicd_write_spendsgir() local
/rk3399_ARM-atf/drivers/arm/gic/common/
H A Dgic_common.c25 unsigned int n = id >> IGROUPR_SHIFT; in gicd_read_igroupr() local
36 unsigned int n = id >> ISENABLER_SHIFT; in gicd_read_isenabler() local
47 unsigned int n = id >> ICENABLER_SHIFT; in gicd_read_icenabler() local
58 unsigned int n = id >> ISPENDR_SHIFT; in gicd_read_ispendr() local
69 unsigned int n = id >> ICPENDR_SHIFT; in gicd_read_icpendr() local
80 unsigned int n = id >> ISACTIVER_SHIFT; in gicd_read_isactiver() local
91 unsigned int n = id >> ICACTIVER_SHIFT; in gicd_read_icactiver() local
102 unsigned int n = id >> IPRIORITYR_SHIFT; in gicd_read_ipriorityr() local
113 unsigned int n = id >> ICFGR_SHIFT; in gicd_read_icfgr() local
124 unsigned int n = id >> NSACR_SHIFT; in gicd_read_nsacr() local
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h44 #define CRU_SOFTRSTS_CON(n) (0x300 + ((n) * 4)) argument
67 #define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) argument
69 #define FIREWALL_CFG_FW_SYS_CON(n) (0x000 + (n) * 4) argument
70 #define FIREWALL_DDR_FW_DDR_RGN(n) (0x000 + (n) * 4) argument
71 #define FIREWALL_DDR_FW_DDR_MST(n) (0x020 + (n) * 4) argument
73 #define GRF_SOC_CON(n) (0x400 + (n) * 4) argument
74 #define GRF_SOC_STATUS(n) (0x480 + (n) * 4) argument
75 #define GRF_CPU_STATUS(n) (0x520 + (n) * 4) argument
76 #define GRF_OS_REG(n) (0x5c8 + (n) * 4) argument
77 #define DDRGRF_SOC_CON(n) (0x000 + (n) * 4) argument
[all …]
/rk3399_ARM-atf/drivers/renesas/rcar_gen4/mssr/
H A Dmssr.c15 #define MSSR_SRCR(n) (MSSR_BASE + 0x2C00U + (n) * 4) argument
16 #define MSSR_SRSTCLR(n) (MSSR_BASE + 0x2C80U + (n) * 4) argument
17 #define MSSR_MSTPCR(n) (MSSR_BASE + 0x2D00U + (n) * 4) argument
18 #define MSSR_MSTPSR(n) (MSSR_BASE + 0x2E00U + (n) * 4) argument
26 void rcar_mssr_clock(unsigned int n, uint32_t data, bool on, bool force) in rcar_mssr_clock()
50 void rcar_mssr_soft_reset(unsigned int n, uint32_t data, bool assert, bool force) in rcar_mssr_soft_reset()
/rk3399_ARM-atf/include/plat/arm/css/common/
H A Dcss_pm.h57 #define SET_SCMI_CHANNEL_ID(n) (((n) & SCMI_CHANNEL_ID_MASK) << \ argument
59 #define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument
60 #define GET_SCMI_CHANNEL_ID(n) (((n) >> SCMI_CHANNEL_ID_SHIFT) & \ argument
62 #define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.h15 #define PMUCRU_PPLL_CON(n) ((n) * 4) argument
16 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
29 #define FBDIV(n) ((0xfff << 16) | n) argument
30 #define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12)) argument
31 #define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8)) argument
32 #define REFDIV(n) ((0x3F << 16) | n) argument
33 #define PLL_LOCK(n) ((n >> 31) & 0x1) argument
46 #define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) argument
56 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) argument
57 #define CRU_GATE_CON(n) (0x300 + (n) * 4) argument
[all …]
/rk3399_ARM-atf/drivers/allwinner/
H A Dsunxi_msgbox.c22 #define RX_IRQ(n) BIT(0 + 2 * (n)) argument
23 #define TX_IRQ(n) BIT(1 + 2 * (n)) argument
25 #define FIFO_STAT_REG(n) (0x0100 + 0x4 * (n)) argument
28 #define MSG_STAT_REG(n) (0x0140 + 0x4 * (n)) argument
31 #define MSG_DATA_REG(n) (0x0180 + 0x4 * (n)) argument
/rk3399_ARM-atf/drivers/renesas/rcar_gen4/pwrc/
H A Dpwrc.c45 static uintptr_t apsreg_ap_cluster_aux0(uint32_t n) in apsreg_ap_cluster_aux0()
51 static uintptr_t rcar_apmu_cluster_base(uint32_t n) in rcar_apmu_cluster_base()
56 static uintptr_t rcar_apmu_cpu_base(uint32_t n) in rcar_apmu_cpu_base()
62 static uintptr_t rcar_apmu_pwrctrlcl(uint32_t n) in rcar_apmu_pwrctrlcl()
67 static uintptr_t rcar_apmu_pwrctrlc(uint32_t n) in rcar_apmu_pwrctrlc()
72 static uintptr_t rcar_apmu_safectrlc(uint32_t n) in rcar_apmu_safectrlc()
77 static uintptr_t rcar_apmu_rvbarplc(uint32_t n) in rcar_apmu_rvbarplc()
82 static uintptr_t rcar_apmu_rvbarphc(uint32_t n) in rcar_apmu_rvbarphc()
87 static uintptr_t rcar_apmu_fsmstsrc(uint32_t n) in rcar_apmu_fsmstsrc()
93 static uint32_t prr_caxx_xx_en_cpu(uint32_t n) in prr_caxx_xx_en_cpu()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c27 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ argument
29 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ argument
32 #define FBDIV_ENC(n) ((n) << 16) argument
33 #define FBDIV_DEC(n) (((n) >> 16) & 0xfff) argument
34 #define POSTDIV2_ENC(n) ((n) << 12) argument
35 #define POSTDIV2_DEC(n) (((n) >> 12) & 0x7) argument
36 #define POSTDIV1_ENC(n) ((n) << 8) argument
37 #define POSTDIV1_DEC(n) (((n) >> 8) & 0x7) argument
38 #define REFDIV_ENC(n) (n) argument
39 #define REFDIV_DEC(n) ((n) & 0x3f) argument
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/ddr/
H A Ddram_retention.c20 #define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * (n)) argument
21 #define CCM_CCGR(n) (CCM_CCGR_OFFSET + 0x10 * (n)) argument
22 #define CCM_TARGET_ROOT(n) (CCM_TARGET_ROOT_OFFSET + 0x80 * (n)) argument
/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgic600ae_fmu_helpers.c31 #define GIC_FMU_WRITE_64(base, reg, n, val) \ argument
76 #define GIC_FMU_WRITE_ON_IDLE_64(base, reg, n, val) \ argument
94 uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n) in gic_fmu_read_errfr()
110 uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n) in gic_fmu_read_errctlr()
126 uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n) in gic_fmu_read_errstatus()
203 void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val) in gic_fmu_write_errctlr()
212 void gic_fmu_write_errstatus(uintptr_t base, unsigned int n, uint64_t val) in gic_fmu_write_errstatus()
/rk3399_ARM-atf/plat/renesas/rcar_gen5/include/
H A Drcar_private.h99 #define SET_SCMI_CHANNEL_ID(n) \ argument
101 #define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument
102 #define GET_SCMI_CHANNEL_ID(n) \ argument
104 #define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) argument
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/secure/
H A Dsecure.h15 #define TZPC_SRAM_SECURE_4K(n) ((n) > 0x200 ? 0x200 : (n)) argument
30 #define SGRF_SOC_CON(n) ((((n) < 6) ? 0x0 : 0x38) + (n) * 4) argument
31 #define SGRF_BUSDMAC_CON(n) (0x20 + (n) * 4) argument
32 #define SGRF_CPU_CON(n) (0x40 + (n) * 4) argument
33 #define SGRF_SOC_STATUS(n) (0x100 + (n) * 4) argument
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dsspm_reg.h18 #define STANDBYWFI_EN(n) (1 << (n + 8)) argument
19 #define GIC_IRQOUT_EN(n) (1 << (n + 0)) argument
/rk3399_ARM-atf/plat/allwinner/common/
H A Dsunxi_cpu_ops.c23 #define SUNXI_C0_CPU_CTRL_REG(n) 0 argument
24 #define SUNXI_CPU_UNK_REG(n) 0 argument
25 #define SUNXI_CPU_CTRL_REG(n) 0 argument
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd2/
H A Dnrd_ros_fw_def2.h41 #define NRD_ROS_MEMCNTRL_MMAP(n) \ argument
76 #define NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(n) \ argument
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/dmc/
H A Ddmc_rk3576.h13 #define GRF_CH_CON(ch, n) ((((ch) % 2) * 0x100) + ((n) * 4)) argument
15 #define GRF_DDRPHY_CON(n) (0x530 + ((n) * 4)) argument
17 #define DDR_GRF_COMMON_CON(n) (0x540 + ((n) * 4)) argument
20 #define PMUGRF_OS_REG(n) (0x200 + ((n) * 4)) argument

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