| /rk3399_rockchip-uboot/board/micronas/vct/vctv/ |
| H A D | reg_ebi.h | 17 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
19 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
21 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
23 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
25 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
27 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
29 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
31 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
33 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
35 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
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| H A D | reg_gpio.h | 15 #define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS) argument
17 #define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS) argument
19 #define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS) argument
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| /rk3399_rockchip-uboot/board/micronas/vct/vcth2/ |
| H A D | reg_ebi.h | 17 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
19 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
21 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
23 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
25 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
27 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
29 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
31 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
33 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
35 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
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| /rk3399_rockchip-uboot/board/micronas/vct/vcth/ |
| H A D | reg_ebi.h | 17 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
19 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
21 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
23 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
25 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
27 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
29 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
31 #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) argument
33 #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) argument
35 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) argument
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| H A D | reg_fwsram.h | 22 #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) argument
24 #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) argument
26 #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) argument
28 #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) argument
30 #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) argument
32 #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) argument
34 #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) argument
36 #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) argument
38 #define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) argument
40 #define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) argument
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| H A D | reg_scc.h | 57 #define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) argument
59 #define SCC_RESET(base) ((base) + SCC_RESET_OFFS) argument
61 #define SCC_VCID(base) ((base) + SCC_VCID_OFFS) argument
63 #define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) argument
65 #define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) argument
67 #define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) argument
69 #define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) argument
71 #define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) argument
73 #define SCC_CMD(base) ((base) + SCC_CMD_OFFS) argument
75 #define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) argument
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| H A D | reg_usbh.h | 12 #define USBH_CAPLENGTH(base) ((base) + USBH_CAPLENGTH_OFFS) argument
14 #define USBH_USBCMD(base) ((base) + USBH_USBCMD_OFFS) argument
16 #define USBH_BURSTSIZE(base) ((base) + USBH_BURSTSIZE_OFFS) argument
18 #define USBH_USBMODE(base) ((base) + USBH_USBMODE_OFFS) argument
20 #define USBH_USBHMISC(base) ((base) + USBH_USBHMISC_OFFS) argument
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| H A D | reg_dcgu.h | 12 #define DCGU_CLK_EN1(base) ((base) + DCGU_CLK_EN1_OFFS) argument
14 #define DCGU_CLK_EN2(base) ((base) + DCGU_CLK_EN2_OFFS) argument
16 #define DCGU_RESET_UNIT1(base) ((base) + DCGU_RESET_UNIT1_OFFS) argument
18 #define DCGU_USBPHY_STAT(base) ((base) + DCGU_USBPHY_STAT_OFFS) argument
20 #define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS) argument
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| H A D | reg_gpio.h | 15 #define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS) argument
17 #define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS) argument
19 #define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS) argument
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| /rk3399_rockchip-uboot/arch/arm/mach-keystone/ |
| H A D | ddr3.c | 25 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) in ddr3_init_ddrphy()
102 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) in ddr3_init_ddremif()
113 int ddr3_ecc_support_rmw(u32 base) in ddr3_ecc_support_rmw()
125 static void ddr3_ecc_config(u32 base, u32 value) in ddr3_ecc_config()
149 static void ddr3_reset_data(u32 base, u32 ddr3_size) in ddr3_reset_data()
239 static void ddr3_ecc_init_range(u32 base) in ddr3_ecc_init_range()
252 void ddr3_enable_ecc(u32 base, int test) in ddr3_enable_ecc()
272 void ddr3_disable_ecc(u32 base) in ddr3_disable_ecc()
278 static void cic_init(u32 base) in cic_init()
291 static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num) in cic_map_cic_to_gic()
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| /rk3399_rockchip-uboot/drivers/net/ |
| H A D | tsi108_eth.c | 45 #define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset)))) argument
47 #define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000) argument
62 #define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004) argument
73 #define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010) argument
75 #define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020) argument
81 #define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024) argument
85 #define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028) argument
86 #define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c) argument
87 #define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030) argument
89 #define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034) argument
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| H A D | ne2000_base.c | 106 u8* base; in dp83902a_init() local
146 u8 *base = dp->base; in dp83902a_stop() local
167 u8 *base = dp->base; in dp83902a_start() local
218 u8 *base = dp->base; in dp83902a_start_xmit() local
246 u8 *base = dp->base; in dp83902a_send() local
376 u8 *base = dp->base; in dp83902a_RxEvent() local
448 u8 *base = dp->base; in dp83902a_recv() local
513 u8 *base = dp->base; in dp83902a_TxEvent() local
550 u8 *base = dp->base; in dp83902a_ClearCounters() local
567 u8 *base = dp->base; in dp83902a_Overflow() local
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| /rk3399_rockchip-uboot/drivers/serial/ |
| H A D | serial_mvebu_a3700.c | 13 void __iomem *base; member
37 void __iomem *base = plat->base; in mvebu_serial_putc() local
50 void __iomem *base = plat->base; in mvebu_serial_getc() local
61 void __iomem *base = plat->base; in mvebu_serial_pending() local
72 void __iomem *base = plat->base; in mvebu_serial_setbrg() local
92 void __iomem *base = plat->base; in mvebu_serial_probe() local
142 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; in _debug_uart_init() local
166 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; in _debug_uart_putc() local
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| H A D | serial_lpuart.c | 107 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_setbrg() local
120 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_getc() local
132 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_putc() local
143 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_tstc() local
157 struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg; in _lpuart_serial_init() local
185 struct lpuart_fsl_reg32 *base = plat->reg; in _lpuart32_serial_setbrg_7ulp() local
244 struct lpuart_fsl_reg32 *base = plat->reg; in _lpuart32_serial_setbrg() local
256 struct lpuart_fsl_reg32 *base = plat->reg; in _lpuart32_serial_getc() local
280 struct lpuart_fsl_reg32 *base = plat->reg; in _lpuart32_serial_putc() local
303 struct lpuart_fsl_reg32 *base = plat->reg; in _lpuart32_serial_tstc() local
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| /rk3399_rockchip-uboot/drivers/bios_emulator/ |
| H A D | biosemui.h | 67 #define readb_le(base) *((u8*)(base)) argument
68 #define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8)) argument
69 #define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \ argument
71 #define writeb_le(base, v) *((u8*)(base)) = (v) argument
72 #define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ argument
74 #define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ argument
79 #define readb_le(base) *((u8*)(base)) argument
80 #define readw_le(base) *((u16*)(base)) argument
81 #define readl_le(base) *((u32*)(base)) argument
82 #define writeb_le(base, v) *((u8*)(base)) = (v) argument
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| /rk3399_rockchip-uboot/lib/ |
| H A D | strto.c | 17 static const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) in _parse_integer_fixup_radix()
34 unsigned int base) in simple_strtoul()
53 int strict_strtoul(const char *cp, unsigned int base, unsigned long *res) in strict_strtoul()
77 long simple_strtol(const char *cp, char **endp, unsigned int base) in simple_strtol()
85 unsigned long ustrtoul(const char *cp, char **endp, unsigned int base) in ustrtoul()
108 unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base) in ustrtoull()
132 unsigned int base) in simple_strtoull()
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| /rk3399_rockchip-uboot/drivers/i2c/ |
| H A D | sh_sh7734_i2c.c | 29 static struct sh_i2c *base; variable
68 static void sh_i2c_send_stop(struct sh_i2c *base) in sh_i2c_send_stop()
73 static int check_icsr_bits(struct sh_i2c *base, u8 bits) in check_icsr_bits()
86 static int check_stop(struct sh_i2c *base) in check_stop()
94 static int check_tend(struct sh_i2c *base, int stop) in check_tend()
107 static int check_tdre(struct sh_i2c *base) in check_tdre()
112 static int check_rdrf(struct sh_i2c *base) in check_rdrf()
117 static int check_bbsy(struct sh_i2c *base) in check_bbsy()
129 static int check_ackbr(struct sh_i2c *base) in check_ackbr()
142 static void sh_i2c_reset(struct sh_i2c *base) in sh_i2c_reset()
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| H A D | fsl_i2c.c | 119 static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, in set_i2c_bus_speed()
209 static int fsl_i2c_fixup(const struct fsl_i2c_base *base) in fsl_i2c_fixup()
256 static void __i2c_init(const struct fsl_i2c_base *base, int speed, int in __i2c_init()
290 i2c_wait4bus(const struct fsl_i2c_base *base) in i2c_wait4bus()
304 i2c_wait(const struct fsl_i2c_base *base, int write) in i2c_wait()
342 i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta) in i2c_write_addr()
357 __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length) in __i2c_write_data()
372 __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length) in __i2c_read_data()
403 __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, in __i2c_read()
451 __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, in __i2c_write()
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| /rk3399_rockchip-uboot/drivers/dma/ |
| H A D | ti-edma3.c | 38 u32 base; member
51 void qedma3_start(u32 base, struct edma3_channel_config *cfg) in qedma3_start()
88 void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode, in edma3_set_dest()
119 void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx) in edma3_set_dest_index()
139 void edma3_set_dest_addr(u32 base, int slot, u32 dst) in edma3_set_dest_addr()
159 void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode, in edma3_set_src()
190 void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx) in edma3_set_src_index()
210 void edma3_set_src_addr(u32 base, int slot, u32 src) in edma3_set_src_addr()
248 void edma3_set_transfer_params(u32 base, int slot, int acnt, in edma3_set_transfer_params()
285 void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param) in edma3_write_slot()
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/ |
| H A D | emif-common.c | 23 void set_lpmode_selfrefresh(u32 base) in set_lpmode_selfrefresh()
45 inline u32 emif_num(u32 base) in emif_num()
55 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) in get_mr()
76 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) in set_mr()
85 void emif_reset_phy(u32 base) in emif_reset_phy()
95 static void do_lpddr2_init(u32 base, u32 cs) in do_lpddr2_init()
126 static void lpddr2_init(u32 base, const struct emif_regs *regs) in lpddr2_init()
160 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) in do_ext_phy_settings()
164 void emif_update_timings(u32 base, const struct emif_regs *regs) in emif_update_timings()
201 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) in omap5_ddr3_leveling()
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| /rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 34 void __iomem *base; in uniphier_ld20_sscpll_init() local
66 void __iomem *base; in uniphier_ld20_sscpll_ssc_en() local
84 void __iomem *base; in uniphier_ld20_sscpll_set_regi() local
103 void __iomem *base; in uniphier_ld20_vpll27_init() local
129 void __iomem *base; in uniphier_ld20_dspll_init() local
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| /rk3399_rockchip-uboot/arch/arm/cpu/armv7/kona-common/ |
| H A D | clk-stubs.c | 13 int __weak clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) in clk_sdio_enable()
18 int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep) in clk_bsc_enable()
23 int __weak clk_usb_otg_enable(void *base) in clk_usb_otg_enable()
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| /rk3399_rockchip-uboot/drivers/gpio/ |
| H A D | mpc85xx_gpio.c | 30 struct ccsr_gpio __iomem *base; member
45 static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask) in mpc85xx_gpio_get_val()
50 static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask) in mpc85xx_gpio_get_dir()
55 static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios) in mpc85xx_gpio_set_in()
62 static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios) in mpc85xx_gpio_set_low()
69 static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios) in mpc85xx_gpio_set_high()
76 static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask) in mpc85xx_gpio_open_drain_val()
81 static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32 in mpc85xx_gpio_open_drain_on()
88 static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base, in mpc85xx_gpio_open_drain_off()
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| /rk3399_rockchip-uboot/arch/arm/mach-mvebu/ |
| H A D | mbus.c | 109 int win, int *enabled, u64 *base, in mvebu_mbus_read_window()
175 phys_addr_t base, size_t size, in mvebu_mbus_window_conflicts()
214 phys_addr_t base, size_t size) in mvebu_mbus_find_window()
238 int win, phys_addr_t base, size_t size, in mvebu_mbus_setup_window()
266 phys_addr_t base, size_t size, in mvebu_mbus_alloc_window()
327 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); in mvebu_mbus_default_setup_cpu_target() local
376 phys_addr_t base, size_t size, in mvebu_mbus_add_window_remap_by_id()
391 phys_addr_t base, size_t size) in mvebu_mbus_add_window_by_id()
397 int mvebu_mbus_del_window(phys_addr_t base, size_t size) in mvebu_mbus_del_window()
410 phys_addr_t *base) in mvebu_mbus_get_lowest_base()
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| /rk3399_rockchip-uboot/drivers/soc/keystone/ |
| H A D | keystone_serdes.c | 109 static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size) in ks2_serdes_cfg_setup()
117 static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane, in ks2_serdes_lane_config()
127 static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes) in ks2_serdes_init_cfg()
140 static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes) in ks2_serdes_cmu_comlane_enable()
155 static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes) in ks2_serdes_pll_enable()
161 static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane) in ks2_serdes_lane_reset()
171 static void ks2_serdes_lane_enable(u32 base, in ks2_serdes_lane_enable()
187 int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes) in ks2_serdes_init()
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