| /optee_os/core/include/drivers/ |
| H A D | zynqmp_pm.h | 29 #define ZYNQMP_EFUSE_LEN(_id) ZYNQMP_EFUSE_##_id##_LENGTH argument
32 #define ZYNQMP_EFUSE_MEM(_id) (ROUNDUP(ZYNQMP_EFUSE_LEN(_id), CACHELINE_LEN)) argument
|
| /optee_os/ta/pkcs11/src/ |
| H A D | pkcs11_helpers.c | 28 #define PKCS11_ID_SZ(_id, _sz) \ argument
31 #define PKCS11_ID_SZ(_id, _sz) \ argument
116 #define PKCS11_ID(_id) { .id = _id, .string = #_id } argument
118 #define PKCS11_ID(_id) { .id = _id } argument
|
| /optee_os/core/drivers/crypto/crypto_api/include/ |
| H A D | drvcrypt_asn1_oid.h | 129 #define DRVCRYPT_OID_LEN(_id) (sizeof(_id) - 1) argument
|
| /optee_os/core/arch/arm/plat-stm32mp1/ |
| H A D | scmi_server.c | 121 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ argument
130 #define CLOCK_CELL_DECPROT(_scmi_id, _id, _name, _init_enabled, _etzpc_id) \ argument
139 #define RESET_CELL(_scmi_id, _id, _name) \ argument
147 #define RESET_CELL_DECPROT(_scmi_id, _id, _name, _etzpc_id) \ argument
|
| /optee_os/core/drivers/ |
| H A D | versal_puf.c | 20 #define PUF_API_ID(_id) ((VERSAL_PUF_MODULE << VERSAL_PUF_MODULE_SHIFT) | (_id)) argument
|
| H A D | versal_nvm.c | 24 #define NVM_API_ID(_id) ((NVM_MODULE << NVM_MODULE_SHIFT) | (_id)) argument
|
| /optee_os/core/arch/arm/plat-stm32mp1/drivers/ |
| H A D | stm32mp1_pwr.c | 161 #define DEFINE_REG(_id, _name, _supply) { \ argument
|
| /optee_os/core/drivers/regulator/ |
| H A D | stm32mp13_regulator_iod.c | 254 #define DEFINE_REG(_id, _name, _supply_name) { \ argument
|
| /optee_os/core/arch/arm/plat-sam/ |
| H A D | scmi_server.c | 21 #define RESET_CELL(_scmi_id, _id, _name) \ argument
|
| /optee_os/core/drivers/clk/ |
| H A D | clk-stm32mp13.c | 270 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\ argument
444 #define MUXRDY_CFG(_id, _offset, _shift, _witdh, _rdy)\ argument
452 #define MUX_CFG(_id, _offset, _shift, _witdh)\ argument
527 #define DIVRDY_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
537 #define DIV_CFG(_id, _offset, _shift, _width, _flags, _table)\ argument
|
| H A D | clk-stm32mp21.c | 382 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\ argument
566 #define _MUX_CFG(_id, _offset, _shift, _width, _rdy)\ argument
611 #define _DIV_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
|
| H A D | clk-stm32mp25.c | 372 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\ argument
601 #define _MUX_CFG(_id, _offset, _shift, _width, _rdy)\ argument
651 #define _DIV_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
|
| /optee_os/core/drivers/clk/sam/ |
| H A D | clk-sam9x60-pll.c | 60 #define WAIT_PLL_READY_TIMEOUT(_base, _id) \ argument
|
| H A D | at91_pmc.h | 152 #define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MASK) argument
|