1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Serial Flash Controller Driver 4 * 5 * Copyright (c) 2017-2021, Rockchip Inc. 6 * Author: Shawn Lin <shawn.lin@rock-chips.com> 7 * Chris Morgan <macromorgan@hotmail.com> 8 * Jon Lin <Jon.lin@rock-chips.com> 9 */ 10 11 #include <asm/io.h> 12 #include <bouncebuf.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <linux/bitops.h> 16 #include <linux/delay.h> 17 #include <linux/iopoll.h> 18 #include <spi.h> 19 #include <spi-mem.h> 20 21 /* System control */ 22 #define SFC_CTRL 0x0 23 #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) 24 #define SFC_CTRL_CMD_BITS_SHIFT 8 25 #define SFC_CTRL_ADDR_BITS_SHIFT 10 26 #define SFC_CTRL_DATA_BITS_SHIFT 12 27 28 /* Interrupt mask */ 29 #define SFC_IMR 0x4 30 #define SFC_IMR_RX_FULL BIT(0) 31 #define SFC_IMR_RX_UFLOW BIT(1) 32 #define SFC_IMR_TX_OFLOW BIT(2) 33 #define SFC_IMR_TX_EMPTY BIT(3) 34 #define SFC_IMR_TRAN_FINISH BIT(4) 35 #define SFC_IMR_BUS_ERR BIT(5) 36 #define SFC_IMR_NSPI_ERR BIT(6) 37 #define SFC_IMR_DMA BIT(7) 38 39 /* Interrupt clear */ 40 #define SFC_ICLR 0x8 41 #define SFC_ICLR_RX_FULL BIT(0) 42 #define SFC_ICLR_RX_UFLOW BIT(1) 43 #define SFC_ICLR_TX_OFLOW BIT(2) 44 #define SFC_ICLR_TX_EMPTY BIT(3) 45 #define SFC_ICLR_TRAN_FINISH BIT(4) 46 #define SFC_ICLR_BUS_ERR BIT(5) 47 #define SFC_ICLR_NSPI_ERR BIT(6) 48 #define SFC_ICLR_DMA BIT(7) 49 50 /* FIFO threshold level */ 51 #define SFC_FTLR 0xc 52 #define SFC_FTLR_TX_SHIFT 0 53 #define SFC_FTLR_TX_MASK 0x1f 54 #define SFC_FTLR_RX_SHIFT 8 55 #define SFC_FTLR_RX_MASK 0x1f 56 57 /* Reset FSM and FIFO */ 58 #define SFC_RCVR 0x10 59 #define SFC_RCVR_RESET BIT(0) 60 61 /* Enhanced mode */ 62 #define SFC_AX 0x14 63 64 /* Address Bit number */ 65 #define SFC_ABIT 0x18 66 67 /* Interrupt status */ 68 #define SFC_ISR 0x1c 69 #define SFC_ISR_RX_FULL_SHIFT BIT(0) 70 #define SFC_ISR_RX_UFLOW_SHIFT BIT(1) 71 #define SFC_ISR_TX_OFLOW_SHIFT BIT(2) 72 #define SFC_ISR_TX_EMPTY_SHIFT BIT(3) 73 #define SFC_ISR_TX_FINISH_SHIFT BIT(4) 74 #define SFC_ISR_BUS_ERR_SHIFT BIT(5) 75 #define SFC_ISR_NSPI_ERR_SHIFT BIT(6) 76 #define SFC_ISR_DMA_SHIFT BIT(7) 77 78 /* FIFO status */ 79 #define SFC_FSR 0x20 80 #define SFC_FSR_TX_IS_FULL BIT(0) 81 #define SFC_FSR_TX_IS_EMPTY BIT(1) 82 #define SFC_FSR_RX_IS_EMPTY BIT(2) 83 #define SFC_FSR_RX_IS_FULL BIT(3) 84 #define SFC_FSR_TXLV_MASK GENMASK(12, 8) 85 #define SFC_FSR_TXLV_SHIFT 8 86 #define SFC_FSR_RXLV_MASK GENMASK(20, 16) 87 #define SFC_FSR_RXLV_SHIFT 16 88 89 /* FSM status */ 90 #define SFC_SR 0x24 91 #define SFC_SR_IS_IDLE 0x0 92 #define SFC_SR_IS_BUSY 0x1 93 94 /* Raw interrupt status */ 95 #define SFC_RISR 0x28 96 #define SFC_RISR_RX_FULL BIT(0) 97 #define SFC_RISR_RX_UNDERFLOW BIT(1) 98 #define SFC_RISR_TX_OVERFLOW BIT(2) 99 #define SFC_RISR_TX_EMPTY BIT(3) 100 #define SFC_RISR_TRAN_FINISH BIT(4) 101 #define SFC_RISR_BUS_ERR BIT(5) 102 #define SFC_RISR_NSPI_ERR BIT(6) 103 #define SFC_RISR_DMA BIT(7) 104 105 /* Version */ 106 #define SFC_VER 0x2C 107 #define SFC_VER_3 0x3 108 #define SFC_VER_4 0x4 109 #define SFC_VER_5 0x5 110 111 /* Delay line controller resiter */ 112 #define SFC_DLL_CTRL0 0x3C 113 #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) 114 #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU 115 #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU 116 117 /* Master trigger */ 118 #define SFC_DMA_TRIGGER 0x80 119 #define SFC_DMA_TRIGGER_START 1 120 121 /* Src or Dst addr for master */ 122 #define SFC_DMA_ADDR 0x84 123 124 /* Length control register extension 32GB */ 125 #define SFC_LEN_CTRL 0x88 126 #define SFC_LEN_CTRL_TRB_SEL 1 127 #define SFC_LEN_EXT 0x8C 128 129 /* Command */ 130 #define SFC_CMD 0x100 131 #define SFC_CMD_IDX_SHIFT 0 132 #define SFC_CMD_DUMMY_SHIFT 8 133 #define SFC_CMD_DIR_SHIFT 12 134 #define SFC_CMD_DIR_RD 0 135 #define SFC_CMD_DIR_WR 1 136 #define SFC_CMD_ADDR_SHIFT 14 137 #define SFC_CMD_ADDR_0BITS 0 138 #define SFC_CMD_ADDR_24BITS 1 139 #define SFC_CMD_ADDR_32BITS 2 140 #define SFC_CMD_ADDR_XBITS 3 141 #define SFC_CMD_TRAN_BYTES_SHIFT 16 142 #define SFC_CMD_CS_SHIFT 30 143 144 /* Address */ 145 #define SFC_ADDR 0x104 146 147 /* Data */ 148 #define SFC_DATA 0x108 149 150 /* The controller and documentation reports that it supports up to 4 CS 151 * devices (0-3), however I have only been able to test a single CS (CS 0) 152 * due to the configuration of my device. 153 */ 154 #define SFC_MAX_CHIPSELECT_NUM 4 155 156 /* The SFC can transfer max 16KB - 1 at one time 157 * we set it to 15.5KB here for alignment. 158 */ 159 #define SFC_MAX_IOSIZE_VER3 (512 * 31) 160 161 #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU) 162 163 /* DMA is only enabled for large data transmission */ 164 #define SFC_DMA_TRANS_THRETHOLD (0x40) 165 166 /* Maximum clock values from datasheet suggest keeping clock value under 167 * 150MHz. No minimum or average value is suggested. 168 */ 169 #define SFC_MAX_SPEED (150 * 1000 * 1000) 170 171 struct rockchip_sfc { 172 struct udevice *dev; 173 void __iomem *regbase; 174 struct clk hclk; 175 struct clk clk; 176 u32 max_freq; 177 u32 speed; 178 bool use_dma; 179 u32 max_iosize; 180 u16 version; 181 }; 182 183 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 184 { 185 int err; 186 u32 status; 187 188 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); 189 190 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, 191 !(status & SFC_RCVR_RESET), 192 1000000); 193 if (err) 194 printf("SFC reset never finished\n"); 195 196 /* Still need to clear the masked interrupt from RISR */ 197 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 198 199 return err; 200 } 201 202 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 203 { 204 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); 205 } 206 207 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) 208 { 209 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 210 return SFC_MAX_IOSIZE_VER4; 211 212 return SFC_MAX_IOSIZE_VER3; 213 } 214 215 static int rockchip_sfc_init(struct rockchip_sfc *sfc) 216 { 217 writel(0, sfc->regbase + SFC_CTRL); 218 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 219 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); 220 221 return 0; 222 } 223 224 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 225 { 226 struct rockchip_sfc *sfc = dev_get_platdata(bus); 227 228 sfc->regbase = dev_read_addr_ptr(bus); 229 if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) 230 sfc->use_dma = false; 231 else 232 sfc->use_dma = true; 233 234 #if CONFIG_IS_ENABLED(CLK) 235 int ret; 236 237 ret = clk_get_by_index(bus, 0, &sfc->clk); 238 if (ret < 0) { 239 printf("Could not get clock for %s: %d\n", bus->name, ret); 240 return ret; 241 } 242 243 ret = clk_get_by_index(bus, 1, &sfc->hclk); 244 if (ret < 0) { 245 printf("Could not get ahb clock for %s: %d\n", bus->name, ret); 246 return ret; 247 } 248 #endif 249 250 return 0; 251 } 252 253 static int rockchip_sfc_probe(struct udevice *bus) 254 { 255 struct rockchip_sfc *sfc = dev_get_platdata(bus); 256 int ret; 257 258 #if CONFIG_IS_ENABLED(CLK) 259 ret = clk_enable(&sfc->hclk); 260 if (ret) 261 dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); 262 263 ret = clk_enable(&sfc->clk); 264 if (ret) 265 dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); 266 #endif 267 268 ret = rockchip_sfc_init(sfc); 269 if (ret) 270 goto err_init; 271 272 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); 273 sfc->version = rockchip_sfc_get_version(sfc); 274 sfc->max_freq = SFC_MAX_SPEED; 275 sfc->dev = bus; 276 277 return 0; 278 279 err_init: 280 #if CONFIG_IS_ENABLED(CLK) 281 clk_disable(&sfc->clk); 282 clk_disable(&sfc->hclk); 283 #endif 284 285 return ret; 286 } 287 288 static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr) 289 { 290 u32 fsr = readl(sfc->regbase + SFC_FSR); 291 int level; 292 293 if (wr) 294 level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; 295 else 296 level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; 297 298 return level; 299 } 300 301 static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout) 302 { 303 unsigned long tbase = get_timer(0); 304 int level; 305 306 while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) { 307 if (get_timer(tbase) > timeout) { 308 debug("%s fifo timeout\n", wr ? "write" : "read"); 309 return -ETIMEDOUT; 310 } 311 udelay(1); 312 } 313 314 return level; 315 } 316 317 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) 318 { 319 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { 320 /* 321 * SFC not support output DUMMY cycles right after CMD cycles, so 322 * treat it as ADDR cycles. 323 */ 324 op->addr.nbytes = op->dummy.nbytes; 325 op->addr.buswidth = op->dummy.buswidth; 326 op->addr.val = 0xFFFFFFFFF; 327 328 op->dummy.nbytes = 0; 329 } 330 } 331 332 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) 333 { 334 unsigned long tbase; 335 336 /* Wait for the DMA interrupt status */ 337 tbase = get_timer(0); 338 while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { 339 if (get_timer(tbase) > timeout) { 340 printf("dma timeout\n"); 341 rockchip_sfc_reset(sfc); 342 343 return -ETIMEDOUT; 344 } 345 346 udelay(1); 347 } 348 349 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 350 351 return 0; 352 } 353 354 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, 355 struct spi_slave *mem, 356 const struct spi_mem_op *op, 357 u32 len) 358 { 359 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 360 u32 ctrl = 0, cmd = 0; 361 362 /* set CMD */ 363 cmd = op->cmd.opcode; 364 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); 365 366 /* set ADDR */ 367 if (op->addr.nbytes) { 368 if (op->addr.nbytes == 4) { 369 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; 370 } else if (op->addr.nbytes == 3) { 371 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; 372 } else { 373 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; 374 writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); 375 } 376 377 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); 378 } 379 380 /* set DUMMY */ 381 if (op->dummy.nbytes) { 382 if (op->dummy.buswidth == 4) 383 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; 384 else if (op->dummy.buswidth == 2) 385 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; 386 else 387 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; 388 } 389 390 /* set DATA */ 391 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ 392 writel(len, sfc->regbase + SFC_LEN_EXT); 393 else 394 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; 395 if (len) { 396 if (op->data.dir == SPI_MEM_DATA_OUT) 397 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 398 399 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); 400 } 401 if (!len && op->addr.nbytes) 402 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 403 404 /* set the Controller */ 405 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; 406 cmd |= plat->cs << SFC_CMD_CS_SHIFT; 407 408 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", 409 op->addr.nbytes, op->addr.buswidth, 410 op->dummy.nbytes, op->dummy.buswidth); 411 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", 412 ctrl, cmd, op->addr.val, len); 413 414 writel(ctrl, sfc->regbase + SFC_CTRL); 415 writel(cmd, sfc->regbase + SFC_CMD); 416 if (op->addr.nbytes) 417 writel(op->addr.val, sfc->regbase + SFC_ADDR); 418 419 return 0; 420 } 421 422 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) 423 { 424 u8 bytes = len & 0x3; 425 u32 dwords; 426 int tx_level; 427 u32 write_words; 428 u32 tmp = 0; 429 430 dwords = len >> 2; 431 while (dwords) { 432 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000); 433 if (tx_level < 0) 434 return tx_level; 435 write_words = min_t(u32, tx_level, dwords); 436 writesl(sfc->regbase + SFC_DATA, buf, write_words); 437 buf += write_words << 2; 438 dwords -= write_words; 439 } 440 441 /* write the rest non word aligned bytes */ 442 if (bytes) { 443 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000); 444 if (tx_level < 0) 445 return tx_level; 446 memcpy(&tmp, buf, bytes); 447 writel(tmp, sfc->regbase + SFC_DATA); 448 } 449 450 return len; 451 } 452 453 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) 454 { 455 u8 bytes = len & 0x3; 456 u32 dwords; 457 u8 read_words; 458 int rx_level; 459 int tmp; 460 461 /* word aligned access only */ 462 dwords = len >> 2; 463 while (dwords) { 464 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000); 465 if (rx_level < 0) 466 return rx_level; 467 read_words = min_t(u32, rx_level, dwords); 468 readsl(sfc->regbase + SFC_DATA, buf, read_words); 469 buf += read_words << 2; 470 dwords -= read_words; 471 } 472 473 /* read the rest non word aligned bytes */ 474 if (bytes) { 475 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000); 476 if (rx_level < 0) 477 return rx_level; 478 tmp = readl(sfc->regbase + SFC_DATA); 479 memcpy(buf, &tmp, bytes); 480 } 481 482 return len; 483 } 484 485 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) 486 { 487 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 488 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); 489 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); 490 491 return len; 492 } 493 494 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, 495 const struct spi_mem_op *op, u32 len) 496 { 497 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); 498 499 if (op->data.dir == SPI_MEM_DATA_OUT) 500 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); 501 else 502 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); 503 } 504 505 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, 506 const struct spi_mem_op *op, u32 len) 507 { 508 struct bounce_buffer bb; 509 unsigned int bb_flags; 510 void *dma_buf; 511 int ret; 512 513 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); 514 515 if (op->data.dir == SPI_MEM_DATA_OUT) { 516 dma_buf = (void *)op->data.buf.out; 517 bb_flags = GEN_BB_READ; 518 } else { 519 dma_buf = (void *)op->data.buf.in; 520 bb_flags = GEN_BB_WRITE; 521 } 522 523 ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags); 524 if (ret) 525 return ret; 526 527 ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); 528 rockchip_sfc_wait_for_dma_finished(sfc, len * 10); 529 bounce_buffer_stop(&bb); 530 531 return ret; 532 } 533 534 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) 535 { 536 unsigned long tbase = get_timer(0); 537 int ret = 0; 538 u32 timeout = timeout_us; 539 540 while (readl(sfc->regbase + SFC_SR) & SFC_SR_IS_BUSY) { 541 if (get_timer(tbase) > timeout) { 542 printf("wait sfc idle timeout\n"); 543 rockchip_sfc_reset(sfc); 544 545 return -ETIMEDOUT; 546 } 547 548 udelay(1); 549 } 550 551 return ret; 552 } 553 554 static int rockchip_sfc_exec_op(struct spi_slave *mem, 555 const struct spi_mem_op *op) 556 { 557 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 558 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 559 int ret; 560 561 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 562 rockchip_sfc_xfer_setup(sfc, mem, op, len); 563 if (len) { 564 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) 565 ret = rockchip_sfc_xfer_data_dma(sfc, op, len); 566 else 567 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 568 569 if (ret != len) { 570 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); 571 572 return -EIO; 573 } 574 } 575 576 return rockchip_sfc_xfer_done(sfc, 100000); 577 } 578 579 static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op) 580 { 581 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 582 583 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); 584 585 return 0; 586 } 587 588 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 589 { 590 struct rockchip_sfc *sfc = dev_get_platdata(bus); 591 592 if (speed > sfc->max_freq) 593 speed = sfc->max_freq; 594 595 if (speed == sfc->speed) 596 return 0; 597 598 #if CONFIG_IS_ENABLED(CLK) 599 int ret = clk_set_rate(&sfc->clk, speed); 600 601 if (ret < 0) { 602 dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", 603 speed); 604 return ret; 605 } 606 sfc->speed = speed; 607 #else 608 dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); 609 #endif 610 return 0; 611 } 612 613 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 614 { 615 return 0; 616 } 617 618 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { 619 .adjust_op_size = rockchip_sfc_adjust_op_size, 620 .exec_op = rockchip_sfc_exec_op, 621 }; 622 623 static const struct dm_spi_ops rockchip_sfc_ops = { 624 .mem_ops = &rockchip_sfc_mem_ops, 625 .set_speed = rockchip_sfc_set_speed, 626 .set_mode = rockchip_sfc_set_mode, 627 }; 628 629 static const struct udevice_id rockchip_sfc_ids[] = { 630 { .compatible = "rockchip,sfc"}, 631 {}, 632 }; 633 634 U_BOOT_DRIVER(rockchip_sfc_driver) = { 635 .name = "rockchip_sfc", 636 .id = UCLASS_SPI, 637 .of_match = rockchip_sfc_ids, 638 .ops = &rockchip_sfc_ops, 639 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 640 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc), 641 .probe = rockchip_sfc_probe, 642 }; 643