1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Serial Flash Controller Driver 4 * 5 * Copyright (c) 2017-2021, Rockchip Inc. 6 * Author: Shawn Lin <shawn.lin@rock-chips.com> 7 * Chris Morgan <macromorgan@hotmail.com> 8 * Jon Lin <Jon.lin@rock-chips.com> 9 */ 10 11 #include <asm/io.h> 12 #include <bouncebuf.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <linux/bitops.h> 16 #include <linux/delay.h> 17 #include <linux/iopoll.h> 18 #include <spi.h> 19 #include <spi-mem.h> 20 21 /* System control */ 22 #define SFC_CTRL 0x0 23 #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) 24 #define SFC_CTRL_CMD_BITS_SHIFT 8 25 #define SFC_CTRL_ADDR_BITS_SHIFT 10 26 #define SFC_CTRL_DATA_BITS_SHIFT 12 27 28 /* Interrupt mask */ 29 #define SFC_IMR 0x4 30 #define SFC_IMR_RX_FULL BIT(0) 31 #define SFC_IMR_RX_UFLOW BIT(1) 32 #define SFC_IMR_TX_OFLOW BIT(2) 33 #define SFC_IMR_TX_EMPTY BIT(3) 34 #define SFC_IMR_TRAN_FINISH BIT(4) 35 #define SFC_IMR_BUS_ERR BIT(5) 36 #define SFC_IMR_NSPI_ERR BIT(6) 37 #define SFC_IMR_DMA BIT(7) 38 39 /* Interrupt clear */ 40 #define SFC_ICLR 0x8 41 #define SFC_ICLR_RX_FULL BIT(0) 42 #define SFC_ICLR_RX_UFLOW BIT(1) 43 #define SFC_ICLR_TX_OFLOW BIT(2) 44 #define SFC_ICLR_TX_EMPTY BIT(3) 45 #define SFC_ICLR_TRAN_FINISH BIT(4) 46 #define SFC_ICLR_BUS_ERR BIT(5) 47 #define SFC_ICLR_NSPI_ERR BIT(6) 48 #define SFC_ICLR_DMA BIT(7) 49 50 /* FIFO threshold level */ 51 #define SFC_FTLR 0xc 52 #define SFC_FTLR_TX_SHIFT 0 53 #define SFC_FTLR_TX_MASK 0x1f 54 #define SFC_FTLR_RX_SHIFT 8 55 #define SFC_FTLR_RX_MASK 0x1f 56 57 /* Reset FSM and FIFO */ 58 #define SFC_RCVR 0x10 59 #define SFC_RCVR_RESET BIT(0) 60 61 /* Enhanced mode */ 62 #define SFC_AX 0x14 63 64 /* Address Bit number */ 65 #define SFC_ABIT 0x18 66 67 /* Interrupt status */ 68 #define SFC_ISR 0x1c 69 #define SFC_ISR_RX_FULL_SHIFT BIT(0) 70 #define SFC_ISR_RX_UFLOW_SHIFT BIT(1) 71 #define SFC_ISR_TX_OFLOW_SHIFT BIT(2) 72 #define SFC_ISR_TX_EMPTY_SHIFT BIT(3) 73 #define SFC_ISR_TX_FINISH_SHIFT BIT(4) 74 #define SFC_ISR_BUS_ERR_SHIFT BIT(5) 75 #define SFC_ISR_NSPI_ERR_SHIFT BIT(6) 76 #define SFC_ISR_DMA_SHIFT BIT(7) 77 78 /* FIFO status */ 79 #define SFC_FSR 0x20 80 #define SFC_FSR_TX_IS_FULL BIT(0) 81 #define SFC_FSR_TX_IS_EMPTY BIT(1) 82 #define SFC_FSR_RX_IS_EMPTY BIT(2) 83 #define SFC_FSR_RX_IS_FULL BIT(3) 84 #define SFC_FSR_TXLV_MASK GENMASK(12, 8) 85 #define SFC_FSR_TXLV_SHIFT 8 86 #define SFC_FSR_RXLV_MASK GENMASK(20, 16) 87 #define SFC_FSR_RXLV_SHIFT 16 88 89 /* FSM status */ 90 #define SFC_SR 0x24 91 #define SFC_SR_IS_IDLE 0x0 92 #define SFC_SR_IS_BUSY 0x1 93 94 /* Raw interrupt status */ 95 #define SFC_RISR 0x28 96 #define SFC_RISR_RX_FULL BIT(0) 97 #define SFC_RISR_RX_UNDERFLOW BIT(1) 98 #define SFC_RISR_TX_OVERFLOW BIT(2) 99 #define SFC_RISR_TX_EMPTY BIT(3) 100 #define SFC_RISR_TRAN_FINISH BIT(4) 101 #define SFC_RISR_BUS_ERR BIT(5) 102 #define SFC_RISR_NSPI_ERR BIT(6) 103 #define SFC_RISR_DMA BIT(7) 104 105 /* Version */ 106 #define SFC_VER 0x2C 107 #define SFC_VER_3 0x3 108 #define SFC_VER_4 0x4 109 #define SFC_VER_5 0x5 110 111 /* Delay line controller resiter */ 112 #define SFC_DLL_CTRL0 0x3C 113 #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) 114 #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU 115 #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU 116 117 /* Master trigger */ 118 #define SFC_DMA_TRIGGER 0x80 119 120 /* Src or Dst addr for master */ 121 #define SFC_DMA_ADDR 0x84 122 123 /* Length control register extension 32GB */ 124 #define SFC_LEN_CTRL 0x88 125 #define SFC_LEN_CTRL_TRB_SEL 1 126 #define SFC_LEN_EXT 0x8C 127 128 /* Command */ 129 #define SFC_CMD 0x100 130 #define SFC_CMD_IDX_SHIFT 0 131 #define SFC_CMD_DUMMY_SHIFT 8 132 #define SFC_CMD_DIR_SHIFT 12 133 #define SFC_CMD_DIR_RD 0 134 #define SFC_CMD_DIR_WR 1 135 #define SFC_CMD_ADDR_SHIFT 14 136 #define SFC_CMD_ADDR_0BITS 0 137 #define SFC_CMD_ADDR_24BITS 1 138 #define SFC_CMD_ADDR_32BITS 2 139 #define SFC_CMD_ADDR_XBITS 3 140 #define SFC_CMD_TRAN_BYTES_SHIFT 16 141 #define SFC_CMD_CS_SHIFT 30 142 143 /* Address */ 144 #define SFC_ADDR 0x104 145 146 /* Data */ 147 #define SFC_DATA 0x108 148 149 /* The controller and documentation reports that it supports up to 4 CS 150 * devices (0-3), however I have only been able to test a single CS (CS 0) 151 * due to the configuration of my device. 152 */ 153 #define SFC_MAX_CHIPSELECT_NUM 4 154 155 /* The SFC can transfer max 16KB - 1 at one time 156 * we set it to 15.5KB here for alignment. 157 */ 158 #define SFC_MAX_IOSIZE_VER3 (512 * 31) 159 160 #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU) 161 162 /* DMA is only enabled for large data transmission */ 163 #define SFC_DMA_TRANS_THRETHOLD (0x40) 164 165 /* Maximum clock values from datasheet suggest keeping clock value under 166 * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver 167 * has a minimum of 10MHz and a default of 80MHz which seems reasonable. 168 */ 169 #define SFC_MIN_SPEED_HZ (10 * 1000 * 1000) 170 #define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000) 171 #define SFC_MAX_SPEED_HZ (150 * 1000 * 1000) 172 173 struct rockchip_sfc { 174 void __iomem *regbase; 175 struct clk hclk; 176 struct clk clk; 177 u32 max_freq; 178 u32 speed; 179 bool use_dma; 180 u32 max_iosize; 181 u16 version; 182 }; 183 184 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 185 { 186 int err; 187 u32 status; 188 189 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); 190 191 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, 192 !(status & SFC_RCVR_RESET), 193 1000000); 194 if (err) 195 printf("SFC reset never finished\n"); 196 197 /* Still need to clear the masked interrupt from RISR */ 198 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 199 200 debug("reset\n"); 201 202 return err; 203 } 204 205 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 206 { 207 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); 208 } 209 210 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) 211 { 212 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 213 return SFC_MAX_IOSIZE_VER4; 214 215 return SFC_MAX_IOSIZE_VER3; 216 } 217 218 static int rockchip_sfc_init(struct rockchip_sfc *sfc) 219 { 220 writel(0, sfc->regbase + SFC_CTRL); 221 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 222 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); 223 224 return 0; 225 } 226 227 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 228 { 229 struct rockchip_sfc *sfc = dev_get_platdata(bus); 230 231 sfc->regbase = dev_read_addr_ptr(bus); 232 if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) 233 sfc->use_dma = false; 234 else 235 sfc->use_dma = true; 236 237 #if CONFIG_IS_ENABLED(CLK) 238 int ret; 239 240 ret = clk_get_by_index(bus, 0, &sfc->clk); 241 if (ret < 0) { 242 printf("Could not get clock for %s: %d\n", bus->name, ret); 243 return ret; 244 } 245 246 ret = clk_get_by_index(bus, 1, &sfc->hclk); 247 if (ret < 0) { 248 printf("Could not get ahb clock for %s: %d\n", bus->name, ret); 249 return ret; 250 } 251 #endif 252 253 return 0; 254 } 255 256 static int rockchip_sfc_probe(struct udevice *bus) 257 { 258 struct rockchip_sfc *sfc = dev_get_platdata(bus); 259 int ret; 260 261 #if CONFIG_IS_ENABLED(CLK) 262 ret = clk_enable(&sfc->hclk); 263 if (ret) 264 debug("Enable ahb clock fail %s: %d\n", bus->name, ret); 265 266 ret = clk_enable(&sfc->clk); 267 if (ret) 268 debug("Enable clock fail for %s: %d\n", bus->name, ret); 269 270 ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ); 271 if (ret) 272 debug("Could not set sfc clock for %s: %d\n", bus->name, ret); 273 #endif 274 275 ret = rockchip_sfc_init(sfc); 276 if (ret) 277 goto err_init; 278 279 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); 280 sfc->version = rockchip_sfc_get_version(sfc); 281 sfc->speed = SFC_DEFAULT_SPEED_HZ; 282 283 return 0; 284 285 err_init: 286 #if CONFIG_IS_ENABLED(CLK) 287 clk_disable(&sfc->clk); 288 clk_disable(&sfc->hclk); 289 #endif 290 291 return ret; 292 } 293 294 static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr) 295 { 296 u32 fsr = readl(sfc->regbase + SFC_FSR); 297 int level; 298 299 if (wr) 300 level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; 301 else 302 level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; 303 304 return level; 305 } 306 307 static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout) 308 { 309 unsigned long tbase = get_timer(0); 310 int level; 311 312 while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) { 313 if (get_timer(tbase) > timeout) { 314 debug("%s fifo timeout\n", wr ? "write" : "read"); 315 return -ETIMEDOUT; 316 } 317 udelay(1); 318 } 319 320 return level; 321 } 322 323 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) 324 { 325 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { 326 /* 327 * SFC not support output DUMMY cycles right after CMD cycles, so 328 * treat it as ADDR cycles. 329 */ 330 op->addr.nbytes = op->dummy.nbytes; 331 op->addr.buswidth = op->dummy.buswidth; 332 op->addr.val = 0xFFFFFFFFF; 333 334 op->dummy.nbytes = 0; 335 } 336 } 337 338 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) 339 { 340 unsigned long tbase; 341 342 /* Wait for the DMA interrupt status */ 343 tbase = get_timer(0); 344 while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { 345 if (get_timer(tbase) > timeout) { 346 printf("dma timeout\n"); 347 rockchip_sfc_reset(sfc); 348 349 return -ETIMEDOUT; 350 } 351 352 udelay(1); 353 } 354 355 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 356 357 return 0; 358 } 359 360 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, 361 struct spi_slave *mem, 362 const struct spi_mem_op *op, 363 u32 len) 364 { 365 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 366 u32 ctrl = 0, cmd = 0; 367 368 /* set CMD */ 369 cmd = op->cmd.opcode; 370 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); 371 372 /* set ADDR */ 373 if (op->addr.nbytes) { 374 if (op->addr.nbytes == 4) { 375 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; 376 } else if (op->addr.nbytes == 3) { 377 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; 378 } else { 379 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; 380 writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); 381 } 382 383 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); 384 } 385 386 /* set DUMMY */ 387 if (op->dummy.nbytes) { 388 if (op->dummy.buswidth == 4) 389 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; 390 else if (op->dummy.buswidth == 2) 391 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; 392 else 393 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; 394 } 395 396 /* set DATA */ 397 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ 398 writel(len, sfc->regbase + SFC_LEN_EXT); 399 else 400 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; 401 if (len) { 402 if (op->data.dir == SPI_MEM_DATA_OUT) 403 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 404 405 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); 406 } 407 if (!len && op->addr.nbytes) 408 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 409 410 /* set the Controller */ 411 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; 412 cmd |= plat->cs << SFC_CMD_CS_SHIFT; 413 414 debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", 415 op->addr.nbytes, op->addr.buswidth, 416 op->dummy.nbytes, op->dummy.buswidth); 417 debug("ctrl=%x cmd=%x addr=%llx len=%x\n", 418 ctrl, cmd, op->addr.val, len); 419 420 writel(ctrl, sfc->regbase + SFC_CTRL); 421 writel(cmd, sfc->regbase + SFC_CMD); 422 if (op->addr.nbytes) 423 writel(op->addr.val, sfc->regbase + SFC_ADDR); 424 425 return 0; 426 } 427 428 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) 429 { 430 u8 bytes = len & 0x3; 431 u32 dwords; 432 int tx_level; 433 u32 write_words; 434 u32 tmp = 0; 435 436 dwords = len >> 2; 437 while (dwords) { 438 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000); 439 if (tx_level < 0) 440 return tx_level; 441 write_words = min_t(u32, tx_level, dwords); 442 writesl(sfc->regbase + SFC_DATA, buf, write_words); 443 buf += write_words << 2; 444 dwords -= write_words; 445 } 446 447 /* write the rest non word aligned bytes */ 448 if (bytes) { 449 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000); 450 if (tx_level < 0) 451 return tx_level; 452 memcpy(&tmp, buf, bytes); 453 writel(tmp, sfc->regbase + SFC_DATA); 454 } 455 456 return len; 457 } 458 459 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) 460 { 461 u8 bytes = len & 0x3; 462 u32 dwords; 463 u8 read_words; 464 int rx_level; 465 int tmp; 466 467 /* word aligned access only */ 468 dwords = len >> 2; 469 while (dwords) { 470 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000); 471 if (rx_level < 0) 472 return rx_level; 473 read_words = min_t(u32, rx_level, dwords); 474 readsl(sfc->regbase + SFC_DATA, buf, read_words); 475 buf += read_words << 2; 476 dwords -= read_words; 477 } 478 479 /* read the rest non word aligned bytes */ 480 if (bytes) { 481 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000); 482 if (rx_level < 0) 483 return rx_level; 484 tmp = readl(sfc->regbase + SFC_DATA); 485 memcpy(buf, &tmp, bytes); 486 } 487 488 return len; 489 } 490 491 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) 492 { 493 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 494 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); 495 writel(0x1, sfc->regbase + SFC_DMA_TRIGGER); 496 497 return len; 498 } 499 500 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, 501 const struct spi_mem_op *op, u32 len) 502 { 503 debug("xfer_poll len=%x\n", len); 504 505 if (op->data.dir == SPI_MEM_DATA_OUT) 506 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); 507 else 508 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); 509 } 510 511 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, 512 const struct spi_mem_op *op, u32 len) 513 { 514 struct bounce_buffer bb; 515 unsigned int bb_flags; 516 void *dma_buf; 517 int ret; 518 519 debug("xfer_dma len=%x\n", len); 520 521 if (op->data.dir == SPI_MEM_DATA_OUT) { 522 dma_buf = (void *)op->data.buf.out; 523 bb_flags = GEN_BB_READ; 524 } else { 525 dma_buf = (void *)op->data.buf.in; 526 bb_flags = GEN_BB_WRITE; 527 } 528 529 ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags); 530 if (ret) 531 return ret; 532 533 ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); 534 rockchip_sfc_wait_for_dma_finished(sfc, len * 10); 535 bounce_buffer_stop(&bb); 536 537 return ret; 538 } 539 540 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) 541 { 542 unsigned long tbase = get_timer(0); 543 int ret = 0; 544 u32 timeout = timeout_us; 545 546 while (readl(sfc->regbase + SFC_SR) & SFC_SR_IS_BUSY) { 547 if (get_timer(tbase) > timeout) { 548 printf("wait sfc idle timeout\n"); 549 rockchip_sfc_reset(sfc); 550 551 return -ETIMEDOUT; 552 } 553 554 udelay(1); 555 } 556 557 return ret; 558 } 559 560 static int rockchip_sfc_exec_op(struct spi_slave *mem, 561 const struct spi_mem_op *op) 562 { 563 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 564 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 565 int ret; 566 567 #if CONFIG_IS_ENABLED(CLK) 568 if (unlikely(mem->max_hz != sfc->speed)) { 569 ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ, 570 (uint)SFC_MAX_SPEED_HZ)); 571 if (ret < 0) { 572 printf("set_freq=%dHz fail, check if it's the cru support level\n", 573 mem->max_hz); 574 return ret; 575 } 576 577 sfc->max_freq = mem->max_hz; 578 sfc->speed = mem->max_hz; 579 debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed); 580 } 581 #endif 582 583 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 584 585 rockchip_sfc_xfer_setup(sfc, mem, op, len); 586 if (len) { 587 if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD) 588 ret = rockchip_sfc_xfer_data_dma(sfc, op, len); 589 else 590 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 591 592 if (ret != len) { 593 printf("xfer data failed ret %d dir %d\n", ret, op->data.dir); 594 595 return -EIO; 596 } 597 } 598 599 return rockchip_sfc_xfer_done(sfc, 100000); 600 } 601 602 static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op) 603 { 604 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 605 606 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); 607 return 0; 608 } 609 610 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 611 { 612 /* We set up speed later for each transmission. 613 */ 614 return 0; 615 } 616 617 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 618 { 619 return 0; 620 } 621 622 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { 623 .adjust_op_size = rockchip_sfc_adjust_op_size, 624 .exec_op = rockchip_sfc_exec_op, 625 }; 626 627 static const struct dm_spi_ops rockchip_sfc_ops = { 628 .mem_ops = &rockchip_sfc_mem_ops, 629 .set_speed = rockchip_sfc_set_speed, 630 .set_mode = rockchip_sfc_set_mode, 631 }; 632 633 static const struct udevice_id rockchip_sfc_ids[] = { 634 { .compatible = "rockchip,sfc"}, 635 {}, 636 }; 637 638 U_BOOT_DRIVER(rockchip_sfc_driver) = { 639 .name = "rockchip_sfc", 640 .id = UCLASS_SPI, 641 .of_match = rockchip_sfc_ids, 642 .ops = &rockchip_sfc_ops, 643 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 644 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc), 645 .probe = rockchip_sfc_probe, 646 }; 647