1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Serial Flash Controller Driver 4 * 5 * Copyright (c) 2017-2021, Rockchip Inc. 6 * Author: Shawn Lin <shawn.lin@rock-chips.com> 7 * Chris Morgan <macromorgan@hotmail.com> 8 * Jon Lin <Jon.lin@rock-chips.com> 9 */ 10 11 #include <asm/io.h> 12 #include <bouncebuf.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <linux/bitops.h> 16 #include <linux/delay.h> 17 #include <linux/iopoll.h> 18 #include <spi.h> 19 #include <spi-mem.h> 20 21 /* System control */ 22 #define SFC_CTRL 0x0 23 #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) 24 #define SFC_CTRL_CMD_BITS_SHIFT 8 25 #define SFC_CTRL_ADDR_BITS_SHIFT 10 26 #define SFC_CTRL_DATA_BITS_SHIFT 12 27 28 /* Interrupt mask */ 29 #define SFC_IMR 0x4 30 #define SFC_IMR_RX_FULL BIT(0) 31 #define SFC_IMR_RX_UFLOW BIT(1) 32 #define SFC_IMR_TX_OFLOW BIT(2) 33 #define SFC_IMR_TX_EMPTY BIT(3) 34 #define SFC_IMR_TRAN_FINISH BIT(4) 35 #define SFC_IMR_BUS_ERR BIT(5) 36 #define SFC_IMR_NSPI_ERR BIT(6) 37 #define SFC_IMR_DMA BIT(7) 38 39 /* Interrupt clear */ 40 #define SFC_ICLR 0x8 41 #define SFC_ICLR_RX_FULL BIT(0) 42 #define SFC_ICLR_RX_UFLOW BIT(1) 43 #define SFC_ICLR_TX_OFLOW BIT(2) 44 #define SFC_ICLR_TX_EMPTY BIT(3) 45 #define SFC_ICLR_TRAN_FINISH BIT(4) 46 #define SFC_ICLR_BUS_ERR BIT(5) 47 #define SFC_ICLR_NSPI_ERR BIT(6) 48 #define SFC_ICLR_DMA BIT(7) 49 50 /* FIFO threshold level */ 51 #define SFC_FTLR 0xc 52 #define SFC_FTLR_TX_SHIFT 0 53 #define SFC_FTLR_TX_MASK 0x1f 54 #define SFC_FTLR_RX_SHIFT 8 55 #define SFC_FTLR_RX_MASK 0x1f 56 57 /* Reset FSM and FIFO */ 58 #define SFC_RCVR 0x10 59 #define SFC_RCVR_RESET BIT(0) 60 61 /* Enhanced mode */ 62 #define SFC_AX 0x14 63 64 /* Address Bit number */ 65 #define SFC_ABIT 0x18 66 67 /* Interrupt status */ 68 #define SFC_ISR 0x1c 69 #define SFC_ISR_RX_FULL_SHIFT BIT(0) 70 #define SFC_ISR_RX_UFLOW_SHIFT BIT(1) 71 #define SFC_ISR_TX_OFLOW_SHIFT BIT(2) 72 #define SFC_ISR_TX_EMPTY_SHIFT BIT(3) 73 #define SFC_ISR_TX_FINISH_SHIFT BIT(4) 74 #define SFC_ISR_BUS_ERR_SHIFT BIT(5) 75 #define SFC_ISR_NSPI_ERR_SHIFT BIT(6) 76 #define SFC_ISR_DMA_SHIFT BIT(7) 77 78 /* FIFO status */ 79 #define SFC_FSR 0x20 80 #define SFC_FSR_TX_IS_FULL BIT(0) 81 #define SFC_FSR_TX_IS_EMPTY BIT(1) 82 #define SFC_FSR_RX_IS_EMPTY BIT(2) 83 #define SFC_FSR_RX_IS_FULL BIT(3) 84 #define SFC_FSR_TXLV_MASK GENMASK(12, 8) 85 #define SFC_FSR_TXLV_SHIFT 8 86 #define SFC_FSR_RXLV_MASK GENMASK(20, 16) 87 #define SFC_FSR_RXLV_SHIFT 16 88 89 /* FSM status */ 90 #define SFC_SR 0x24 91 #define SFC_SR_IS_IDLE 0x0 92 #define SFC_SR_IS_BUSY 0x1 93 94 /* Raw interrupt status */ 95 #define SFC_RISR 0x28 96 #define SFC_RISR_RX_FULL BIT(0) 97 #define SFC_RISR_RX_UNDERFLOW BIT(1) 98 #define SFC_RISR_TX_OVERFLOW BIT(2) 99 #define SFC_RISR_TX_EMPTY BIT(3) 100 #define SFC_RISR_TRAN_FINISH BIT(4) 101 #define SFC_RISR_BUS_ERR BIT(5) 102 #define SFC_RISR_NSPI_ERR BIT(6) 103 #define SFC_RISR_DMA BIT(7) 104 105 /* Version */ 106 #define SFC_VER 0x2C 107 #define SFC_VER_3 0x3 108 #define SFC_VER_4 0x4 109 #define SFC_VER_5 0x5 110 111 /* Delay line controller resiter */ 112 #define SFC_DLL_CTRL0 0x3C 113 #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) 114 #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU 115 #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU 116 117 /* Master trigger */ 118 #define SFC_DMA_TRIGGER 0x80 119 #define SFC_DMA_TRIGGER_START 1 120 121 /* Src or Dst addr for master */ 122 #define SFC_DMA_ADDR 0x84 123 124 /* Length control register extension 32GB */ 125 #define SFC_LEN_CTRL 0x88 126 #define SFC_LEN_CTRL_TRB_SEL 1 127 #define SFC_LEN_EXT 0x8C 128 129 /* Command */ 130 #define SFC_CMD 0x100 131 #define SFC_CMD_IDX_SHIFT 0 132 #define SFC_CMD_DUMMY_SHIFT 8 133 #define SFC_CMD_DIR_SHIFT 12 134 #define SFC_CMD_DIR_RD 0 135 #define SFC_CMD_DIR_WR 1 136 #define SFC_CMD_ADDR_SHIFT 14 137 #define SFC_CMD_ADDR_0BITS 0 138 #define SFC_CMD_ADDR_24BITS 1 139 #define SFC_CMD_ADDR_32BITS 2 140 #define SFC_CMD_ADDR_XBITS 3 141 #define SFC_CMD_TRAN_BYTES_SHIFT 16 142 #define SFC_CMD_CS_SHIFT 30 143 144 /* Address */ 145 #define SFC_ADDR 0x104 146 147 /* Data */ 148 #define SFC_DATA 0x108 149 150 /* The controller and documentation reports that it supports up to 4 CS 151 * devices (0-3), however I have only been able to test a single CS (CS 0) 152 * due to the configuration of my device. 153 */ 154 #define SFC_MAX_CHIPSELECT_NUM 4 155 156 /* The SFC can transfer max 16KB - 1 at one time 157 * we set it to 15.5KB here for alignment. 158 */ 159 #define SFC_MAX_IOSIZE_VER3 (512 * 31) 160 161 #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU) 162 163 /* DMA is only enabled for large data transmission */ 164 #define SFC_DMA_TRANS_THRETHOLD (0x40) 165 166 /* Maximum clock values from datasheet suggest keeping clock value under 167 * 150MHz. No minimum or average value is suggested. 168 */ 169 #define SFC_MAX_SPEED (150 * 1000 * 1000) 170 171 struct rockchip_sfc { 172 struct udevice *dev; 173 void __iomem *regbase; 174 struct clk hclk; 175 struct clk clk; 176 u32 max_freq; 177 u32 speed; 178 bool use_dma; 179 u32 max_iosize; 180 u16 version; 181 }; 182 183 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 184 { 185 int err; 186 u32 status; 187 188 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); 189 190 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, 191 !(status & SFC_RCVR_RESET), 192 1000000); 193 if (err) 194 printf("SFC reset never finished\n"); 195 196 /* Still need to clear the masked interrupt from RISR */ 197 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 198 199 return err; 200 } 201 202 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 203 { 204 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); 205 } 206 207 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) 208 { 209 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 210 return SFC_MAX_IOSIZE_VER4; 211 212 return SFC_MAX_IOSIZE_VER3; 213 } 214 215 static int rockchip_sfc_init(struct rockchip_sfc *sfc) 216 { 217 writel(0, sfc->regbase + SFC_CTRL); 218 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 219 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); 220 221 return 0; 222 } 223 224 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 225 { 226 struct rockchip_sfc *sfc = dev_get_platdata(bus); 227 228 sfc->regbase = dev_read_addr_ptr(bus); 229 if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) 230 sfc->use_dma = false; 231 else 232 sfc->use_dma = true; 233 234 #if CONFIG_IS_ENABLED(CLK) 235 int ret; 236 237 ret = clk_get_by_index(bus, 0, &sfc->clk); 238 if (ret < 0) { 239 printf("Could not get clock for %s: %d\n", bus->name, ret); 240 return ret; 241 } 242 243 ret = clk_get_by_index(bus, 1, &sfc->hclk); 244 if (ret < 0) { 245 printf("Could not get ahb clock for %s: %d\n", bus->name, ret); 246 return ret; 247 } 248 #endif 249 250 return 0; 251 } 252 253 static int rockchip_sfc_probe(struct udevice *bus) 254 { 255 struct rockchip_sfc *sfc = dev_get_platdata(bus); 256 int ret; 257 258 #if CONFIG_IS_ENABLED(CLK) 259 ret = clk_enable(&sfc->hclk); 260 if (ret) 261 dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); 262 263 ret = clk_enable(&sfc->clk); 264 if (ret) 265 dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); 266 #endif 267 268 ret = rockchip_sfc_init(sfc); 269 if (ret) 270 goto err_init; 271 272 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); 273 sfc->version = rockchip_sfc_get_version(sfc); 274 sfc->max_freq = SFC_MAX_SPEED; 275 sfc->dev = bus; 276 277 return 0; 278 279 err_init: 280 #if CONFIG_IS_ENABLED(CLK) 281 clk_disable(&sfc->clk); 282 clk_disable(&sfc->hclk); 283 #endif 284 285 return ret; 286 } 287 288 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 289 { 290 int ret = 0; 291 u32 status; 292 293 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 294 status & SFC_FSR_TXLV_MASK, 295 timeout_us); 296 if (ret) { 297 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); 298 299 return -ETIMEDOUT; 300 } 301 302 return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; 303 } 304 305 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 306 { 307 int ret = 0; 308 u32 status; 309 310 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 311 status & SFC_FSR_RXLV_MASK, 312 timeout_us); 313 if (ret) { 314 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); 315 316 return -ETIMEDOUT; 317 } 318 319 return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; 320 } 321 322 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) 323 { 324 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { 325 /* 326 * SFC not support output DUMMY cycles right after CMD cycles, so 327 * treat it as ADDR cycles. 328 */ 329 op->addr.nbytes = op->dummy.nbytes; 330 op->addr.buswidth = op->dummy.buswidth; 331 op->addr.val = 0xFFFFFFFFF; 332 333 op->dummy.nbytes = 0; 334 } 335 } 336 337 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) 338 { 339 unsigned long tbase; 340 341 /* Wait for the DMA interrupt status */ 342 tbase = get_timer(0); 343 while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { 344 if (get_timer(tbase) > timeout) { 345 printf("dma timeout\n"); 346 rockchip_sfc_reset(sfc); 347 348 return -ETIMEDOUT; 349 } 350 351 udelay(1); 352 } 353 354 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 355 356 return 0; 357 } 358 359 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, 360 struct spi_slave *mem, 361 const struct spi_mem_op *op, 362 u32 len) 363 { 364 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 365 u32 ctrl = 0, cmd = 0; 366 367 /* set CMD */ 368 cmd = op->cmd.opcode; 369 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); 370 371 /* set ADDR */ 372 if (op->addr.nbytes) { 373 if (op->addr.nbytes == 4) { 374 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; 375 } else if (op->addr.nbytes == 3) { 376 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; 377 } else { 378 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; 379 writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); 380 } 381 382 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); 383 } 384 385 /* set DUMMY */ 386 if (op->dummy.nbytes) { 387 if (op->dummy.buswidth == 4) 388 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; 389 else if (op->dummy.buswidth == 2) 390 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; 391 else 392 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; 393 } 394 395 /* set DATA */ 396 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ 397 writel(len, sfc->regbase + SFC_LEN_EXT); 398 else 399 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; 400 if (len) { 401 if (op->data.dir == SPI_MEM_DATA_OUT) 402 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 403 404 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); 405 } 406 if (!len && op->addr.nbytes) 407 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 408 409 /* set the Controller */ 410 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; 411 cmd |= plat->cs << SFC_CMD_CS_SHIFT; 412 413 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", 414 op->addr.nbytes, op->addr.buswidth, 415 op->dummy.nbytes, op->dummy.buswidth); 416 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", 417 ctrl, cmd, op->addr.val, len); 418 419 writel(ctrl, sfc->regbase + SFC_CTRL); 420 writel(cmd, sfc->regbase + SFC_CMD); 421 if (op->addr.nbytes) 422 writel(op->addr.val, sfc->regbase + SFC_ADDR); 423 424 return 0; 425 } 426 427 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) 428 { 429 u8 bytes = len & 0x3; 430 u32 dwords; 431 int tx_level; 432 u32 write_words; 433 u32 tmp = 0; 434 435 dwords = len >> 2; 436 while (dwords) { 437 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 438 if (tx_level < 0) 439 return tx_level; 440 write_words = min_t(u32, tx_level, dwords); 441 writesl(sfc->regbase + SFC_DATA, buf, write_words); 442 buf += write_words << 2; 443 dwords -= write_words; 444 } 445 446 /* write the rest non word aligned bytes */ 447 if (bytes) { 448 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 449 if (tx_level < 0) 450 return tx_level; 451 memcpy(&tmp, buf, bytes); 452 writel(tmp, sfc->regbase + SFC_DATA); 453 } 454 455 return len; 456 } 457 458 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) 459 { 460 u8 bytes = len & 0x3; 461 u32 dwords; 462 u8 read_words; 463 int rx_level; 464 int tmp; 465 466 /* word aligned access only */ 467 dwords = len >> 2; 468 while (dwords) { 469 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 470 if (rx_level < 0) 471 return rx_level; 472 read_words = min_t(u32, rx_level, dwords); 473 readsl(sfc->regbase + SFC_DATA, buf, read_words); 474 buf += read_words << 2; 475 dwords -= read_words; 476 } 477 478 /* read the rest non word aligned bytes */ 479 if (bytes) { 480 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 481 if (rx_level < 0) 482 return rx_level; 483 tmp = readl(sfc->regbase + SFC_DATA); 484 memcpy(buf, &tmp, bytes); 485 } 486 487 return len; 488 } 489 490 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) 491 { 492 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 493 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); 494 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); 495 496 return len; 497 } 498 499 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, 500 const struct spi_mem_op *op, u32 len) 501 { 502 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); 503 504 if (op->data.dir == SPI_MEM_DATA_OUT) 505 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); 506 else 507 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); 508 } 509 510 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, 511 const struct spi_mem_op *op, u32 len) 512 { 513 struct bounce_buffer bb; 514 unsigned int bb_flags; 515 void *dma_buf; 516 int ret; 517 518 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); 519 520 if (op->data.dir == SPI_MEM_DATA_OUT) { 521 dma_buf = (void *)op->data.buf.out; 522 bb_flags = GEN_BB_READ; 523 } else { 524 dma_buf = (void *)op->data.buf.in; 525 bb_flags = GEN_BB_WRITE; 526 } 527 528 ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags); 529 if (ret) 530 return ret; 531 532 ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); 533 rockchip_sfc_wait_for_dma_finished(sfc, len * 10); 534 bounce_buffer_stop(&bb); 535 536 return ret; 537 } 538 539 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) 540 { 541 int ret = 0; 542 u32 status; 543 544 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, 545 !(status & SFC_SR_IS_BUSY), 546 timeout_us); 547 if (ret) { 548 dev_err(sfc->dev, "wait sfc idle timeout\n"); 549 rockchip_sfc_reset(sfc); 550 551 ret = -EIO; 552 } 553 554 return ret; 555 } 556 557 static int rockchip_sfc_exec_op(struct spi_slave *mem, 558 const struct spi_mem_op *op) 559 { 560 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 561 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 562 int ret; 563 564 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 565 rockchip_sfc_xfer_setup(sfc, mem, op, len); 566 if (len) { 567 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) 568 ret = rockchip_sfc_xfer_data_dma(sfc, op, len); 569 else 570 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 571 572 if (ret != len) { 573 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); 574 575 return -EIO; 576 } 577 } 578 579 return rockchip_sfc_xfer_done(sfc, 100000); 580 } 581 582 static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op) 583 { 584 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 585 586 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); 587 588 return 0; 589 } 590 591 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 592 { 593 struct rockchip_sfc *sfc = dev_get_platdata(bus); 594 595 if (speed > sfc->max_freq) 596 speed = sfc->max_freq; 597 598 if (speed == sfc->speed) 599 return 0; 600 601 #if CONFIG_IS_ENABLED(CLK) 602 int ret = clk_set_rate(&sfc->clk, speed); 603 604 if (ret < 0) { 605 dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", 606 speed); 607 return ret; 608 } 609 sfc->speed = speed; 610 #else 611 dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); 612 #endif 613 return 0; 614 } 615 616 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 617 { 618 return 0; 619 } 620 621 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { 622 .adjust_op_size = rockchip_sfc_adjust_op_size, 623 .exec_op = rockchip_sfc_exec_op, 624 }; 625 626 static const struct dm_spi_ops rockchip_sfc_ops = { 627 .mem_ops = &rockchip_sfc_mem_ops, 628 .set_speed = rockchip_sfc_set_speed, 629 .set_mode = rockchip_sfc_set_mode, 630 }; 631 632 static const struct udevice_id rockchip_sfc_ids[] = { 633 { .compatible = "rockchip,sfc"}, 634 {}, 635 }; 636 637 U_BOOT_DRIVER(rockchip_sfc_driver) = { 638 .name = "rockchip_sfc", 639 .id = UCLASS_SPI, 640 .of_match = rockchip_sfc_ids, 641 .ops = &rockchip_sfc_ops, 642 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 643 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc), 644 .probe = rockchip_sfc_probe, 645 }; 646