1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Serial Flash Controller Driver 4 * 5 * Copyright (c) 2017-2021, Rockchip Inc. 6 * Author: Shawn Lin <shawn.lin@rock-chips.com> 7 * Chris Morgan <macromorgan@hotmail.com> 8 * Jon Lin <Jon.lin@rock-chips.com> 9 */ 10 11 #include <asm/io.h> 12 #include <bouncebuf.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <linux/bitops.h> 16 #include <linux/delay.h> 17 #include <linux/iopoll.h> 18 #include <spi.h> 19 #include <spi-mem.h> 20 21 /* System control */ 22 #define SFC_CTRL 0x0 23 #define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) 24 #define SFC_CTRL_CMD_BITS_SHIFT 8 25 #define SFC_CTRL_ADDR_BITS_SHIFT 10 26 #define SFC_CTRL_DATA_BITS_SHIFT 12 27 28 /* Interrupt mask */ 29 #define SFC_IMR 0x4 30 #define SFC_IMR_RX_FULL BIT(0) 31 #define SFC_IMR_RX_UFLOW BIT(1) 32 #define SFC_IMR_TX_OFLOW BIT(2) 33 #define SFC_IMR_TX_EMPTY BIT(3) 34 #define SFC_IMR_TRAN_FINISH BIT(4) 35 #define SFC_IMR_BUS_ERR BIT(5) 36 #define SFC_IMR_NSPI_ERR BIT(6) 37 #define SFC_IMR_DMA BIT(7) 38 39 /* Interrupt clear */ 40 #define SFC_ICLR 0x8 41 #define SFC_ICLR_RX_FULL BIT(0) 42 #define SFC_ICLR_RX_UFLOW BIT(1) 43 #define SFC_ICLR_TX_OFLOW BIT(2) 44 #define SFC_ICLR_TX_EMPTY BIT(3) 45 #define SFC_ICLR_TRAN_FINISH BIT(4) 46 #define SFC_ICLR_BUS_ERR BIT(5) 47 #define SFC_ICLR_NSPI_ERR BIT(6) 48 #define SFC_ICLR_DMA BIT(7) 49 50 /* FIFO threshold level */ 51 #define SFC_FTLR 0xc 52 #define SFC_FTLR_TX_SHIFT 0 53 #define SFC_FTLR_TX_MASK 0x1f 54 #define SFC_FTLR_RX_SHIFT 8 55 #define SFC_FTLR_RX_MASK 0x1f 56 57 /* Reset FSM and FIFO */ 58 #define SFC_RCVR 0x10 59 #define SFC_RCVR_RESET BIT(0) 60 61 /* Enhanced mode */ 62 #define SFC_AX 0x14 63 64 /* Address Bit number */ 65 #define SFC_ABIT 0x18 66 67 /* Interrupt status */ 68 #define SFC_ISR 0x1c 69 #define SFC_ISR_RX_FULL_SHIFT BIT(0) 70 #define SFC_ISR_RX_UFLOW_SHIFT BIT(1) 71 #define SFC_ISR_TX_OFLOW_SHIFT BIT(2) 72 #define SFC_ISR_TX_EMPTY_SHIFT BIT(3) 73 #define SFC_ISR_TX_FINISH_SHIFT BIT(4) 74 #define SFC_ISR_BUS_ERR_SHIFT BIT(5) 75 #define SFC_ISR_NSPI_ERR_SHIFT BIT(6) 76 #define SFC_ISR_DMA_SHIFT BIT(7) 77 78 /* FIFO status */ 79 #define SFC_FSR 0x20 80 #define SFC_FSR_TX_IS_FULL BIT(0) 81 #define SFC_FSR_TX_IS_EMPTY BIT(1) 82 #define SFC_FSR_RX_IS_EMPTY BIT(2) 83 #define SFC_FSR_RX_IS_FULL BIT(3) 84 #define SFC_FSR_TXLV_MASK GENMASK(12, 8) 85 #define SFC_FSR_TXLV_SHIFT 8 86 #define SFC_FSR_RXLV_MASK GENMASK(20, 16) 87 #define SFC_FSR_RXLV_SHIFT 16 88 89 /* FSM status */ 90 #define SFC_SR 0x24 91 #define SFC_SR_IS_IDLE 0x0 92 #define SFC_SR_IS_BUSY 0x1 93 94 /* Raw interrupt status */ 95 #define SFC_RISR 0x28 96 #define SFC_RISR_RX_FULL BIT(0) 97 #define SFC_RISR_RX_UNDERFLOW BIT(1) 98 #define SFC_RISR_TX_OVERFLOW BIT(2) 99 #define SFC_RISR_TX_EMPTY BIT(3) 100 #define SFC_RISR_TRAN_FINISH BIT(4) 101 #define SFC_RISR_BUS_ERR BIT(5) 102 #define SFC_RISR_NSPI_ERR BIT(6) 103 #define SFC_RISR_DMA BIT(7) 104 105 /* Version */ 106 #define SFC_VER 0x2C 107 #define SFC_VER_3 0x3 108 #define SFC_VER_4 0x4 109 #define SFC_VER_5 0x5 110 111 /* Delay line controller resiter */ 112 #define SFC_DLL_CTRL0 0x3C 113 #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) 114 #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU 115 #define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU 116 117 /* Master trigger */ 118 #define SFC_DMA_TRIGGER 0x80 119 #define SFC_DMA_TRIGGER_START 1 120 121 /* Src or Dst addr for master */ 122 #define SFC_DMA_ADDR 0x84 123 124 /* Length control register extension 32GB */ 125 #define SFC_LEN_CTRL 0x88 126 #define SFC_LEN_CTRL_TRB_SEL 1 127 #define SFC_LEN_EXT 0x8C 128 129 /* Command */ 130 #define SFC_CMD 0x100 131 #define SFC_CMD_IDX_SHIFT 0 132 #define SFC_CMD_DUMMY_SHIFT 8 133 #define SFC_CMD_DIR_SHIFT 12 134 #define SFC_CMD_DIR_RD 0 135 #define SFC_CMD_DIR_WR 1 136 #define SFC_CMD_ADDR_SHIFT 14 137 #define SFC_CMD_ADDR_0BITS 0 138 #define SFC_CMD_ADDR_24BITS 1 139 #define SFC_CMD_ADDR_32BITS 2 140 #define SFC_CMD_ADDR_XBITS 3 141 #define SFC_CMD_TRAN_BYTES_SHIFT 16 142 #define SFC_CMD_CS_SHIFT 30 143 144 /* Address */ 145 #define SFC_ADDR 0x104 146 147 /* Data */ 148 #define SFC_DATA 0x108 149 150 /* The controller and documentation reports that it supports up to 4 CS 151 * devices (0-3), however I have only been able to test a single CS (CS 0) 152 * due to the configuration of my device. 153 */ 154 #define SFC_MAX_CHIPSELECT_NUM 4 155 156 /* The SFC can transfer max 16KB - 1 at one time 157 * we set it to 15.5KB here for alignment. 158 */ 159 #define SFC_MAX_IOSIZE_VER3 (512 * 31) 160 161 #define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU) 162 163 /* DMA is only enabled for large data transmission */ 164 #define SFC_DMA_TRANS_THRETHOLD (0x40) 165 166 /* Maximum clock values from datasheet suggest keeping clock value under 167 * 150MHz. No minimum or average value is suggested. 168 */ 169 #define SFC_MAX_SPEED (150 * 1000 * 1000) 170 171 struct rockchip_sfc { 172 struct udevice *dev; 173 void __iomem *regbase; 174 struct clk hclk; 175 struct clk clk; 176 u32 max_freq; 177 u32 speed; 178 bool use_dma; 179 u32 max_iosize; 180 u16 version; 181 182 u32 last_async_size; 183 u32 async; 184 }; 185 186 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 187 { 188 int err; 189 u32 status; 190 191 writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); 192 193 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, 194 !(status & SFC_RCVR_RESET), 195 1000000); 196 if (err) 197 printf("SFC reset never finished\n"); 198 199 /* Still need to clear the masked interrupt from RISR */ 200 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 201 202 return err; 203 } 204 205 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 206 { 207 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); 208 } 209 210 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) 211 { 212 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 213 return SFC_MAX_IOSIZE_VER4; 214 215 return SFC_MAX_IOSIZE_VER3; 216 } 217 218 static int rockchip_sfc_init(struct rockchip_sfc *sfc) 219 { 220 writel(0, sfc->regbase + SFC_CTRL); 221 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 222 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); 223 224 return 0; 225 } 226 227 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 228 { 229 struct rockchip_sfc *sfc = dev_get_platdata(bus); 230 231 sfc->regbase = dev_read_addr_ptr(bus); 232 if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma")) 233 sfc->use_dma = false; 234 else 235 sfc->use_dma = true; 236 237 #if CONFIG_IS_ENABLED(CLK) 238 int ret; 239 240 ret = clk_get_by_index(bus, 0, &sfc->clk); 241 if (ret < 0) { 242 printf("Could not get clock for %s: %d\n", bus->name, ret); 243 return ret; 244 } 245 246 ret = clk_get_by_index(bus, 1, &sfc->hclk); 247 if (ret < 0) { 248 printf("Could not get ahb clock for %s: %d\n", bus->name, ret); 249 return ret; 250 } 251 #endif 252 253 return 0; 254 } 255 256 static int rockchip_sfc_probe(struct udevice *bus) 257 { 258 struct rockchip_sfc *sfc = dev_get_platdata(bus); 259 int ret; 260 261 #if CONFIG_IS_ENABLED(CLK) 262 ret = clk_enable(&sfc->hclk); 263 if (ret) 264 dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); 265 266 ret = clk_enable(&sfc->clk); 267 if (ret) 268 dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); 269 #endif 270 271 ret = rockchip_sfc_init(sfc); 272 if (ret) 273 goto err_init; 274 275 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); 276 sfc->version = rockchip_sfc_get_version(sfc); 277 sfc->max_freq = SFC_MAX_SPEED; 278 sfc->dev = bus; 279 280 return 0; 281 282 err_init: 283 #if CONFIG_IS_ENABLED(CLK) 284 clk_disable(&sfc->clk); 285 clk_disable(&sfc->hclk); 286 #endif 287 288 return ret; 289 } 290 291 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 292 { 293 int ret = 0; 294 u32 status; 295 296 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 297 status & SFC_FSR_TXLV_MASK, 298 timeout_us); 299 if (ret) { 300 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); 301 302 return -ETIMEDOUT; 303 } 304 305 return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; 306 } 307 308 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 309 { 310 int ret = 0; 311 u32 status; 312 313 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 314 status & SFC_FSR_RXLV_MASK, 315 timeout_us); 316 if (ret) { 317 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); 318 319 return -ETIMEDOUT; 320 } 321 322 return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; 323 } 324 325 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) 326 { 327 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { 328 /* 329 * SFC not support output DUMMY cycles right after CMD cycles, so 330 * treat it as ADDR cycles. 331 */ 332 op->addr.nbytes = op->dummy.nbytes; 333 op->addr.buswidth = op->dummy.buswidth; 334 op->addr.val = 0xFFFFFFFFF; 335 336 op->dummy.nbytes = 0; 337 } 338 } 339 340 static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout) 341 { 342 unsigned long tbase; 343 344 /* Wait for the DMA interrupt status */ 345 tbase = get_timer(0); 346 while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) { 347 if (get_timer(tbase) > timeout) { 348 printf("dma timeout\n"); 349 rockchip_sfc_reset(sfc); 350 351 return -ETIMEDOUT; 352 } 353 354 udelay(1); 355 } 356 357 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 358 359 return 0; 360 } 361 362 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, 363 struct spi_slave *mem, 364 const struct spi_mem_op *op, 365 u32 len) 366 { 367 struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(mem->dev); 368 u32 ctrl = 0, cmd = 0; 369 370 /* set CMD */ 371 cmd = op->cmd.opcode; 372 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); 373 374 /* set ADDR */ 375 if (op->addr.nbytes) { 376 if (op->addr.nbytes == 4) { 377 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; 378 } else if (op->addr.nbytes == 3) { 379 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; 380 } else { 381 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; 382 writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); 383 } 384 385 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); 386 } 387 388 /* set DUMMY */ 389 if (op->dummy.nbytes) { 390 if (op->dummy.buswidth == 4) 391 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; 392 else if (op->dummy.buswidth == 2) 393 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; 394 else 395 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; 396 } 397 398 /* set DATA */ 399 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ 400 writel(len, sfc->regbase + SFC_LEN_EXT); 401 else 402 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; 403 if (len) { 404 if (op->data.dir == SPI_MEM_DATA_OUT) 405 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 406 407 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); 408 } 409 if (!len && op->addr.nbytes) 410 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 411 412 /* set the Controller */ 413 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; 414 cmd |= plat->cs << SFC_CMD_CS_SHIFT; 415 416 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", 417 op->addr.nbytes, op->addr.buswidth, 418 op->dummy.nbytes, op->dummy.buswidth); 419 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", 420 ctrl, cmd, op->addr.val, len); 421 422 writel(ctrl, sfc->regbase + SFC_CTRL); 423 writel(cmd, sfc->regbase + SFC_CMD); 424 if (op->addr.nbytes) 425 writel(op->addr.val, sfc->regbase + SFC_ADDR); 426 427 return 0; 428 } 429 430 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) 431 { 432 u8 bytes = len & 0x3; 433 u32 dwords; 434 int tx_level; 435 u32 write_words; 436 u32 tmp = 0; 437 438 dwords = len >> 2; 439 while (dwords) { 440 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 441 if (tx_level < 0) 442 return tx_level; 443 write_words = min_t(u32, tx_level, dwords); 444 writesl(sfc->regbase + SFC_DATA, buf, write_words); 445 buf += write_words << 2; 446 dwords -= write_words; 447 } 448 449 /* write the rest non word aligned bytes */ 450 if (bytes) { 451 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 452 if (tx_level < 0) 453 return tx_level; 454 memcpy(&tmp, buf, bytes); 455 writel(tmp, sfc->regbase + SFC_DATA); 456 } 457 458 return len; 459 } 460 461 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) 462 { 463 u8 bytes = len & 0x3; 464 u32 dwords; 465 u8 read_words; 466 int rx_level; 467 int tmp; 468 469 /* word aligned access only */ 470 dwords = len >> 2; 471 while (dwords) { 472 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 473 if (rx_level < 0) 474 return rx_level; 475 read_words = min_t(u32, rx_level, dwords); 476 readsl(sfc->regbase + SFC_DATA, buf, read_words); 477 buf += read_words << 2; 478 dwords -= read_words; 479 } 480 481 /* read the rest non word aligned bytes */ 482 if (bytes) { 483 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 484 if (rx_level < 0) 485 return rx_level; 486 tmp = readl(sfc->regbase + SFC_DATA); 487 memcpy(buf, &tmp, bytes); 488 } 489 490 return len; 491 } 492 493 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) 494 { 495 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 496 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); 497 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); 498 499 return len; 500 } 501 502 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, 503 const struct spi_mem_op *op, u32 len) 504 { 505 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); 506 507 if (op->data.dir == SPI_MEM_DATA_OUT) 508 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); 509 else 510 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); 511 } 512 513 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, 514 const struct spi_mem_op *op, u32 len) 515 { 516 struct bounce_buffer bb; 517 unsigned int bb_flags; 518 void *dma_buf; 519 int ret; 520 521 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); 522 523 if (op->data.dir == SPI_MEM_DATA_OUT) { 524 dma_buf = (void *)op->data.buf.out; 525 bb_flags = GEN_BB_READ; 526 } else { 527 dma_buf = (void *)op->data.buf.in; 528 bb_flags = GEN_BB_WRITE; 529 } 530 531 ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags); 532 if (ret) 533 return ret; 534 535 ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len); 536 rockchip_sfc_wait_for_dma_finished(sfc, len * 10); 537 bounce_buffer_stop(&bb); 538 539 return ret; 540 } 541 542 static int rockchip_sfc_xfer_data_dma_async(struct rockchip_sfc *sfc, 543 const struct spi_mem_op *op, u32 len) 544 { 545 void *dma_buf; 546 547 if (op->data.dir == SPI_MEM_DATA_OUT) 548 dma_buf = (void *)op->data.buf.out; 549 else 550 dma_buf = (void *)op->data.buf.in; 551 552 dev_dbg(sfc->dev, "xfer_dma_async len=%x %p\n", len, dma_buf); 553 554 flush_dcache_range((unsigned long)dma_buf, 555 (unsigned long)dma_buf + len); 556 557 rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)dma_buf, len); 558 sfc->last_async_size = len; 559 560 return 0; 561 } 562 563 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) 564 { 565 int ret = 0; 566 u32 status; 567 568 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, 569 !(status & SFC_SR_IS_BUSY), 570 timeout_us); 571 if (ret) { 572 dev_err(sfc->dev, "wait sfc idle timeout\n"); 573 rockchip_sfc_reset(sfc); 574 575 ret = -EIO; 576 } 577 578 return ret; 579 } 580 581 static int rockchip_sfc_exec_op(struct spi_slave *mem, 582 const struct spi_mem_op *op) 583 { 584 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 585 u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); 586 int ret; 587 588 /* Wait for last async transfer finished */ 589 if (sfc->last_async_size) { 590 rockchip_sfc_wait_for_dma_finished(sfc, sfc->last_async_size); 591 sfc->last_async_size = 0; 592 } 593 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 594 rockchip_sfc_xfer_setup(sfc, mem, op, len); 595 if (len) { 596 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) { 597 if (mem->mode & SPI_DMA_PREPARE) 598 return rockchip_sfc_xfer_data_dma_async(sfc, op, len); 599 ret = rockchip_sfc_xfer_data_dma(sfc, op, len); 600 } else { 601 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 602 } 603 604 if (ret != len) { 605 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); 606 607 return -EIO; 608 } 609 } 610 611 return rockchip_sfc_xfer_done(sfc, 100000); 612 } 613 614 static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op) 615 { 616 struct rockchip_sfc *sfc = dev_get_platdata(mem->dev->parent); 617 618 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); 619 620 return 0; 621 } 622 623 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 624 { 625 struct rockchip_sfc *sfc = dev_get_platdata(bus); 626 627 if (speed > sfc->max_freq) 628 speed = sfc->max_freq; 629 630 if (speed == sfc->speed) 631 return 0; 632 633 #if CONFIG_IS_ENABLED(CLK) 634 int ret = clk_set_rate(&sfc->clk, speed); 635 636 if (ret < 0) { 637 dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", 638 speed); 639 return ret; 640 } 641 sfc->speed = speed; 642 #else 643 dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); 644 #endif 645 return 0; 646 } 647 648 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 649 { 650 return 0; 651 } 652 653 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { 654 .adjust_op_size = rockchip_sfc_adjust_op_size, 655 .exec_op = rockchip_sfc_exec_op, 656 }; 657 658 static const struct dm_spi_ops rockchip_sfc_ops = { 659 .mem_ops = &rockchip_sfc_mem_ops, 660 .set_speed = rockchip_sfc_set_speed, 661 .set_mode = rockchip_sfc_set_mode, 662 }; 663 664 static const struct udevice_id rockchip_sfc_ids[] = { 665 { .compatible = "rockchip,sfc"}, 666 {}, 667 }; 668 669 U_BOOT_DRIVER(rockchip_sfc_driver) = { 670 .name = "rockchip_sfc", 671 .id = UCLASS_SPI, 672 .of_match = rockchip_sfc_ids, 673 .ops = &rockchip_sfc_ops, 674 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 675 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc), 676 .probe = rockchip_sfc_probe, 677 }; 678