spi: rockchip_sfc: Support auto_merge

Change-Id: I4416b004d315f2f5689312b1eb53e36fce7f6bbf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support maximum dll cell setting for chips

Change-Id: I4349832bd5ba07ae1aed6df27c1c2ab39b93137e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support sclk_x2_bypass

Change-Id: I1f2af9c75389bafa530b2a48b32cbb765973e4d5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: spi-rockchip-sfc: Support SFC_VER_9

Change-Id: Id1bd812f400a9be437c3824c7c19f90dbae81783
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Print Bootrom cmd info

6BH means quad line, 03H means single line.

Change-Id: I9082528be43039383e0e732bc80285d05c6ed15b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support sclk_x2 version

SFC after version 8 supports dtr mode, so the IO is the binary output of
the controller clock.

Change-Id: I38e17cf1c33b4a4bdcc0a24a91bd7359512a144a
Signed

spi: rockchip_sfc: Support sclk_x2 version

SFC after version 8 supports dtr mode, so the IO is the binary output of
the controller clock.

Change-Id: I38e17cf1c33b4a4bdcc0a24a91bd7359512a144a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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spi: rockchip_sfc: Support cs-gpios

Change-Id: Ida79e915a84081bf58b36978c0c4351927aba380
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Initial the version at the first

Change-Id: I353d581c11daf6b15b48e44e61cbd2985d6387b3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support tx fifo 128B

Change-Id: If2bb5eee2a2db27191e09254bf0543d62b31fc40
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Add macro limitation for dll tuning apis

Change-Id: I54d41c2f6a138f92a6470d80a5b9d3c00070136e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support chip select 1

Change-Id: I13b4769eb0c8a2414a0c9b7cd35cae35d09f3dd0
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: soft_spi: Synchronize the names of control pins with kernel

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I9e46447487ac6ef0007057faa1ad685bd97a8dd7

spi: rockchip_sfc: Support ver8

Change-Id: I2733ae03f25c715771c624e0e78a11f1b07c3440
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip: Add quirks for px30

Change-Id: Iff8282d371e1ffc51101ea814dfbb0413de6c1d5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip: Add quirks for controller workaround

Change-Id: I5aed76f9ccf1799be228a7f4dce0f6cad2af0f11
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Remove useless cache flush for SPI_DMA_PREPARE read

Change-Id: I63185ee05e893b64672223a48ee778f86a620fc8
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rk_spi: Do not output data in RO mode

Change-Id: I9a631c3d36246264ca8b9974572830aaa031a6de
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support ver6

Change-Id: I16b8796e61eb34de727cf1d34a32ac64ac11c0f9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rk_spi: Support rx sample delay

Adding a number of spi_clk cycles delay for rx sample.

Change-Id: I4b5e71f1d5d11a085cf54eafd4299b0ca290b642
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

rockchip: drivers: spi: Support read only

Change-Id: Ib99db168d9ba3566c9e038986af202023a4a5daa
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Support delay line tuning

Change-Id: I38b26cf15e0c82c713245defaf2478a9708e3f92
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

spi: rockchip_sfc: Supoprt spi async transfer

Change-Id: Ib7e09ea564db0d673effab506a90c7cb9fbb4a33
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

UPSTREAM: spi: rockchip_sfc: Using read_poll

Using read_poll logic.

Tested-by: Chris Morgan <macromorgan@hotmail.com>
Change-Id: I5e24cd0930f299117d7f34af7275f5fbe5f48a95
Signed-off-by: Jon Lin <jo

UPSTREAM: spi: rockchip_sfc: Using read_poll

Using read_poll logic.

Tested-by: Chris Morgan <macromorgan@hotmail.com>
Change-Id: I5e24cd0930f299117d7f34af7275f5fbe5f48a95
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from 20210819094557.v2.2.Ie019ef3e204a0095d9580fa48b7cbf9b9e05fc33@changeid)

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UPSTREAM: spi: rockchip_sfc: Implement set_speed logic

Set clock related processing into set_speed logic. And Optimize
printing format.

Tested-by: Chris Morgan <macromorgan@hotmail.com>
Change-Id:

UPSTREAM: spi: rockchip_sfc: Implement set_speed logic

Set clock related processing into set_speed logic. And Optimize
printing format.

Tested-by: Chris Morgan <macromorgan@hotmail.com>
Change-Id: Iaf6f3d58cc44deb4a22d74984531b32c53386201
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from 20210819094557.v2.1.Id0647655ab4060f95c9a49fe834465bbe39b8d31@changeid)
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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UPSTREAM: spi: rockchip_sfc: add support for Rockchip SFC

This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, howev

UPSTREAM: spi: rockchip_sfc: add support for Rockchip SFC

This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.

This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of the driver is that this one does not support DMA. In testing
the performance difference (performing a dual mode read on a 128Mb
chip) is negligible. DMA, if used, must also be disabled in SPL
mode when using A-TF anyway.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 3fb08a21387b9f4f24cfd5b45f9d7f344d40fba4)
Change-Id: I75e1fcae03c060c2b8ccf8c49e026dc882469166

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