mtd: spi: Support auto merge

In order to enable dual NOR flash users to experience double the
capacity and avoid frequent switching between two NOR flash devices,
the two NOR flash devices are virtu

mtd: spi: Support auto merge

In order to enable dual NOR flash users to experience double the
capacity and avoid frequent switching between two NOR flash devices,
the two NOR flash devices are virtualized into one device, which
I name it auto_merge tech.

Change-Id: I5edd7cde0481b1de6a35fce7ac67068889ff5ffe
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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mtd: spi-nor-ids: Support BFPT_DWORD15_QER_SR2_BIT1_WR

QE is bit 1 of the status register 2. Status register 1 is read using
Read Status instruction 05h. Status register 2 is read using instruction

mtd: spi-nor-ids: Support BFPT_DWORD15_QER_SR2_BIT1_WR

QE is bit 1 of the status register 2. Status register 1 is read using
Read Status instruction 05h. Status register 2 is read using instruction
35h, and status register 3 is read using instruction 15h. QE is set via
write Status Register instruction 31h with one data byte where bit 1 is
one. It is cleared via Write Status Register instruction 31h with one
data byte where bit 1 is zero.

Change-Id: I4bfab50210dc8dbc7818c41d15b516be49640706
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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mtd: spi-nor-ids: Issue the flash JEDEC id

Change-Id: I32e1d1ea901cf63bda7a07626e0d57b3c6bb48f6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

mtd: spi-nor-ids: support NM25Q128EVB

Change-Id: Ic77028b0e2a30d1b6791d667e57da25e7a15b3f5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

UPSTREAM: mtd: spi-nor-core: Add octal mode support

Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.

Sig

UPSTREAM: mtd: spi-nor-core: Add octal mode support

Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
(cherry picked from commit 658df8bd946493e7fa7b0048a3a9bd658a1f4518)
Change-Id: I1fabb494a963ceccb873c8a04fc3241eddd65069
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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UPSTREAM: mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with SPI_FLASH_USE_4K_SECTORS

U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector
support. Use that instead of MTD_S

UPSTREAM: mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with SPI_FLASH_USE_4K_SECTORS

U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector
support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS.

Change-Id: Ia999865ee27d03cc036ef7df647a7929c2f9945c
Reported-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 2a2174d3da33b9e71a26ecc5d40f1369401275fd)

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UPSTREAM: mtd: spi-nor-core: Use dev_err for reporting erase/write failures

Use dev_err() when reporting reason for erase/write failures so that
users can be made aware of the reason for failure.

C

UPSTREAM: mtd: spi-nor-core: Use dev_err for reporting erase/write failures

Use dev_err() when reporting reason for erase/write failures so that
users can be made aware of the reason for failure.

Change-Id: I30be5f7077082f7d1dbad28f9145f61150e4c61d
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit cc9118757f6ce57bf1776cca41cb52a3dc24401e)

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UPSTREAM: mtd: spi-nor: add missing SST26* flash IC protection ops

Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework)
performs switch from previous 'spi_flash' infrastructure without
pr

UPSTREAM: mtd: spi-nor: add missing SST26* flash IC protection ops

Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework)
performs switch from previous 'spi_flash' infrastructure without
proper testing/investigations which results in a regressions for
SST26 flash series.

Add missing SST26* flash IC protection ops which were introduced
previously by
Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs
protection ops)

Change-Id: I4944e5680fb58c0a2fd2f38a6477acab24536928
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e0cacdcc0a479dc70d3048ee40705478dce2655e)

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Revert "mtd: spinor: Add more mtd information"

This reverts commit 8ff9c29cc8f6c82d68b6e1f3d373e0f4e78b087c.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Change-Id: I72d3409e3bb3061492de1023b269

Revert "mtd: spinor: Add more mtd information"

This reverts commit 8ff9c29cc8f6c82d68b6e1f3d373e0f4e78b087c.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Change-Id: I72d3409e3bb3061492de1023b269acb5dfd93667

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mtd: spinor: Add more mtd information

1.erasesize_shift, erasesize_mask
2.it's useful for mtd_blk.c

Change-Id: I0bd184fc86637849fbd079f9f539387465a07b8f
Signed-off-by: Jon Lin <jon.lin@rock-chips.c

mtd: spinor: Add more mtd information

1.erasesize_shift, erasesize_mask
2.it's useful for mtd_blk.c

Change-Id: I0bd184fc86637849fbd079f9f539387465a07b8f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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UPSTREAM: mtd: spi-nor: fix page program issue when using spi-mem driver

Some SPI controllers can't write nor->page_size bytes in a single step
because their TX FIFO is too small, but when that happ

UPSTREAM: mtd: spi-nor: fix page program issue when using spi-mem driver

Some SPI controllers can't write nor->page_size bytes in a single step
because their TX FIFO is too small, but when that happens we should
make sure a WRITE_EN command before each write access and READ_SR command
after each write access is issued.

We should allow nor->write() to return a size that is smaller than the
requested write size to gracefully handle this case.

Also, the spi_nor_write_data() should return the actual number of bytes
that were written during the spi_mem_exec_op() operation.

This patch is a combination of two commits backported from kernel:

commit 630d6bd8a3b4 ("mtd: spi-nor: Support controllers with limit ...")
commit 3baa8ec88c2f ("mtd: devices: m25p80: Make sure WRITE_EN is ...")

Cc: Vignesh R <vigneshr@ti.com>
Change-Id: I352142d4325b15c52eb04ac929b9e2bcd3648472
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Acked-by: Vignesh R <vigneshr@ti.com>
Tested-by: Shyam Saini <shyam.saini@amarulasolutions.com> # microzed
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 60e2bf46784ebbd30ff29b3d3c7c97e56b11e86a)

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UPSTREAM: mtd: spi: Replace ad-hoc default implementation with spi_mem_op

Replace the ad-hoc erase operation implementation with a simple spi_mem_op
implementation of the same functionality. This is

UPSTREAM: mtd: spi: Replace ad-hoc default implementation with spi_mem_op

Replace the ad-hoc erase operation implementation with a simple spi_mem_op
implementation of the same functionality. This is a minor optimization and
removal of the ad-hoc code.

This however also changes the behavior of the execution of the erase
opcode from two separate transfer requests to the SPI NOR driver to
one transfer request to the SPI NOR driver. The former was how U-Boot
behaved before the SPI NOR framework was imported and the later was
introduced by the SPI NOR framework. The former is more optimal, so
keep that.

Change-Id: Ie8f39dff83fd7f49b606c813be0260a159257ac9
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Horatiu Vultur <horatiu.vultur@microchip.com>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>
Tested-by: Ashish Kumar <Ashish.kumar@nxp.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit f909ddb3e1770a5ef18606b46000e0d3eaf63b2e)

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UPSTREAM: mtd: spi: Add lightweight SPI flash stack for SPL

Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints

UPSTREAM: mtd: spi: Add lightweight SPI flash stack for SPL

Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints and
would need to use SPI flash framework just to read images/data from
flash. There is approximately 1.5 to 2KB savings with this.

Based on prior work of reducing spi flash id table by
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Change-Id: I9b87d3ed4a01d2ce31eee327b67689e5e2ecff57
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 778572d7cb1e2df678340fda9b081e4f7bd6c4b3)

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UPSTREAM: mtd: spi: Switch to new SPI NOR framework

Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
u

UPSTREAM: mtd: spi: Switch to new SPI NOR framework

Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Change-Id: I4c459ebdff8b2aec38623f27d0ba630c6c6f1ca3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c4e8862308d420e85c227498797c32410d9e47a8)

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UPSTREAM: mtd: spi: spi-nor-core: Add back U-Boot specific features

For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework

UPSTREAM: mtd: spi: spi-nor-core: Add back U-Boot specific features

For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework

Change-Id: I6888e49eeaeb89adca64cb8ca6683b27781bd7a8
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8c927809ea960596345c33b02294af6e236d4ad4)

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UPSTREAM: mtd: spi: spi-nor-core: Add SFDP support

Sync Serial Flash Discoverable Parameters (SFDP) parsing support from
Linux. This allows auto detection and configuration of Flash parameters.

Sig

UPSTREAM: mtd: spi: spi-nor-core: Add SFDP support

Sync Serial Flash Discoverable Parameters (SFDP) parsing support from
Linux. This allows auto detection and configuration of Flash parameters.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Change-Id: I595586c8e491a56b6819182bc30de8e7f70b9476
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 0c6f187cdb18b52bcf6d3964771cf3a36b758568)

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UPSTREAM: mtd: spi: spi-nor-core: Add 4 Byte addressing support

Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x
th

UPSTREAM: mtd: spi: spi-nor-core: Add 4 Byte addressing support

Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x
that no longer support legacy Bank Address Register(BAR) way of accessing
>16MB region.

Change-Id: I051c17ed80e1b483166a3057732ae579cc2572c9
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 61059bc55ab108bdd53c953480b3f84f9d6100ab)

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UPSTREAM: mtd: spi: spi-nor-core: Add SPI MEM support

Many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to make

UPSTREAM: mtd: spi: spi-nor-core: Add SPI MEM support

Many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to make use of it. Recent spi-mem layer provides a way to support such
controllers.
Therefore, add spi-mem support to spi-nor-core as a way to support SPI
controllers with MMIO interface. SPI MEM layer takes care of translating
spi_mem_ops to spi_xfer()s in case of legacy SPI controllers.

Change-Id: Ib62acebae33a6c21961d0c2f2630267c1346d193
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 492e65b29b4c75ba6139577e10c9a5a6747ffa5a)

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UPSTREAM: mtd: spi: Port SPI NOR framework from Linux

Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different t

UPSTREAM: mtd: spi: Port SPI NOR framework from Linux

Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
quad mode enable sequences. Many newer flashes no longer support BANK
registers used by sf layer to a access >16MB of flash address space.
So, sync SPI NOR framework from Linux v4.19 that supports all the
above features. Start with basic sync up that brings in basic framework
subsequent commits will bring in more features.

Change-Id: I16b35b48166c00b7a4be215cfb6dcde00805f9f8
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 7aeedac01534ab343c28abed60f8e0fb9311bbee)

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