1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 * 9 * Synced from Linux v4.19 10 */ 11 12 #include <common.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/log2.h> 16 #include <linux/math64.h> 17 #include <linux/sizes.h> 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/mtd/spi-nor.h> 21 #include <spi-mem.h> 22 #include <spi.h> 23 24 #include "sf_internal.h" 25 26 /* Define max times to check status register before we give up. */ 27 28 /* 29 * For everything but full-chip erase; probably could be much smaller, but kept 30 * around for safety for now 31 */ 32 33 #define HZ CONFIG_SYS_HZ 34 35 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 36 37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op 38 *op, void *buf) 39 { 40 if (op->data.dir == SPI_MEM_DATA_IN) 41 op->data.buf.in = buf; 42 else 43 op->data.buf.out = buf; 44 return spi_mem_exec_op(nor->spi, op); 45 } 46 47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) 48 { 49 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1), 50 SPI_MEM_OP_NO_ADDR, 51 SPI_MEM_OP_NO_DUMMY, 52 SPI_MEM_OP_DATA_IN(len, NULL, 1)); 53 int ret; 54 55 ret = spi_nor_read_write_reg(nor, &op, val); 56 if (ret < 0) 57 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret, 58 code); 59 60 return ret; 61 } 62 63 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) 64 { 65 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1), 66 SPI_MEM_OP_NO_ADDR, 67 SPI_MEM_OP_NO_DUMMY, 68 SPI_MEM_OP_DATA_OUT(len, NULL, 1)); 69 70 return spi_nor_read_write_reg(nor, &op, buf); 71 } 72 73 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, 74 u_char *buf) 75 { 76 struct spi_mem_op op = 77 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), 78 SPI_MEM_OP_ADDR(nor->addr_width, from, 1), 79 SPI_MEM_OP_DUMMY(nor->read_dummy, 1), 80 SPI_MEM_OP_DATA_IN(len, buf, 1)); 81 size_t remaining = len; 82 int ret; 83 84 /* get transfer protocols. */ 85 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); 86 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); 87 op.dummy.buswidth = op.addr.buswidth; 88 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 89 90 /* convert the dummy cycles to the number of bytes */ 91 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 92 93 while (remaining) { 94 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; 95 ret = spi_mem_adjust_op_size(nor->spi, &op); 96 if (ret) 97 return ret; 98 99 ret = spi_mem_exec_op(nor->spi, &op); 100 if (ret) 101 return ret; 102 103 op.addr.val += op.data.nbytes; 104 remaining -= op.data.nbytes; 105 op.data.buf.in += op.data.nbytes; 106 } 107 108 return len; 109 } 110 111 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 112 const u_char *buf) 113 { 114 struct spi_mem_op op = 115 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1), 116 SPI_MEM_OP_ADDR(nor->addr_width, to, 1), 117 SPI_MEM_OP_NO_DUMMY, 118 SPI_MEM_OP_DATA_OUT(len, buf, 1)); 119 size_t remaining = len; 120 int ret; 121 122 /* get transfer protocols. */ 123 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto); 124 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); 125 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 126 127 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 128 op.addr.nbytes = 0; 129 130 while (remaining) { 131 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; 132 ret = spi_mem_adjust_op_size(nor->spi, &op); 133 if (ret) 134 return ret; 135 136 ret = spi_mem_exec_op(nor->spi, &op); 137 if (ret) 138 return ret; 139 140 op.addr.val += op.data.nbytes; 141 remaining -= op.data.nbytes; 142 op.data.buf.out += op.data.nbytes; 143 } 144 145 return len; 146 } 147 148 /* 149 * Read the status register, returning its value in the location 150 * Return the status register value. 151 * Returns negative if error occurred. 152 */ 153 static int read_sr(struct spi_nor *nor) 154 { 155 int ret; 156 u8 val; 157 158 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); 159 if (ret < 0) { 160 pr_debug("error %d reading SR\n", (int)ret); 161 return ret; 162 } 163 164 return val; 165 } 166 167 /* 168 * Read the flag status register, returning its value in the location 169 * Return the status register value. 170 * Returns negative if error occurred. 171 */ 172 static int read_fsr(struct spi_nor *nor) 173 { 174 int ret; 175 u8 val; 176 177 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); 178 if (ret < 0) { 179 pr_debug("error %d reading FSR\n", ret); 180 return ret; 181 } 182 183 return val; 184 } 185 186 /* 187 * Read configuration register, returning its value in the 188 * location. Return the configuration register value. 189 * Returns negative if error occurred. 190 */ 191 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 192 static int read_cr(struct spi_nor *nor) 193 { 194 int ret; 195 u8 val; 196 197 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); 198 if (ret < 0) { 199 dev_dbg(nor->dev, "error %d reading CR\n", ret); 200 return ret; 201 } 202 203 return val; 204 } 205 #endif 206 207 /* 208 * Write status register 1 byte 209 * Returns negative if error occurred. 210 */ 211 static int write_sr(struct spi_nor *nor, u8 val) 212 { 213 nor->cmd_buf[0] = val; 214 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); 215 } 216 217 /* 218 * Set write enable latch with Write Enable command. 219 * Returns negative if error occurred. 220 */ 221 static int write_enable(struct spi_nor *nor) 222 { 223 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); 224 } 225 226 /* 227 * Send write disable instruction to the chip. 228 */ 229 static int write_disable(struct spi_nor *nor) 230 { 231 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); 232 } 233 234 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) 235 { 236 return mtd->priv; 237 } 238 239 #ifndef CONFIG_SPI_FLASH_BAR 240 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 241 { 242 size_t i; 243 244 for (i = 0; i < size; i++) 245 if (table[i][0] == opcode) 246 return table[i][1]; 247 248 /* No conversion found, keep input op code. */ 249 return opcode; 250 } 251 252 static u8 spi_nor_convert_3to4_read(u8 opcode) 253 { 254 static const u8 spi_nor_3to4_read[][2] = { 255 { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 256 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 257 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 258 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 259 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 260 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 261 262 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 263 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 264 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 265 }; 266 267 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 268 ARRAY_SIZE(spi_nor_3to4_read)); 269 } 270 271 static u8 spi_nor_convert_3to4_program(u8 opcode) 272 { 273 static const u8 spi_nor_3to4_program[][2] = { 274 { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 275 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 276 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 277 }; 278 279 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 280 ARRAY_SIZE(spi_nor_3to4_program)); 281 } 282 283 static u8 spi_nor_convert_3to4_erase(u8 opcode) 284 { 285 static const u8 spi_nor_3to4_erase[][2] = { 286 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 287 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 288 { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 289 }; 290 291 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 292 ARRAY_SIZE(spi_nor_3to4_erase)); 293 } 294 295 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, 296 const struct flash_info *info) 297 { 298 /* Do some manufacturer fixups first */ 299 switch (JEDEC_MFR(info)) { 300 case SNOR_MFR_SPANSION: 301 /* No small sector erase for 4-byte command set */ 302 nor->erase_opcode = SPINOR_OP_SE; 303 nor->mtd.erasesize = info->sector_size; 304 break; 305 306 default: 307 break; 308 } 309 310 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 311 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 312 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 313 } 314 #endif /* !CONFIG_SPI_FLASH_BAR */ 315 316 /* Enable/disable 4-byte addressing mode. */ 317 static int set_4byte(struct spi_nor *nor, const struct flash_info *info, 318 int enable) 319 { 320 int status; 321 bool need_wren = false; 322 u8 cmd; 323 324 switch (JEDEC_MFR(info)) { 325 case SNOR_MFR_ST: 326 case SNOR_MFR_MICRON: 327 /* Some Micron need WREN command; all will accept it */ 328 need_wren = true; 329 case SNOR_MFR_MACRONIX: 330 case SNOR_MFR_WINBOND: 331 if (need_wren) 332 write_enable(nor); 333 334 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; 335 status = nor->write_reg(nor, cmd, NULL, 0); 336 if (need_wren) 337 write_disable(nor); 338 339 if (!status && !enable && 340 JEDEC_MFR(info) == SNOR_MFR_WINBOND) { 341 /* 342 * On Winbond W25Q256FV, leaving 4byte mode causes 343 * the Extended Address Register to be set to 1, so all 344 * 3-byte-address reads come from the second 16M. 345 * We must clear the register to enable normal behavior. 346 */ 347 write_enable(nor); 348 nor->cmd_buf[0] = 0; 349 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1); 350 write_disable(nor); 351 } 352 353 return status; 354 default: 355 /* Spansion style */ 356 nor->cmd_buf[0] = enable << 7; 357 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); 358 } 359 } 360 361 static int spi_nor_sr_ready(struct spi_nor *nor) 362 { 363 int sr = read_sr(nor); 364 365 if (sr < 0) 366 return sr; 367 368 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) { 369 if (sr & SR_E_ERR) 370 dev_dbg(nor->dev, "Erase Error occurred\n"); 371 else 372 dev_dbg(nor->dev, "Programming Error occurred\n"); 373 374 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0); 375 return -EIO; 376 } 377 378 return !(sr & SR_WIP); 379 } 380 381 static int spi_nor_fsr_ready(struct spi_nor *nor) 382 { 383 int fsr = read_fsr(nor); 384 385 if (fsr < 0) 386 return fsr; 387 388 if (fsr & (FSR_E_ERR | FSR_P_ERR)) { 389 if (fsr & FSR_E_ERR) 390 dev_dbg(nor->dev, "Erase operation failed.\n"); 391 else 392 dev_dbg(nor->dev, "Program operation failed.\n"); 393 394 if (fsr & FSR_PT_ERR) 395 dev_dbg(nor->dev, 396 "Attempted to modify a protected sector.\n"); 397 398 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0); 399 return -EIO; 400 } 401 402 return fsr & FSR_READY; 403 } 404 405 static int spi_nor_ready(struct spi_nor *nor) 406 { 407 int sr, fsr; 408 409 sr = spi_nor_sr_ready(nor); 410 if (sr < 0) 411 return sr; 412 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; 413 if (fsr < 0) 414 return fsr; 415 return sr && fsr; 416 } 417 418 /* 419 * Service routine to read status register until ready, or timeout occurs. 420 * Returns non-zero if error. 421 */ 422 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 423 unsigned long timeout) 424 { 425 unsigned long timebase; 426 int ret; 427 428 timebase = get_timer(0); 429 430 while (get_timer(timebase) < timeout) { 431 ret = spi_nor_ready(nor); 432 if (ret < 0) 433 return ret; 434 if (ret) 435 return 0; 436 } 437 438 dev_err(nor->dev, "flash operation timed out\n"); 439 440 return -ETIMEDOUT; 441 } 442 443 static int spi_nor_wait_till_ready(struct spi_nor *nor) 444 { 445 return spi_nor_wait_till_ready_with_timeout(nor, 446 DEFAULT_READY_WAIT_JIFFIES); 447 } 448 449 #ifdef CONFIG_SPI_FLASH_BAR 450 /* 451 * This "clean_bar" is necessary in a situation when one was accessing 452 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit. 453 * 454 * After it the BA24 bit shall be cleared to allow access to correct 455 * memory region after SW reset (by calling "reset" command). 456 * 457 * Otherwise, the BA24 bit may be left set and then after reset, the 458 * ROM would read/write/erase SPL from 16 MiB * bank_sel address. 459 */ 460 static int clean_bar(struct spi_nor *nor) 461 { 462 u8 cmd, bank_sel = 0; 463 464 if (nor->bank_curr == 0) 465 return 0; 466 cmd = nor->bank_write_cmd; 467 nor->bank_curr = 0; 468 write_enable(nor); 469 470 return nor->write_reg(nor, cmd, &bank_sel, 1); 471 } 472 473 static int write_bar(struct spi_nor *nor, u32 offset) 474 { 475 u8 cmd, bank_sel; 476 int ret; 477 478 bank_sel = offset / SZ_16M; 479 if (bank_sel == nor->bank_curr) 480 goto bar_end; 481 482 cmd = nor->bank_write_cmd; 483 write_enable(nor); 484 ret = nor->write_reg(nor, cmd, &bank_sel, 1); 485 if (ret < 0) { 486 debug("SF: fail to write bank register\n"); 487 return ret; 488 } 489 490 bar_end: 491 nor->bank_curr = bank_sel; 492 return nor->bank_curr; 493 } 494 495 static int read_bar(struct spi_nor *nor, const struct flash_info *info) 496 { 497 u8 curr_bank = 0; 498 int ret; 499 500 switch (JEDEC_MFR(info)) { 501 case SNOR_MFR_SPANSION: 502 nor->bank_read_cmd = SPINOR_OP_BRRD; 503 nor->bank_write_cmd = SPINOR_OP_BRWR; 504 break; 505 default: 506 nor->bank_read_cmd = SPINOR_OP_RDEAR; 507 nor->bank_write_cmd = SPINOR_OP_WREAR; 508 } 509 510 ret = nor->read_reg(nor, nor->bank_read_cmd, 511 &curr_bank, 1); 512 if (ret) { 513 debug("SF: fail to read bank addr register\n"); 514 return ret; 515 } 516 nor->bank_curr = curr_bank; 517 518 return 0; 519 } 520 #endif 521 522 /* 523 * Initiate the erasure of a single sector 524 */ 525 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 526 { 527 u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; 528 int i; 529 530 if (nor->erase) 531 return nor->erase(nor, addr); 532 533 /* 534 * Default implementation, if driver doesn't have a specialized HW 535 * control 536 */ 537 for (i = nor->addr_width - 1; i >= 0; i--) { 538 buf[i] = addr & 0xff; 539 addr >>= 8; 540 } 541 542 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); 543 } 544 545 /* 546 * Erase an address range on the nor chip. The address range may extend 547 * one or more erase sectors. Return an error is there is a problem erasing. 548 */ 549 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 550 { 551 struct spi_nor *nor = mtd_to_spi_nor(mtd); 552 u32 addr, len, rem; 553 int ret; 554 555 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 556 (long long)instr->len); 557 558 div_u64_rem(instr->len, mtd->erasesize, &rem); 559 if (rem) 560 return -EINVAL; 561 562 addr = instr->addr; 563 len = instr->len; 564 565 while (len) { 566 #ifdef CONFIG_SPI_FLASH_BAR 567 ret = write_bar(nor, addr); 568 if (ret < 0) 569 return ret; 570 #endif 571 write_enable(nor); 572 573 ret = spi_nor_erase_sector(nor, addr); 574 if (ret) 575 goto erase_err; 576 577 addr += mtd->erasesize; 578 len -= mtd->erasesize; 579 580 ret = spi_nor_wait_till_ready(nor); 581 if (ret) 582 goto erase_err; 583 } 584 585 erase_err: 586 #ifdef CONFIG_SPI_FLASH_BAR 587 ret = clean_bar(nor); 588 #endif 589 write_disable(nor); 590 591 return ret; 592 } 593 594 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 595 /* Write status register and ensure bits in mask match written values */ 596 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) 597 { 598 int ret; 599 600 write_enable(nor); 601 ret = write_sr(nor, status_new); 602 if (ret) 603 return ret; 604 605 ret = spi_nor_wait_till_ready(nor); 606 if (ret) 607 return ret; 608 609 ret = read_sr(nor); 610 if (ret < 0) 611 return ret; 612 613 return ((ret & mask) != (status_new & mask)) ? -EIO : 0; 614 } 615 616 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, 617 uint64_t *len) 618 { 619 struct mtd_info *mtd = &nor->mtd; 620 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 621 int shift = ffs(mask) - 1; 622 int pow; 623 624 if (!(sr & mask)) { 625 /* No protection */ 626 *ofs = 0; 627 *len = 0; 628 } else { 629 pow = ((sr & mask) ^ mask) >> shift; 630 *len = mtd->size >> pow; 631 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) 632 *ofs = 0; 633 else 634 *ofs = mtd->size - *len; 635 } 636 } 637 638 /* 639 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if 640 * @locked is false); 0 otherwise 641 */ 642 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len, 643 u8 sr, bool locked) 644 { 645 loff_t lock_offs; 646 uint64_t lock_len; 647 648 if (!len) 649 return 1; 650 651 stm_get_locked_range(nor, sr, &lock_offs, &lock_len); 652 653 if (locked) 654 /* Requested range is a sub-range of locked range */ 655 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 656 else 657 /* Requested range does not overlap with locked range */ 658 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); 659 } 660 661 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 662 u8 sr) 663 { 664 return stm_check_lock_status_sr(nor, ofs, len, sr, true); 665 } 666 667 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 668 u8 sr) 669 { 670 return stm_check_lock_status_sr(nor, ofs, len, sr, false); 671 } 672 673 /* 674 * Lock a region of the flash. Compatible with ST Micro and similar flash. 675 * Supports the block protection bits BP{0,1,2} in the status register 676 * (SR). Does not support these features found in newer SR bitfields: 677 * - SEC: sector/block protect - only handle SEC=0 (block protect) 678 * - CMP: complement protect - only support CMP=0 (range is not complemented) 679 * 680 * Support for the following is provided conditionally for some flash: 681 * - TB: top/bottom protect 682 * 683 * Sample table portion for 8MB flash (Winbond w25q64fw): 684 * 685 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 686 * -------------------------------------------------------------------------- 687 * X | X | 0 | 0 | 0 | NONE | NONE 688 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 689 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 690 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 691 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 692 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 693 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 694 * X | X | 1 | 1 | 1 | 8 MB | ALL 695 * ------|-------|-------|-------|-------|---------------|------------------- 696 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 697 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 698 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 699 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 700 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 701 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 702 * 703 * Returns negative on errors, 0 on success. 704 */ 705 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 706 { 707 struct mtd_info *mtd = &nor->mtd; 708 int status_old, status_new; 709 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 710 u8 shift = ffs(mask) - 1, pow, val; 711 loff_t lock_len; 712 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 713 bool use_top; 714 715 status_old = read_sr(nor); 716 if (status_old < 0) 717 return status_old; 718 719 /* If nothing in our range is unlocked, we don't need to do anything */ 720 if (stm_is_locked_sr(nor, ofs, len, status_old)) 721 return 0; 722 723 /* If anything below us is unlocked, we can't use 'bottom' protection */ 724 if (!stm_is_locked_sr(nor, 0, ofs, status_old)) 725 can_be_bottom = false; 726 727 /* If anything above us is unlocked, we can't use 'top' protection */ 728 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), 729 status_old)) 730 can_be_top = false; 731 732 if (!can_be_bottom && !can_be_top) 733 return -EINVAL; 734 735 /* Prefer top, if both are valid */ 736 use_top = can_be_top; 737 738 /* lock_len: length of region that should end up locked */ 739 if (use_top) 740 lock_len = mtd->size - ofs; 741 else 742 lock_len = ofs + len; 743 744 /* 745 * Need smallest pow such that: 746 * 747 * 1 / (2^pow) <= (len / size) 748 * 749 * so (assuming power-of-2 size) we do: 750 * 751 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 752 */ 753 pow = ilog2(mtd->size) - ilog2(lock_len); 754 val = mask - (pow << shift); 755 if (val & ~mask) 756 return -EINVAL; 757 /* Don't "lock" with no region! */ 758 if (!(val & mask)) 759 return -EINVAL; 760 761 status_new = (status_old & ~mask & ~SR_TB) | val; 762 763 /* Disallow further writes if WP pin is asserted */ 764 status_new |= SR_SRWD; 765 766 if (!use_top) 767 status_new |= SR_TB; 768 769 /* Don't bother if they're the same */ 770 if (status_new == status_old) 771 return 0; 772 773 /* Only modify protection if it will not unlock other areas */ 774 if ((status_new & mask) < (status_old & mask)) 775 return -EINVAL; 776 777 return write_sr_and_check(nor, status_new, mask); 778 } 779 780 /* 781 * Unlock a region of the flash. See stm_lock() for more info 782 * 783 * Returns negative on errors, 0 on success. 784 */ 785 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 786 { 787 struct mtd_info *mtd = &nor->mtd; 788 int status_old, status_new; 789 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 790 u8 shift = ffs(mask) - 1, pow, val; 791 loff_t lock_len; 792 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 793 bool use_top; 794 795 status_old = read_sr(nor); 796 if (status_old < 0) 797 return status_old; 798 799 /* If nothing in our range is locked, we don't need to do anything */ 800 if (stm_is_unlocked_sr(nor, ofs, len, status_old)) 801 return 0; 802 803 /* If anything below us is locked, we can't use 'top' protection */ 804 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) 805 can_be_top = false; 806 807 /* If anything above us is locked, we can't use 'bottom' protection */ 808 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), 809 status_old)) 810 can_be_bottom = false; 811 812 if (!can_be_bottom && !can_be_top) 813 return -EINVAL; 814 815 /* Prefer top, if both are valid */ 816 use_top = can_be_top; 817 818 /* lock_len: length of region that should remain locked */ 819 if (use_top) 820 lock_len = mtd->size - (ofs + len); 821 else 822 lock_len = ofs; 823 824 /* 825 * Need largest pow such that: 826 * 827 * 1 / (2^pow) >= (len / size) 828 * 829 * so (assuming power-of-2 size) we do: 830 * 831 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 832 */ 833 pow = ilog2(mtd->size) - order_base_2(lock_len); 834 if (lock_len == 0) { 835 val = 0; /* fully unlocked */ 836 } else { 837 val = mask - (pow << shift); 838 /* Some power-of-two sizes are not supported */ 839 if (val & ~mask) 840 return -EINVAL; 841 } 842 843 status_new = (status_old & ~mask & ~SR_TB) | val; 844 845 /* Don't protect status register if we're fully unlocked */ 846 if (lock_len == 0) 847 status_new &= ~SR_SRWD; 848 849 if (!use_top) 850 status_new |= SR_TB; 851 852 /* Don't bother if they're the same */ 853 if (status_new == status_old) 854 return 0; 855 856 /* Only modify protection if it will not lock other areas */ 857 if ((status_new & mask) > (status_old & mask)) 858 return -EINVAL; 859 860 return write_sr_and_check(nor, status_new, mask); 861 } 862 863 /* 864 * Check if a region of the flash is (completely) locked. See stm_lock() for 865 * more info. 866 * 867 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 868 * negative on errors. 869 */ 870 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 871 { 872 int status; 873 874 status = read_sr(nor); 875 if (status < 0) 876 return status; 877 878 return stm_is_locked_sr(nor, ofs, len, status); 879 } 880 #endif /* CONFIG_SPI_FLASH_STMICRO */ 881 882 /* Used when the "_ext_id" is two bytes at most */ 883 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 884 .id = { \ 885 ((_jedec_id) >> 16) & 0xff, \ 886 ((_jedec_id) >> 8) & 0xff, \ 887 (_jedec_id) & 0xff, \ 888 ((_ext_id) >> 8) & 0xff, \ 889 (_ext_id) & 0xff, \ 890 }, \ 891 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 892 .sector_size = (_sector_size), \ 893 .n_sectors = (_n_sectors), \ 894 .page_size = 256, \ 895 .flags = (_flags), 896 897 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 898 .id = { \ 899 ((_jedec_id) >> 16) & 0xff, \ 900 ((_jedec_id) >> 8) & 0xff, \ 901 (_jedec_id) & 0xff, \ 902 ((_ext_id) >> 16) & 0xff, \ 903 ((_ext_id) >> 8) & 0xff, \ 904 (_ext_id) & 0xff, \ 905 }, \ 906 .id_len = 6, \ 907 .sector_size = (_sector_size), \ 908 .n_sectors = (_n_sectors), \ 909 .page_size = 256, \ 910 .flags = (_flags), 911 912 /* NOTE: double check command sets and memory organization when you add 913 * more nor chips. This current list focusses on newer chips, which 914 * have been converging on command sets which including JEDEC ID. 915 * 916 * All newly added entries should describe *hardware* and should use SECT_4K 917 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage 918 * scenarios excluding small sectors there is config option that can be 919 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. 920 * For historical (and compatibility) reasons (before we got above config) some 921 * old entries may be missing 4K flag. 922 */ 923 const struct flash_info spi_nor_ids[] = { 924 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ 925 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 926 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 927 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 928 929 { "at45db011d", INFO(0x1f2200, 0, 64 * 1024, 4, SECT_4K) }, 930 { "at45db021d", INFO(0x1f2300, 0, 64 * 1024, 8, SECT_4K) }, 931 { "at45db041d", INFO(0x1f2400, 0, 64 * 1024, 8, SECT_4K) }, 932 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 933 { "at45db161d", INFO(0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, 934 { "at45db321d", INFO(0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, 935 { "at45db641d", INFO(0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, 936 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 937 #endif 938 #ifdef CONFIG_SPI_FLASH_EON /* EON */ 939 /* EON -- en25xxx */ 940 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, 941 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 942 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, 943 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, 944 #endif 945 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ 946 /* GigaDevice */ 947 { 948 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32, 949 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 950 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 951 }, 952 { 953 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, 954 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 955 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 956 }, 957 { 958 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64, 959 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 960 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 961 }, 962 { 963 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, 964 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 965 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 966 }, 967 #endif 968 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ 969 /* ISSI */ 970 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8, 971 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 972 { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64, 0) }, 973 { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128, 0) }, 974 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256, 975 SECT_4K | SPI_NOR_DUAL_READ) }, 976 { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512, 977 SECT_4K | SPI_NOR_DUAL_READ) }, 978 { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64, 979 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 980 { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128, 981 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 982 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256, 983 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 984 #endif 985 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ 986 /* Macronix */ 987 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 988 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 989 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, 990 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 991 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) }, 992 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) }, 993 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) }, 994 { "mx25u1635e", INFO(0xc22535, 0, 64 * 1024, 32, SECT_4K) }, 995 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 996 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, 997 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, 998 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 999 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, 1000 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, 1001 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 1002 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 1003 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1004 { "mx25l1633e", INFO(0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, 1005 #endif 1006 1007 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 1008 /* Micron */ 1009 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, 1010 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 1011 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 1012 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 1013 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 1014 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 1015 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 1016 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1017 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, 1018 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 1019 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 1020 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 1021 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 1022 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 1023 #endif 1024 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ 1025 /* Spansion/Cypress -- single (large) sector size only, at least 1026 * for the chips listed here (without boot sectors). 1027 */ 1028 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1029 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1030 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) }, 1031 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1032 { "s25fl512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1033 { "s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1034 { "s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1035 { "s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1036 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, 1037 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, 1038 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1039 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1040 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1041 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, 1042 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, 1043 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, 1044 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, 1045 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1046 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, 1047 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, 1048 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 1049 #endif 1050 #ifdef CONFIG_SPI_FLASH_SST /* SST */ 1051 /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 1052 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 1053 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 1054 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, 1055 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, 1056 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, 1057 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, 1058 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, 1059 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, 1060 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, 1061 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, 1062 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 1063 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 1064 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1065 { "sst26wf016", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K) }, 1066 { "sst26wf032", INFO(0xbf2622, 0, 64 * 1024, 64, SECT_4K) }, 1067 { "sst26wf064", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K) }, 1068 #endif 1069 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 1070 /* ST Microelectronics -- newer production may have feature updates */ 1071 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, 1072 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, 1073 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, 1074 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, 1075 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, 1076 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, 1077 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, 1078 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, 1079 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, 1080 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1081 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, 1082 #endif 1083 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ 1084 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 1085 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 1086 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, 1087 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, 1088 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 1089 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, 1090 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 1091 { 1092 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32, 1093 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1094 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1095 }, 1096 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 1097 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 1098 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 1099 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 1100 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, 1101 { 1102 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, 1103 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1104 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1105 }, 1106 { 1107 "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64, 1108 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1109 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1110 }, 1111 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 1112 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, 1113 { 1114 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, 1115 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1116 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1117 }, 1118 { 1119 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, 1120 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1121 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1122 }, 1123 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 1124 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, 1125 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, 1126 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1127 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, 1128 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, 1129 #endif 1130 #ifdef CONFIG_SPI_FLASH_XMC 1131 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 1132 { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1133 { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1134 #endif 1135 { }, 1136 }; 1137 1138 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 1139 { 1140 int tmp; 1141 u8 id[SPI_NOR_MAX_ID_LEN]; 1142 const struct flash_info *info; 1143 1144 if (!ARRAY_SIZE(spi_nor_ids)) 1145 return ERR_PTR(-ENODEV); 1146 1147 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); 1148 if (tmp < 0) { 1149 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); 1150 return ERR_PTR(tmp); 1151 } 1152 1153 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { 1154 info = &spi_nor_ids[tmp]; 1155 if (info->id_len) { 1156 if (!memcmp(info->id, id, info->id_len)) 1157 return &spi_nor_ids[tmp]; 1158 } 1159 } 1160 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", 1161 id[0], id[1], id[2]); 1162 return ERR_PTR(-ENODEV); 1163 } 1164 1165 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 1166 size_t *retlen, u_char *buf) 1167 { 1168 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1169 int ret; 1170 1171 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 1172 1173 while (len) { 1174 loff_t addr = from; 1175 size_t read_len = len; 1176 1177 #ifdef CONFIG_SPI_FLASH_BAR 1178 u32 remain_len; 1179 1180 ret = write_bar(nor, addr); 1181 if (ret < 0) 1182 return log_ret(ret); 1183 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr; 1184 1185 if (len < remain_len) 1186 read_len = len; 1187 else 1188 read_len = remain_len; 1189 #endif 1190 1191 ret = nor->read(nor, addr, read_len, buf); 1192 if (ret == 0) { 1193 /* We shouldn't see 0-length reads */ 1194 ret = -EIO; 1195 goto read_err; 1196 } 1197 if (ret < 0) 1198 goto read_err; 1199 1200 *retlen += ret; 1201 buf += ret; 1202 from += ret; 1203 len -= ret; 1204 } 1205 ret = 0; 1206 1207 read_err: 1208 #ifdef CONFIG_SPI_FLASH_BAR 1209 ret = clean_bar(nor); 1210 #endif 1211 return ret; 1212 } 1213 1214 #ifdef CONFIG_SPI_FLASH_SST 1215 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len, 1216 size_t *retlen, const u_char *buf) 1217 { 1218 size_t actual; 1219 int ret = 0; 1220 1221 for (actual = 0; actual < len; actual++) { 1222 nor->program_opcode = SPINOR_OP_BP; 1223 1224 write_enable(nor); 1225 /* write one byte. */ 1226 ret = nor->write(nor, to, 1, buf + actual); 1227 if (ret < 0) 1228 goto sst_write_err; 1229 ret = spi_nor_wait_till_ready(nor); 1230 if (ret) 1231 goto sst_write_err; 1232 to++; 1233 } 1234 1235 sst_write_err: 1236 write_disable(nor); 1237 return ret; 1238 } 1239 1240 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, 1241 size_t *retlen, const u_char *buf) 1242 { 1243 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1244 struct spi_slave *spi = nor->spi; 1245 size_t actual; 1246 int ret; 1247 1248 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 1249 if (spi->mode & SPI_TX_BYTE) 1250 return sst_write_byteprogram(nor, to, len, retlen, buf); 1251 1252 write_enable(nor); 1253 1254 nor->sst_write_second = false; 1255 1256 actual = to % 2; 1257 /* Start write from odd address. */ 1258 if (actual) { 1259 nor->program_opcode = SPINOR_OP_BP; 1260 1261 /* write one byte. */ 1262 ret = nor->write(nor, to, 1, buf); 1263 if (ret < 0) 1264 goto sst_write_err; 1265 ret = spi_nor_wait_till_ready(nor); 1266 if (ret) 1267 goto sst_write_err; 1268 } 1269 to += actual; 1270 1271 /* Write out most of the data here. */ 1272 for (; actual < len - 1; actual += 2) { 1273 nor->program_opcode = SPINOR_OP_AAI_WP; 1274 1275 /* write two bytes. */ 1276 ret = nor->write(nor, to, 2, buf + actual); 1277 if (ret < 0) 1278 goto sst_write_err; 1279 ret = spi_nor_wait_till_ready(nor); 1280 if (ret) 1281 goto sst_write_err; 1282 to += 2; 1283 nor->sst_write_second = true; 1284 } 1285 nor->sst_write_second = false; 1286 1287 write_disable(nor); 1288 ret = spi_nor_wait_till_ready(nor); 1289 if (ret) 1290 goto sst_write_err; 1291 1292 /* Write out trailing byte if it exists. */ 1293 if (actual != len) { 1294 write_enable(nor); 1295 1296 nor->program_opcode = SPINOR_OP_BP; 1297 ret = nor->write(nor, to, 1, buf + actual); 1298 if (ret < 0) 1299 goto sst_write_err; 1300 ret = spi_nor_wait_till_ready(nor); 1301 if (ret) 1302 goto sst_write_err; 1303 write_disable(nor); 1304 actual += 1; 1305 } 1306 sst_write_err: 1307 *retlen += actual; 1308 return ret; 1309 } 1310 #endif 1311 /* 1312 * Write an address range to the nor chip. Data must be written in 1313 * FLASH_PAGESIZE chunks. The address range may be any size provided 1314 * it is within the physical boundaries. 1315 */ 1316 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 1317 size_t *retlen, const u_char *buf) 1318 { 1319 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1320 size_t page_offset, page_remain, i; 1321 ssize_t ret; 1322 1323 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 1324 1325 for (i = 0; i < len; ) { 1326 ssize_t written; 1327 loff_t addr = to + i; 1328 1329 /* 1330 * If page_size is a power of two, the offset can be quickly 1331 * calculated with an AND operation. On the other cases we 1332 * need to do a modulus operation (more expensive). 1333 * Power of two numbers have only one bit set and we can use 1334 * the instruction hweight32 to detect if we need to do a 1335 * modulus (do_div()) or not. 1336 */ 1337 if (hweight32(nor->page_size) == 1) { 1338 page_offset = addr & (nor->page_size - 1); 1339 } else { 1340 u64 aux = addr; 1341 1342 page_offset = do_div(aux, nor->page_size); 1343 } 1344 /* the size of data remaining on the first page */ 1345 page_remain = min_t(size_t, 1346 nor->page_size - page_offset, len - i); 1347 1348 #ifdef CONFIG_SPI_FLASH_BAR 1349 ret = write_bar(nor, addr); 1350 if (ret < 0) 1351 return ret; 1352 #endif 1353 write_enable(nor); 1354 ret = nor->write(nor, addr, page_remain, buf + i); 1355 if (ret < 0) 1356 goto write_err; 1357 written = ret; 1358 1359 ret = spi_nor_wait_till_ready(nor); 1360 if (ret) 1361 goto write_err; 1362 *retlen += written; 1363 i += written; 1364 if (written != page_remain) { 1365 ret = -EIO; 1366 goto write_err; 1367 } 1368 } 1369 1370 write_err: 1371 #ifdef CONFIG_SPI_FLASH_BAR 1372 ret = clean_bar(nor); 1373 #endif 1374 return ret; 1375 } 1376 1377 #ifdef CONFIG_SPI_FLASH_MACRONIX 1378 /** 1379 * macronix_quad_enable() - set QE bit in Status Register. 1380 * @nor: pointer to a 'struct spi_nor' 1381 * 1382 * Set the Quad Enable (QE) bit in the Status Register. 1383 * 1384 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. 1385 * 1386 * Return: 0 on success, -errno otherwise. 1387 */ 1388 static int macronix_quad_enable(struct spi_nor *nor) 1389 { 1390 int ret, val; 1391 1392 val = read_sr(nor); 1393 if (val < 0) 1394 return val; 1395 if (val & SR_QUAD_EN_MX) 1396 return 0; 1397 1398 write_enable(nor); 1399 1400 write_sr(nor, val | SR_QUAD_EN_MX); 1401 1402 ret = spi_nor_wait_till_ready(nor); 1403 if (ret) 1404 return ret; 1405 1406 ret = read_sr(nor); 1407 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { 1408 dev_err(nor->dev, "Macronix Quad bit not set\n"); 1409 return -EINVAL; 1410 } 1411 1412 return 0; 1413 } 1414 #endif 1415 1416 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1417 /* 1418 * Write status Register and configuration register with 2 bytes 1419 * The first byte will be written to the status register, while the 1420 * second byte will be written to the configuration register. 1421 * Return negative if error occurred. 1422 */ 1423 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) 1424 { 1425 int ret; 1426 1427 write_enable(nor); 1428 1429 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2); 1430 if (ret < 0) { 1431 dev_dbg(nor->dev, 1432 "error while writing configuration register\n"); 1433 return -EINVAL; 1434 } 1435 1436 ret = spi_nor_wait_till_ready(nor); 1437 if (ret) { 1438 dev_dbg(nor->dev, 1439 "timeout while writing configuration register\n"); 1440 return ret; 1441 } 1442 1443 return 0; 1444 } 1445 1446 /** 1447 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. 1448 * @nor: pointer to a 'struct spi_nor' 1449 * 1450 * Set the Quad Enable (QE) bit in the Configuration Register. 1451 * This function should be used with QSPI memories supporting the Read 1452 * Configuration Register (35h) instruction. 1453 * 1454 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1455 * memories. 1456 * 1457 * Return: 0 on success, -errno otherwise. 1458 */ 1459 static int spansion_read_cr_quad_enable(struct spi_nor *nor) 1460 { 1461 u8 sr_cr[2]; 1462 int ret; 1463 1464 /* Check current Quad Enable bit value. */ 1465 ret = read_cr(nor); 1466 if (ret < 0) { 1467 dev_dbg(dev, "error while reading configuration register\n"); 1468 return -EINVAL; 1469 } 1470 1471 if (ret & CR_QUAD_EN_SPAN) 1472 return 0; 1473 1474 sr_cr[1] = ret | CR_QUAD_EN_SPAN; 1475 1476 /* Keep the current value of the Status Register. */ 1477 ret = read_sr(nor); 1478 if (ret < 0) { 1479 dev_dbg(dev, "error while reading status register\n"); 1480 return -EINVAL; 1481 } 1482 sr_cr[0] = ret; 1483 1484 ret = write_sr_cr(nor, sr_cr); 1485 if (ret) 1486 return ret; 1487 1488 /* Read back and check it. */ 1489 ret = read_cr(nor); 1490 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { 1491 dev_dbg(nor->dev, "Spansion Quad bit not set\n"); 1492 return -EINVAL; 1493 } 1494 1495 return 0; 1496 } 1497 1498 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1499 /** 1500 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register. 1501 * @nor: pointer to a 'struct spi_nor' 1502 * 1503 * Set the Quad Enable (QE) bit in the Configuration Register. 1504 * This function should be used with QSPI memories not supporting the Read 1505 * Configuration Register (35h) instruction. 1506 * 1507 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1508 * memories. 1509 * 1510 * Return: 0 on success, -errno otherwise. 1511 */ 1512 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) 1513 { 1514 u8 sr_cr[2]; 1515 int ret; 1516 1517 /* Keep the current value of the Status Register. */ 1518 ret = read_sr(nor); 1519 if (ret < 0) { 1520 dev_dbg(nor->dev, "error while reading status register\n"); 1521 return -EINVAL; 1522 } 1523 sr_cr[0] = ret; 1524 sr_cr[1] = CR_QUAD_EN_SPAN; 1525 1526 return write_sr_cr(nor, sr_cr); 1527 } 1528 1529 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */ 1530 #endif /* CONFIG_SPI_FLASH_SPANSION */ 1531 1532 struct spi_nor_read_command { 1533 u8 num_mode_clocks; 1534 u8 num_wait_states; 1535 u8 opcode; 1536 enum spi_nor_protocol proto; 1537 }; 1538 1539 struct spi_nor_pp_command { 1540 u8 opcode; 1541 enum spi_nor_protocol proto; 1542 }; 1543 1544 enum spi_nor_read_command_index { 1545 SNOR_CMD_READ, 1546 SNOR_CMD_READ_FAST, 1547 SNOR_CMD_READ_1_1_1_DTR, 1548 1549 /* Dual SPI */ 1550 SNOR_CMD_READ_1_1_2, 1551 SNOR_CMD_READ_1_2_2, 1552 SNOR_CMD_READ_2_2_2, 1553 SNOR_CMD_READ_1_2_2_DTR, 1554 1555 /* Quad SPI */ 1556 SNOR_CMD_READ_1_1_4, 1557 SNOR_CMD_READ_1_4_4, 1558 SNOR_CMD_READ_4_4_4, 1559 SNOR_CMD_READ_1_4_4_DTR, 1560 1561 /* Octo SPI */ 1562 SNOR_CMD_READ_1_1_8, 1563 SNOR_CMD_READ_1_8_8, 1564 SNOR_CMD_READ_8_8_8, 1565 SNOR_CMD_READ_1_8_8_DTR, 1566 1567 SNOR_CMD_READ_MAX 1568 }; 1569 1570 enum spi_nor_pp_command_index { 1571 SNOR_CMD_PP, 1572 1573 /* Quad SPI */ 1574 SNOR_CMD_PP_1_1_4, 1575 SNOR_CMD_PP_1_4_4, 1576 SNOR_CMD_PP_4_4_4, 1577 1578 /* Octo SPI */ 1579 SNOR_CMD_PP_1_1_8, 1580 SNOR_CMD_PP_1_8_8, 1581 SNOR_CMD_PP_8_8_8, 1582 1583 SNOR_CMD_PP_MAX 1584 }; 1585 1586 struct spi_nor_flash_parameter { 1587 u64 size; 1588 u32 page_size; 1589 1590 struct spi_nor_hwcaps hwcaps; 1591 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; 1592 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; 1593 1594 int (*quad_enable)(struct spi_nor *nor); 1595 }; 1596 1597 static void 1598 spi_nor_set_read_settings(struct spi_nor_read_command *read, 1599 u8 num_mode_clocks, 1600 u8 num_wait_states, 1601 u8 opcode, 1602 enum spi_nor_protocol proto) 1603 { 1604 read->num_mode_clocks = num_mode_clocks; 1605 read->num_wait_states = num_wait_states; 1606 read->opcode = opcode; 1607 read->proto = proto; 1608 } 1609 1610 static void 1611 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, 1612 u8 opcode, 1613 enum spi_nor_protocol proto) 1614 { 1615 pp->opcode = opcode; 1616 pp->proto = proto; 1617 } 1618 1619 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1620 /* 1621 * Serial Flash Discoverable Parameters (SFDP) parsing. 1622 */ 1623 1624 /** 1625 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters. 1626 * @nor: pointer to a 'struct spi_nor' 1627 * @addr: offset in the SFDP area to start reading data from 1628 * @len: number of bytes to read 1629 * @buf: buffer where the SFDP data are copied into (dma-safe memory) 1630 * 1631 * Whatever the actual numbers of bytes for address and dummy cycles are 1632 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always 1633 * followed by a 3-byte address and 8 dummy clock cycles. 1634 * 1635 * Return: 0 on success, -errno otherwise. 1636 */ 1637 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr, 1638 size_t len, void *buf) 1639 { 1640 u8 addr_width, read_opcode, read_dummy; 1641 int ret; 1642 1643 read_opcode = nor->read_opcode; 1644 addr_width = nor->addr_width; 1645 read_dummy = nor->read_dummy; 1646 1647 nor->read_opcode = SPINOR_OP_RDSFDP; 1648 nor->addr_width = 3; 1649 nor->read_dummy = 8; 1650 1651 while (len) { 1652 ret = nor->read(nor, addr, len, (u8 *)buf); 1653 if (!ret || ret > len) { 1654 ret = -EIO; 1655 goto read_err; 1656 } 1657 if (ret < 0) 1658 goto read_err; 1659 1660 buf += ret; 1661 addr += ret; 1662 len -= ret; 1663 } 1664 ret = 0; 1665 1666 read_err: 1667 nor->read_opcode = read_opcode; 1668 nor->addr_width = addr_width; 1669 nor->read_dummy = read_dummy; 1670 1671 return ret; 1672 } 1673 1674 struct sfdp_parameter_header { 1675 u8 id_lsb; 1676 u8 minor; 1677 u8 major; 1678 u8 length; /* in double words */ 1679 u8 parameter_table_pointer[3]; /* byte address */ 1680 u8 id_msb; 1681 }; 1682 1683 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) 1684 #define SFDP_PARAM_HEADER_PTP(p) \ 1685 (((p)->parameter_table_pointer[2] << 16) | \ 1686 ((p)->parameter_table_pointer[1] << 8) | \ 1687 ((p)->parameter_table_pointer[0] << 0)) 1688 1689 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ 1690 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ 1691 1692 #define SFDP_SIGNATURE 0x50444653U 1693 #define SFDP_JESD216_MAJOR 1 1694 #define SFDP_JESD216_MINOR 0 1695 #define SFDP_JESD216A_MINOR 5 1696 #define SFDP_JESD216B_MINOR 6 1697 1698 struct sfdp_header { 1699 u32 signature; /* Ox50444653U <=> "SFDP" */ 1700 u8 minor; 1701 u8 major; 1702 u8 nph; /* 0-base number of parameter headers */ 1703 u8 unused; 1704 1705 /* Basic Flash Parameter Table. */ 1706 struct sfdp_parameter_header bfpt_header; 1707 }; 1708 1709 /* Basic Flash Parameter Table */ 1710 1711 /* 1712 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. 1713 * They are indexed from 1 but C arrays are indexed from 0. 1714 */ 1715 #define BFPT_DWORD(i) ((i) - 1) 1716 #define BFPT_DWORD_MAX 16 1717 1718 /* The first version of JESB216 defined only 9 DWORDs. */ 1719 #define BFPT_DWORD_MAX_JESD216 9 1720 1721 /* 1st DWORD. */ 1722 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) 1723 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) 1724 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) 1725 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) 1726 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) 1727 #define BFPT_DWORD1_DTR BIT(19) 1728 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) 1729 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) 1730 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) 1731 1732 /* 5th DWORD. */ 1733 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) 1734 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) 1735 1736 /* 11th DWORD. */ 1737 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 1738 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) 1739 1740 /* 15th DWORD. */ 1741 1742 /* 1743 * (from JESD216 rev B) 1744 * Quad Enable Requirements (QER): 1745 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 1746 * reads based on instruction. DQ3/HOLD# functions are hold during 1747 * instruction phase. 1748 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with 1749 * two data bytes where bit 1 of the second byte is one. 1750 * [...] 1751 * Writing only one byte to the status register has the side-effect of 1752 * clearing status register 2, including the QE bit. The 100b code is 1753 * used if writing one byte to the status register does not modify 1754 * status register 2. 1755 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with 1756 * one data byte where bit 6 is one. 1757 * [...] 1758 * - 011b: QE is bit 7 of status register 2. It is set via Write status 1759 * register 2 instruction 3Eh with one data byte where bit 7 is one. 1760 * [...] 1761 * The status register 2 is read using instruction 3Fh. 1762 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with 1763 * two data bytes where bit 1 of the second byte is one. 1764 * [...] 1765 * In contrast to the 001b code, writing one byte to the status 1766 * register does not modify status register 2. 1767 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using 1768 * Read Status instruction 05h. Status register2 is read using 1769 * instruction 35h. QE is set via Writ Status instruction 01h with 1770 * two data bytes where bit 1 of the second byte is one. 1771 * [...] 1772 */ 1773 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) 1774 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ 1775 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) 1776 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ 1777 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) 1778 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) 1779 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ 1780 1781 struct sfdp_bfpt { 1782 u32 dwords[BFPT_DWORD_MAX]; 1783 }; 1784 1785 /* Fast Read settings. */ 1786 1787 static void 1788 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read, 1789 u16 half, 1790 enum spi_nor_protocol proto) 1791 { 1792 read->num_mode_clocks = (half >> 5) & 0x07; 1793 read->num_wait_states = (half >> 0) & 0x1f; 1794 read->opcode = (half >> 8) & 0xff; 1795 read->proto = proto; 1796 } 1797 1798 struct sfdp_bfpt_read { 1799 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */ 1800 u32 hwcaps; 1801 1802 /* 1803 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us 1804 * whether the Fast Read x-y-z command is supported. 1805 */ 1806 u32 supported_dword; 1807 u32 supported_bit; 1808 1809 /* 1810 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD 1811 * encodes the op code, the number of mode clocks and the number of wait 1812 * states to be used by Fast Read x-y-z command. 1813 */ 1814 u32 settings_dword; 1815 u32 settings_shift; 1816 1817 /* The SPI protocol for this Fast Read x-y-z command. */ 1818 enum spi_nor_protocol proto; 1819 }; 1820 1821 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = { 1822 /* Fast Read 1-1-2 */ 1823 { 1824 SNOR_HWCAPS_READ_1_1_2, 1825 BFPT_DWORD(1), BIT(16), /* Supported bit */ 1826 BFPT_DWORD(4), 0, /* Settings */ 1827 SNOR_PROTO_1_1_2, 1828 }, 1829 1830 /* Fast Read 1-2-2 */ 1831 { 1832 SNOR_HWCAPS_READ_1_2_2, 1833 BFPT_DWORD(1), BIT(20), /* Supported bit */ 1834 BFPT_DWORD(4), 16, /* Settings */ 1835 SNOR_PROTO_1_2_2, 1836 }, 1837 1838 /* Fast Read 2-2-2 */ 1839 { 1840 SNOR_HWCAPS_READ_2_2_2, 1841 BFPT_DWORD(5), BIT(0), /* Supported bit */ 1842 BFPT_DWORD(6), 16, /* Settings */ 1843 SNOR_PROTO_2_2_2, 1844 }, 1845 1846 /* Fast Read 1-1-4 */ 1847 { 1848 SNOR_HWCAPS_READ_1_1_4, 1849 BFPT_DWORD(1), BIT(22), /* Supported bit */ 1850 BFPT_DWORD(3), 16, /* Settings */ 1851 SNOR_PROTO_1_1_4, 1852 }, 1853 1854 /* Fast Read 1-4-4 */ 1855 { 1856 SNOR_HWCAPS_READ_1_4_4, 1857 BFPT_DWORD(1), BIT(21), /* Supported bit */ 1858 BFPT_DWORD(3), 0, /* Settings */ 1859 SNOR_PROTO_1_4_4, 1860 }, 1861 1862 /* Fast Read 4-4-4 */ 1863 { 1864 SNOR_HWCAPS_READ_4_4_4, 1865 BFPT_DWORD(5), BIT(4), /* Supported bit */ 1866 BFPT_DWORD(7), 16, /* Settings */ 1867 SNOR_PROTO_4_4_4, 1868 }, 1869 }; 1870 1871 struct sfdp_bfpt_erase { 1872 /* 1873 * The half-word at offset <shift> in DWORD <dwoard> encodes the 1874 * op code and erase sector size to be used by Sector Erase commands. 1875 */ 1876 u32 dword; 1877 u32 shift; 1878 }; 1879 1880 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = { 1881 /* Erase Type 1 in DWORD8 bits[15:0] */ 1882 {BFPT_DWORD(8), 0}, 1883 1884 /* Erase Type 2 in DWORD8 bits[31:16] */ 1885 {BFPT_DWORD(8), 16}, 1886 1887 /* Erase Type 3 in DWORD9 bits[15:0] */ 1888 {BFPT_DWORD(9), 0}, 1889 1890 /* Erase Type 4 in DWORD9 bits[31:16] */ 1891 {BFPT_DWORD(9), 16}, 1892 }; 1893 1894 static int spi_nor_hwcaps_read2cmd(u32 hwcaps); 1895 1896 /** 1897 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table. 1898 * @nor: pointer to a 'struct spi_nor' 1899 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing 1900 * the Basic Flash Parameter Table length and version 1901 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 1902 * filled 1903 * 1904 * The Basic Flash Parameter Table is the main and only mandatory table as 1905 * defined by the SFDP (JESD216) specification. 1906 * It provides us with the total size (memory density) of the data array and 1907 * the number of address bytes for Fast Read, Page Program and Sector Erase 1908 * commands. 1909 * For Fast READ commands, it also gives the number of mode clock cycles and 1910 * wait states (regrouped in the number of dummy clock cycles) for each 1911 * supported instruction op code. 1912 * For Page Program, the page size is now available since JESD216 rev A, however 1913 * the supported instruction op codes are still not provided. 1914 * For Sector Erase commands, this table stores the supported instruction op 1915 * codes and the associated sector sizes. 1916 * Finally, the Quad Enable Requirements (QER) are also available since JESD216 1917 * rev A. The QER bits encode the manufacturer dependent procedure to be 1918 * executed to set the Quad Enable (QE) bit in some internal register of the 1919 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before 1920 * sending any Quad SPI command to the memory. Actually, setting the QE bit 1921 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2 1922 * and IO3 hence enabling 4 (Quad) I/O lines. 1923 * 1924 * Return: 0 on success, -errno otherwise. 1925 */ 1926 static int spi_nor_parse_bfpt(struct spi_nor *nor, 1927 const struct sfdp_parameter_header *bfpt_header, 1928 struct spi_nor_flash_parameter *params) 1929 { 1930 struct mtd_info *mtd = &nor->mtd; 1931 struct sfdp_bfpt bfpt; 1932 size_t len; 1933 int i, cmd, err; 1934 u32 addr; 1935 u16 half; 1936 1937 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */ 1938 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216) 1939 return -EINVAL; 1940 1941 /* Read the Basic Flash Parameter Table. */ 1942 len = min_t(size_t, sizeof(bfpt), 1943 bfpt_header->length * sizeof(u32)); 1944 addr = SFDP_PARAM_HEADER_PTP(bfpt_header); 1945 memset(&bfpt, 0, sizeof(bfpt)); 1946 err = spi_nor_read_sfdp(nor, addr, len, &bfpt); 1947 if (err < 0) 1948 return err; 1949 1950 /* Fix endianness of the BFPT DWORDs. */ 1951 for (i = 0; i < BFPT_DWORD_MAX; i++) 1952 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]); 1953 1954 /* Number of address bytes. */ 1955 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) { 1956 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: 1957 nor->addr_width = 3; 1958 break; 1959 1960 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: 1961 nor->addr_width = 4; 1962 break; 1963 1964 default: 1965 break; 1966 } 1967 1968 /* Flash Memory Density (in bits). */ 1969 params->size = bfpt.dwords[BFPT_DWORD(2)]; 1970 if (params->size & BIT(31)) { 1971 params->size &= ~BIT(31); 1972 1973 /* 1974 * Prevent overflows on params->size. Anyway, a NOR of 2^64 1975 * bits is unlikely to exist so this error probably means 1976 * the BFPT we are reading is corrupted/wrong. 1977 */ 1978 if (params->size > 63) 1979 return -EINVAL; 1980 1981 params->size = 1ULL << params->size; 1982 } else { 1983 params->size++; 1984 } 1985 params->size >>= 3; /* Convert to bytes. */ 1986 1987 /* Fast Read settings. */ 1988 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) { 1989 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i]; 1990 struct spi_nor_read_command *read; 1991 1992 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) { 1993 params->hwcaps.mask &= ~rd->hwcaps; 1994 continue; 1995 } 1996 1997 params->hwcaps.mask |= rd->hwcaps; 1998 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps); 1999 read = ¶ms->reads[cmd]; 2000 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift; 2001 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto); 2002 } 2003 2004 /* Sector Erase settings. */ 2005 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) { 2006 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i]; 2007 u32 erasesize; 2008 u8 opcode; 2009 2010 half = bfpt.dwords[er->dword] >> er->shift; 2011 erasesize = half & 0xff; 2012 2013 /* erasesize == 0 means this Erase Type is not supported. */ 2014 if (!erasesize) 2015 continue; 2016 2017 erasesize = 1U << erasesize; 2018 opcode = (half >> 8) & 0xff; 2019 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS 2020 if (erasesize == SZ_4K) { 2021 nor->erase_opcode = opcode; 2022 mtd->erasesize = erasesize; 2023 break; 2024 } 2025 #endif 2026 if (!mtd->erasesize || mtd->erasesize < erasesize) { 2027 nor->erase_opcode = opcode; 2028 mtd->erasesize = erasesize; 2029 } 2030 } 2031 2032 /* Stop here if not JESD216 rev A or later. */ 2033 if (bfpt_header->length < BFPT_DWORD_MAX) 2034 return 0; 2035 2036 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */ 2037 params->page_size = bfpt.dwords[BFPT_DWORD(11)]; 2038 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK; 2039 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT; 2040 params->page_size = 1U << params->page_size; 2041 2042 /* Quad Enable Requirements. */ 2043 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { 2044 case BFPT_DWORD15_QER_NONE: 2045 params->quad_enable = NULL; 2046 break; 2047 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 2048 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: 2049 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: 2050 params->quad_enable = spansion_no_read_cr_quad_enable; 2051 break; 2052 #endif 2053 #ifdef CONFIG_SPI_FLASH_MACRONIX 2054 case BFPT_DWORD15_QER_SR1_BIT6: 2055 params->quad_enable = macronix_quad_enable; 2056 break; 2057 #endif 2058 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 2059 case BFPT_DWORD15_QER_SR2_BIT1: 2060 params->quad_enable = spansion_read_cr_quad_enable; 2061 break; 2062 #endif 2063 default: 2064 return -EINVAL; 2065 } 2066 2067 return 0; 2068 } 2069 2070 /** 2071 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters. 2072 * @nor: pointer to a 'struct spi_nor' 2073 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 2074 * filled 2075 * 2076 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216 2077 * specification. This is a standard which tends to supported by almost all 2078 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at 2079 * runtime the main parameters needed to perform basic SPI flash operations such 2080 * as Fast Read, Page Program or Sector Erase commands. 2081 * 2082 * Return: 0 on success, -errno otherwise. 2083 */ 2084 static int spi_nor_parse_sfdp(struct spi_nor *nor, 2085 struct spi_nor_flash_parameter *params) 2086 { 2087 const struct sfdp_parameter_header *param_header, *bfpt_header; 2088 struct sfdp_parameter_header *param_headers = NULL; 2089 struct sfdp_header header; 2090 size_t psize; 2091 int i, err; 2092 2093 /* Get the SFDP header. */ 2094 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header); 2095 if (err < 0) 2096 return err; 2097 2098 /* Check the SFDP header version. */ 2099 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE || 2100 header.major != SFDP_JESD216_MAJOR) 2101 return -EINVAL; 2102 2103 /* 2104 * Verify that the first and only mandatory parameter header is a 2105 * Basic Flash Parameter Table header as specified in JESD216. 2106 */ 2107 bfpt_header = &header.bfpt_header; 2108 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID || 2109 bfpt_header->major != SFDP_JESD216_MAJOR) 2110 return -EINVAL; 2111 2112 /* 2113 * Allocate memory then read all parameter headers with a single 2114 * Read SFDP command. These parameter headers will actually be parsed 2115 * twice: a first time to get the latest revision of the basic flash 2116 * parameter table, then a second time to handle the supported optional 2117 * tables. 2118 * Hence we read the parameter headers once for all to reduce the 2119 * processing time. Also we use kmalloc() instead of devm_kmalloc() 2120 * because we don't need to keep these parameter headers: the allocated 2121 * memory is always released with kfree() before exiting this function. 2122 */ 2123 if (header.nph) { 2124 psize = header.nph * sizeof(*param_headers); 2125 2126 param_headers = kmalloc(psize, GFP_KERNEL); 2127 if (!param_headers) 2128 return -ENOMEM; 2129 2130 err = spi_nor_read_sfdp(nor, sizeof(header), 2131 psize, param_headers); 2132 if (err < 0) { 2133 dev_err(dev, "failed to read SFDP parameter headers\n"); 2134 goto exit; 2135 } 2136 } 2137 2138 /* 2139 * Check other parameter headers to get the latest revision of 2140 * the basic flash parameter table. 2141 */ 2142 for (i = 0; i < header.nph; i++) { 2143 param_header = ¶m_headers[i]; 2144 2145 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID && 2146 param_header->major == SFDP_JESD216_MAJOR && 2147 (param_header->minor > bfpt_header->minor || 2148 (param_header->minor == bfpt_header->minor && 2149 param_header->length > bfpt_header->length))) 2150 bfpt_header = param_header; 2151 } 2152 2153 err = spi_nor_parse_bfpt(nor, bfpt_header, params); 2154 if (err) 2155 goto exit; 2156 2157 /* Parse other parameter headers. */ 2158 for (i = 0; i < header.nph; i++) { 2159 param_header = ¶m_headers[i]; 2160 2161 switch (SFDP_PARAM_HEADER_ID(param_header)) { 2162 case SFDP_SECTOR_MAP_ID: 2163 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n"); 2164 break; 2165 2166 default: 2167 break; 2168 } 2169 2170 if (err) 2171 goto exit; 2172 } 2173 2174 exit: 2175 kfree(param_headers); 2176 return err; 2177 } 2178 #else 2179 static int spi_nor_parse_sfdp(struct spi_nor *nor, 2180 struct spi_nor_flash_parameter *params) 2181 { 2182 return -EINVAL; 2183 } 2184 #endif /* SPI_FLASH_SFDP_SUPPORT */ 2185 2186 static int spi_nor_init_params(struct spi_nor *nor, 2187 const struct flash_info *info, 2188 struct spi_nor_flash_parameter *params) 2189 { 2190 /* Set legacy flash parameters as default. */ 2191 memset(params, 0, sizeof(*params)); 2192 2193 /* Set SPI NOR sizes. */ 2194 params->size = info->sector_size * info->n_sectors; 2195 params->page_size = info->page_size; 2196 2197 /* (Fast) Read settings. */ 2198 params->hwcaps.mask |= SNOR_HWCAPS_READ; 2199 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 2200 0, 0, SPINOR_OP_READ, 2201 SNOR_PROTO_1_1_1); 2202 2203 if (!(info->flags & SPI_NOR_NO_FR)) { 2204 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 2205 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 2206 0, 8, SPINOR_OP_READ_FAST, 2207 SNOR_PROTO_1_1_1); 2208 } 2209 2210 if (info->flags & SPI_NOR_DUAL_READ) { 2211 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2212 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 2213 0, 8, SPINOR_OP_READ_1_1_2, 2214 SNOR_PROTO_1_1_2); 2215 } 2216 2217 if (info->flags & SPI_NOR_QUAD_READ) { 2218 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2219 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 2220 0, 8, SPINOR_OP_READ_1_1_4, 2221 SNOR_PROTO_1_1_4); 2222 } 2223 2224 /* Page Program settings. */ 2225 params->hwcaps.mask |= SNOR_HWCAPS_PP; 2226 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 2227 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 2228 2229 if (info->flags & SPI_NOR_QUAD_READ) { 2230 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; 2231 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], 2232 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4); 2233 } 2234 2235 /* Select the procedure to set the Quad Enable bit. */ 2236 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD | 2237 SNOR_HWCAPS_PP_QUAD)) { 2238 switch (JEDEC_MFR(info)) { 2239 #ifdef CONFIG_SPI_FLASH_MACRONIX 2240 case SNOR_MFR_MACRONIX: 2241 params->quad_enable = macronix_quad_enable; 2242 break; 2243 #endif 2244 case SNOR_MFR_ST: 2245 case SNOR_MFR_MICRON: 2246 break; 2247 2248 default: 2249 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 2250 /* Kept only for backward compatibility purpose. */ 2251 params->quad_enable = spansion_read_cr_quad_enable; 2252 #endif 2253 break; 2254 } 2255 } 2256 2257 /* Override the parameters with data read from SFDP tables. */ 2258 nor->addr_width = 0; 2259 nor->mtd.erasesize = 0; 2260 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) && 2261 !(info->flags & SPI_NOR_SKIP_SFDP)) { 2262 struct spi_nor_flash_parameter sfdp_params; 2263 2264 memcpy(&sfdp_params, params, sizeof(sfdp_params)); 2265 if (spi_nor_parse_sfdp(nor, &sfdp_params)) { 2266 nor->addr_width = 0; 2267 nor->mtd.erasesize = 0; 2268 } else { 2269 memcpy(params, &sfdp_params, sizeof(*params)); 2270 } 2271 } 2272 2273 return 0; 2274 } 2275 2276 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 2277 { 2278 size_t i; 2279 2280 for (i = 0; i < size; i++) 2281 if (table[i][0] == (int)hwcaps) 2282 return table[i][1]; 2283 2284 return -EINVAL; 2285 } 2286 2287 static int spi_nor_hwcaps_read2cmd(u32 hwcaps) 2288 { 2289 static const int hwcaps_read2cmd[][2] = { 2290 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 2291 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 2292 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 2293 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 2294 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 2295 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 2296 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 2297 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 2298 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 2299 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 2300 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 2301 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 2302 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 2303 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 2304 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 2305 }; 2306 2307 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 2308 ARRAY_SIZE(hwcaps_read2cmd)); 2309 } 2310 2311 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 2312 { 2313 static const int hwcaps_pp2cmd[][2] = { 2314 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 2315 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 2316 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 2317 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 2318 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 2319 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 2320 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 2321 }; 2322 2323 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 2324 ARRAY_SIZE(hwcaps_pp2cmd)); 2325 } 2326 2327 static int spi_nor_select_read(struct spi_nor *nor, 2328 const struct spi_nor_flash_parameter *params, 2329 u32 shared_hwcaps) 2330 { 2331 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2332 const struct spi_nor_read_command *read; 2333 2334 if (best_match < 0) 2335 return -EINVAL; 2336 2337 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2338 if (cmd < 0) 2339 return -EINVAL; 2340 2341 read = ¶ms->reads[cmd]; 2342 nor->read_opcode = read->opcode; 2343 nor->read_proto = read->proto; 2344 2345 /* 2346 * In the spi-nor framework, we don't need to make the difference 2347 * between mode clock cycles and wait state clock cycles. 2348 * Indeed, the value of the mode clock cycles is used by a QSPI 2349 * flash memory to know whether it should enter or leave its 0-4-4 2350 * (Continuous Read / XIP) mode. 2351 * eXecution In Place is out of the scope of the mtd sub-system. 2352 * Hence we choose to merge both mode and wait state clock cycles 2353 * into the so called dummy clock cycles. 2354 */ 2355 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2356 return 0; 2357 } 2358 2359 static int spi_nor_select_pp(struct spi_nor *nor, 2360 const struct spi_nor_flash_parameter *params, 2361 u32 shared_hwcaps) 2362 { 2363 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2364 const struct spi_nor_pp_command *pp; 2365 2366 if (best_match < 0) 2367 return -EINVAL; 2368 2369 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2370 if (cmd < 0) 2371 return -EINVAL; 2372 2373 pp = ¶ms->page_programs[cmd]; 2374 nor->program_opcode = pp->opcode; 2375 nor->write_proto = pp->proto; 2376 return 0; 2377 } 2378 2379 static int spi_nor_select_erase(struct spi_nor *nor, 2380 const struct flash_info *info) 2381 { 2382 struct mtd_info *mtd = &nor->mtd; 2383 2384 /* Do nothing if already configured from SFDP. */ 2385 if (mtd->erasesize) 2386 return 0; 2387 2388 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 2389 /* prefer "small sector" erase if possible */ 2390 if (info->flags & SECT_4K) { 2391 nor->erase_opcode = SPINOR_OP_BE_4K; 2392 mtd->erasesize = 4096; 2393 } else if (info->flags & SECT_4K_PMC) { 2394 nor->erase_opcode = SPINOR_OP_BE_4K_PMC; 2395 mtd->erasesize = 4096; 2396 } else 2397 #endif 2398 { 2399 nor->erase_opcode = SPINOR_OP_SE; 2400 mtd->erasesize = info->sector_size; 2401 } 2402 return 0; 2403 } 2404 2405 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, 2406 const struct spi_nor_flash_parameter *params, 2407 const struct spi_nor_hwcaps *hwcaps) 2408 { 2409 u32 ignored_mask, shared_mask; 2410 bool enable_quad_io; 2411 int err; 2412 2413 /* 2414 * Keep only the hardware capabilities supported by both the SPI 2415 * controller and the SPI flash memory. 2416 */ 2417 shared_mask = hwcaps->mask & params->hwcaps.mask; 2418 2419 /* SPI n-n-n protocols are not supported yet. */ 2420 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 | 2421 SNOR_HWCAPS_READ_4_4_4 | 2422 SNOR_HWCAPS_READ_8_8_8 | 2423 SNOR_HWCAPS_PP_4_4_4 | 2424 SNOR_HWCAPS_PP_8_8_8); 2425 if (shared_mask & ignored_mask) { 2426 dev_dbg(nor->dev, 2427 "SPI n-n-n protocols are not supported yet.\n"); 2428 shared_mask &= ~ignored_mask; 2429 } 2430 2431 /* Select the (Fast) Read command. */ 2432 err = spi_nor_select_read(nor, params, shared_mask); 2433 if (err) { 2434 dev_dbg(nor->dev, 2435 "can't select read settings supported by both the SPI controller and memory.\n"); 2436 return err; 2437 } 2438 2439 /* Select the Page Program command. */ 2440 err = spi_nor_select_pp(nor, params, shared_mask); 2441 if (err) { 2442 dev_dbg(nor->dev, 2443 "can't select write settings supported by both the SPI controller and memory.\n"); 2444 return err; 2445 } 2446 2447 /* Select the Sector Erase command. */ 2448 err = spi_nor_select_erase(nor, info); 2449 if (err) { 2450 dev_dbg(nor->dev, 2451 "can't select erase settings supported by both the SPI controller and memory.\n"); 2452 return err; 2453 } 2454 2455 /* Enable Quad I/O if needed. */ 2456 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 || 2457 spi_nor_get_protocol_width(nor->write_proto) == 4); 2458 if (enable_quad_io && params->quad_enable) 2459 nor->quad_enable = params->quad_enable; 2460 else 2461 nor->quad_enable = NULL; 2462 2463 return 0; 2464 } 2465 2466 static int spi_nor_init(struct spi_nor *nor) 2467 { 2468 int err; 2469 2470 /* 2471 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up 2472 * with the software protection bits set 2473 */ 2474 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || 2475 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || 2476 JEDEC_MFR(nor->info) == SNOR_MFR_SST || 2477 nor->info->flags & SPI_NOR_HAS_LOCK) { 2478 write_enable(nor); 2479 write_sr(nor, 0); 2480 spi_nor_wait_till_ready(nor); 2481 } 2482 2483 if (nor->quad_enable) { 2484 err = nor->quad_enable(nor); 2485 if (err) { 2486 dev_dbg(nor->dev, "quad mode not supported\n"); 2487 return err; 2488 } 2489 } 2490 2491 if (nor->addr_width == 4 && 2492 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) && 2493 !(nor->info->flags & SPI_NOR_4B_OPCODES)) { 2494 /* 2495 * If the RESET# pin isn't hooked up properly, or the system 2496 * otherwise doesn't perform a reset command in the boot 2497 * sequence, it's impossible to 100% protect against unexpected 2498 * reboots (e.g., crashes). Warn the user (or hopefully, system 2499 * designer) that this is bad. 2500 */ 2501 if (nor->flags & SNOR_F_BROKEN_RESET) 2502 printf("enabling reset hack; may not recover from unexpected reboots\n"); 2503 set_4byte(nor, nor->info, 1); 2504 } 2505 2506 return 0; 2507 } 2508 2509 int spi_nor_scan(struct spi_nor *nor) 2510 { 2511 struct spi_nor_flash_parameter params; 2512 const struct flash_info *info = NULL; 2513 struct mtd_info *mtd = &nor->mtd; 2514 struct spi_nor_hwcaps hwcaps = { 2515 .mask = SNOR_HWCAPS_READ | 2516 SNOR_HWCAPS_READ_FAST | 2517 SNOR_HWCAPS_PP, 2518 }; 2519 struct spi_slave *spi = nor->spi; 2520 int ret; 2521 2522 /* Reset SPI protocol for all commands. */ 2523 nor->reg_proto = SNOR_PROTO_1_1_1; 2524 nor->read_proto = SNOR_PROTO_1_1_1; 2525 nor->write_proto = SNOR_PROTO_1_1_1; 2526 nor->read = spi_nor_read_data; 2527 nor->write = spi_nor_write_data; 2528 nor->read_reg = spi_nor_read_reg; 2529 nor->write_reg = spi_nor_write_reg; 2530 2531 if (spi->mode & SPI_RX_QUAD) { 2532 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2533 2534 if (spi->mode & SPI_TX_QUAD) 2535 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 | 2536 SNOR_HWCAPS_PP_1_1_4 | 2537 SNOR_HWCAPS_PP_1_4_4); 2538 } else if (spi->mode & SPI_RX_DUAL) { 2539 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2540 2541 if (spi->mode & SPI_TX_DUAL) 2542 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2; 2543 } 2544 2545 info = spi_nor_read_id(nor); 2546 if (IS_ERR_OR_NULL(info)) 2547 return -ENOENT; 2548 /* Parse the Serial Flash Discoverable Parameters table. */ 2549 ret = spi_nor_init_params(nor, info, ¶ms); 2550 if (ret) 2551 return ret; 2552 2553 if (!mtd->name) 2554 mtd->name = info->name; 2555 mtd->priv = nor; 2556 mtd->type = MTD_NORFLASH; 2557 mtd->writesize = 1; 2558 mtd->flags = MTD_CAP_NORFLASH; 2559 mtd->size = params.size; 2560 mtd->_erase = spi_nor_erase; 2561 mtd->_read = spi_nor_read; 2562 2563 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 2564 /* NOR protection support for STmicro/Micron chips and similar */ 2565 if (JEDEC_MFR(info) == SNOR_MFR_ST || 2566 JEDEC_MFR(info) == SNOR_MFR_MICRON || 2567 JEDEC_MFR(info) == SNOR_MFR_SST || 2568 info->flags & SPI_NOR_HAS_LOCK) { 2569 nor->flash_lock = stm_lock; 2570 nor->flash_unlock = stm_unlock; 2571 nor->flash_is_locked = stm_is_locked; 2572 } 2573 #endif 2574 2575 #ifdef CONFIG_SPI_FLASH_SST 2576 /* sst nor chips use AAI word program */ 2577 if (info->flags & SST_WRITE) 2578 mtd->_write = sst_write; 2579 else 2580 #endif 2581 mtd->_write = spi_nor_write; 2582 2583 if (info->flags & USE_FSR) 2584 nor->flags |= SNOR_F_USE_FSR; 2585 if (info->flags & SPI_NOR_HAS_TB) 2586 nor->flags |= SNOR_F_HAS_SR_TB; 2587 if (info->flags & NO_CHIP_ERASE) 2588 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 2589 if (info->flags & USE_CLSR) 2590 nor->flags |= SNOR_F_USE_CLSR; 2591 2592 if (info->flags & SPI_NOR_NO_ERASE) 2593 mtd->flags |= MTD_NO_ERASE; 2594 2595 nor->page_size = params.page_size; 2596 mtd->writebufsize = nor->page_size; 2597 2598 /* Some devices cannot do fast-read, no matter what DT tells us */ 2599 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW)) 2600 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 2601 2602 /* 2603 * Configure the SPI memory: 2604 * - select op codes for (Fast) Read, Page Program and Sector Erase. 2605 * - set the number of dummy cycles (mode cycles + wait states). 2606 * - set the SPI protocols for register and memory accesses. 2607 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos). 2608 */ 2609 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps); 2610 if (ret) 2611 return ret; 2612 2613 if (nor->addr_width) { 2614 /* already configured from SFDP */ 2615 } else if (info->addr_width) { 2616 nor->addr_width = info->addr_width; 2617 } else if (mtd->size > SZ_16M) { 2618 #ifndef CONFIG_SPI_FLASH_BAR 2619 /* enable 4-byte addressing if the device exceeds 16MiB */ 2620 nor->addr_width = 4; 2621 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || 2622 info->flags & SPI_NOR_4B_OPCODES) 2623 spi_nor_set_4byte_opcodes(nor, info); 2624 #else 2625 /* Configure the BAR - discover bank cmds and read current bank */ 2626 nor->addr_width = 3; 2627 ret = read_bar(nor, info); 2628 if (ret < 0) 2629 return ret; 2630 #endif 2631 } else { 2632 nor->addr_width = 3; 2633 } 2634 2635 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 2636 dev_dbg(dev, "address width is too large: %u\n", 2637 nor->addr_width); 2638 return -EINVAL; 2639 } 2640 2641 /* Send all the required SPI flash commands to initialize device */ 2642 nor->info = info; 2643 ret = spi_nor_init(nor); 2644 if (ret) 2645 return ret; 2646 2647 nor->name = mtd->name; 2648 nor->size = mtd->size; 2649 nor->erase_size = mtd->erasesize; 2650 nor->sector_size = mtd->erasesize; 2651 2652 #ifndef CONFIG_SPL_BUILD 2653 printf("SF: Detected %s with page size ", nor->name); 2654 print_size(nor->page_size, ", erase size "); 2655 print_size(nor->erase_size, ", total "); 2656 print_size(nor->size, ""); 2657 puts("\n"); 2658 #endif 2659 2660 return 0; 2661 } 2662 2663 /* U-Boot specific functions, need to extend MTD to support these */ 2664 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor) 2665 { 2666 int sr = read_sr(nor); 2667 2668 if (sr < 0) 2669 return sr; 2670 2671 return (sr >> 2) & 7; 2672 } 2673