1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 * 9 * Synced from Linux v4.19 10 */ 11 12 #include <common.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/log2.h> 16 #include <linux/math64.h> 17 #include <linux/sizes.h> 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/mtd/spi-nor.h> 21 #include <spi-mem.h> 22 #include <spi.h> 23 24 #include "sf_internal.h" 25 26 /* Define max times to check status register before we give up. */ 27 28 /* 29 * For everything but full-chip erase; probably could be much smaller, but kept 30 * around for safety for now 31 */ 32 33 #define HZ CONFIG_SYS_HZ 34 35 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 36 37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op 38 *op, void *buf) 39 { 40 if (op->data.dir == SPI_MEM_DATA_IN) 41 op->data.buf.in = buf; 42 else 43 op->data.buf.out = buf; 44 return spi_mem_exec_op(nor->spi, op); 45 } 46 47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) 48 { 49 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1), 50 SPI_MEM_OP_NO_ADDR, 51 SPI_MEM_OP_NO_DUMMY, 52 SPI_MEM_OP_DATA_IN(len, NULL, 1)); 53 int ret; 54 55 ret = spi_nor_read_write_reg(nor, &op, val); 56 if (ret < 0) 57 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret, 58 code); 59 60 return ret; 61 } 62 63 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) 64 { 65 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1), 66 SPI_MEM_OP_NO_ADDR, 67 SPI_MEM_OP_NO_DUMMY, 68 SPI_MEM_OP_DATA_OUT(len, NULL, 1)); 69 70 return spi_nor_read_write_reg(nor, &op, buf); 71 } 72 73 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, 74 u_char *buf) 75 { 76 struct spi_mem_op op = 77 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), 78 SPI_MEM_OP_ADDR(nor->addr_width, from, 1), 79 SPI_MEM_OP_DUMMY(nor->read_dummy, 1), 80 SPI_MEM_OP_DATA_IN(len, buf, 1)); 81 size_t remaining = len; 82 int ret; 83 84 /* get transfer protocols. */ 85 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); 86 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); 87 op.dummy.buswidth = op.addr.buswidth; 88 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 89 90 /* convert the dummy cycles to the number of bytes */ 91 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 92 93 while (remaining) { 94 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; 95 ret = spi_mem_adjust_op_size(nor->spi, &op); 96 if (ret) 97 return ret; 98 99 ret = spi_mem_exec_op(nor->spi, &op); 100 if (ret) 101 return ret; 102 103 op.addr.val += op.data.nbytes; 104 remaining -= op.data.nbytes; 105 op.data.buf.in += op.data.nbytes; 106 } 107 108 return len; 109 } 110 111 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 112 const u_char *buf) 113 { 114 struct spi_mem_op op = 115 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1), 116 SPI_MEM_OP_ADDR(nor->addr_width, to, 1), 117 SPI_MEM_OP_NO_DUMMY, 118 SPI_MEM_OP_DATA_OUT(len, buf, 1)); 119 int ret; 120 121 /* get transfer protocols. */ 122 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto); 123 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); 124 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 125 126 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 127 op.addr.nbytes = 0; 128 129 ret = spi_mem_adjust_op_size(nor->spi, &op); 130 if (ret) 131 return ret; 132 op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes; 133 134 ret = spi_mem_exec_op(nor->spi, &op); 135 if (ret) 136 return ret; 137 138 return op.data.nbytes; 139 } 140 141 /* 142 * Read the status register, returning its value in the location 143 * Return the status register value. 144 * Returns negative if error occurred. 145 */ 146 static int read_sr(struct spi_nor *nor) 147 { 148 int ret; 149 u8 val; 150 151 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); 152 if (ret < 0) { 153 pr_debug("error %d reading SR\n", (int)ret); 154 return ret; 155 } 156 157 return val; 158 } 159 160 /* 161 * Read the flag status register, returning its value in the location 162 * Return the status register value. 163 * Returns negative if error occurred. 164 */ 165 static int read_fsr(struct spi_nor *nor) 166 { 167 int ret; 168 u8 val; 169 170 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); 171 if (ret < 0) { 172 pr_debug("error %d reading FSR\n", ret); 173 return ret; 174 } 175 176 return val; 177 } 178 179 /* 180 * Read configuration register, returning its value in the 181 * location. Return the configuration register value. 182 * Returns negative if error occurred. 183 */ 184 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 185 static int read_cr(struct spi_nor *nor) 186 { 187 int ret; 188 u8 val; 189 190 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); 191 if (ret < 0) { 192 dev_dbg(nor->dev, "error %d reading CR\n", ret); 193 return ret; 194 } 195 196 return val; 197 } 198 #endif 199 200 /* 201 * Write status register 1 byte 202 * Returns negative if error occurred. 203 */ 204 static int write_sr(struct spi_nor *nor, u8 val) 205 { 206 nor->cmd_buf[0] = val; 207 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); 208 } 209 210 /* 211 * Set write enable latch with Write Enable command. 212 * Returns negative if error occurred. 213 */ 214 static int write_enable(struct spi_nor *nor) 215 { 216 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); 217 } 218 219 /* 220 * Send write disable instruction to the chip. 221 */ 222 static int write_disable(struct spi_nor *nor) 223 { 224 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); 225 } 226 227 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) 228 { 229 return mtd->priv; 230 } 231 232 #ifndef CONFIG_SPI_FLASH_BAR 233 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 234 { 235 size_t i; 236 237 for (i = 0; i < size; i++) 238 if (table[i][0] == opcode) 239 return table[i][1]; 240 241 /* No conversion found, keep input op code. */ 242 return opcode; 243 } 244 245 static u8 spi_nor_convert_3to4_read(u8 opcode) 246 { 247 static const u8 spi_nor_3to4_read[][2] = { 248 { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 249 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 250 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 251 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 252 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 253 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 254 255 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 256 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 257 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 258 }; 259 260 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 261 ARRAY_SIZE(spi_nor_3to4_read)); 262 } 263 264 static u8 spi_nor_convert_3to4_program(u8 opcode) 265 { 266 static const u8 spi_nor_3to4_program[][2] = { 267 { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 268 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 269 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 270 }; 271 272 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 273 ARRAY_SIZE(spi_nor_3to4_program)); 274 } 275 276 static u8 spi_nor_convert_3to4_erase(u8 opcode) 277 { 278 static const u8 spi_nor_3to4_erase[][2] = { 279 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 280 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 281 { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 282 }; 283 284 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 285 ARRAY_SIZE(spi_nor_3to4_erase)); 286 } 287 288 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, 289 const struct flash_info *info) 290 { 291 /* Do some manufacturer fixups first */ 292 switch (JEDEC_MFR(info)) { 293 case SNOR_MFR_SPANSION: 294 /* No small sector erase for 4-byte command set */ 295 nor->erase_opcode = SPINOR_OP_SE; 296 nor->mtd.erasesize = info->sector_size; 297 break; 298 299 default: 300 break; 301 } 302 303 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 304 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 305 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 306 } 307 #endif /* !CONFIG_SPI_FLASH_BAR */ 308 309 /* Enable/disable 4-byte addressing mode. */ 310 static int set_4byte(struct spi_nor *nor, const struct flash_info *info, 311 int enable) 312 { 313 int status; 314 bool need_wren = false; 315 u8 cmd; 316 317 switch (JEDEC_MFR(info)) { 318 case SNOR_MFR_ST: 319 case SNOR_MFR_MICRON: 320 /* Some Micron need WREN command; all will accept it */ 321 need_wren = true; 322 case SNOR_MFR_MACRONIX: 323 case SNOR_MFR_WINBOND: 324 if (need_wren) 325 write_enable(nor); 326 327 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; 328 status = nor->write_reg(nor, cmd, NULL, 0); 329 if (need_wren) 330 write_disable(nor); 331 332 if (!status && !enable && 333 JEDEC_MFR(info) == SNOR_MFR_WINBOND) { 334 /* 335 * On Winbond W25Q256FV, leaving 4byte mode causes 336 * the Extended Address Register to be set to 1, so all 337 * 3-byte-address reads come from the second 16M. 338 * We must clear the register to enable normal behavior. 339 */ 340 write_enable(nor); 341 nor->cmd_buf[0] = 0; 342 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1); 343 write_disable(nor); 344 } 345 346 return status; 347 default: 348 /* Spansion style */ 349 nor->cmd_buf[0] = enable << 7; 350 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); 351 } 352 } 353 354 static int spi_nor_sr_ready(struct spi_nor *nor) 355 { 356 int sr = read_sr(nor); 357 358 if (sr < 0) 359 return sr; 360 361 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) { 362 if (sr & SR_E_ERR) 363 dev_dbg(nor->dev, "Erase Error occurred\n"); 364 else 365 dev_dbg(nor->dev, "Programming Error occurred\n"); 366 367 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0); 368 return -EIO; 369 } 370 371 return !(sr & SR_WIP); 372 } 373 374 static int spi_nor_fsr_ready(struct spi_nor *nor) 375 { 376 int fsr = read_fsr(nor); 377 378 if (fsr < 0) 379 return fsr; 380 381 if (fsr & (FSR_E_ERR | FSR_P_ERR)) { 382 if (fsr & FSR_E_ERR) 383 dev_err(nor->dev, "Erase operation failed.\n"); 384 else 385 dev_err(nor->dev, "Program operation failed.\n"); 386 387 if (fsr & FSR_PT_ERR) 388 dev_err(nor->dev, 389 "Attempted to modify a protected sector.\n"); 390 391 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0); 392 return -EIO; 393 } 394 395 return fsr & FSR_READY; 396 } 397 398 static int spi_nor_ready(struct spi_nor *nor) 399 { 400 int sr, fsr; 401 402 sr = spi_nor_sr_ready(nor); 403 if (sr < 0) 404 return sr; 405 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; 406 if (fsr < 0) 407 return fsr; 408 return sr && fsr; 409 } 410 411 /* 412 * Service routine to read status register until ready, or timeout occurs. 413 * Returns non-zero if error. 414 */ 415 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 416 unsigned long timeout) 417 { 418 unsigned long timebase; 419 int ret; 420 421 timebase = get_timer(0); 422 423 while (get_timer(timebase) < timeout) { 424 ret = spi_nor_ready(nor); 425 if (ret < 0) 426 return ret; 427 if (ret) 428 return 0; 429 } 430 431 dev_err(nor->dev, "flash operation timed out\n"); 432 433 return -ETIMEDOUT; 434 } 435 436 static int spi_nor_wait_till_ready(struct spi_nor *nor) 437 { 438 return spi_nor_wait_till_ready_with_timeout(nor, 439 DEFAULT_READY_WAIT_JIFFIES); 440 } 441 442 #ifdef CONFIG_SPI_FLASH_BAR 443 /* 444 * This "clean_bar" is necessary in a situation when one was accessing 445 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit. 446 * 447 * After it the BA24 bit shall be cleared to allow access to correct 448 * memory region after SW reset (by calling "reset" command). 449 * 450 * Otherwise, the BA24 bit may be left set and then after reset, the 451 * ROM would read/write/erase SPL from 16 MiB * bank_sel address. 452 */ 453 static int clean_bar(struct spi_nor *nor) 454 { 455 u8 cmd, bank_sel = 0; 456 457 if (nor->bank_curr == 0) 458 return 0; 459 cmd = nor->bank_write_cmd; 460 nor->bank_curr = 0; 461 write_enable(nor); 462 463 return nor->write_reg(nor, cmd, &bank_sel, 1); 464 } 465 466 static int write_bar(struct spi_nor *nor, u32 offset) 467 { 468 u8 cmd, bank_sel; 469 int ret; 470 471 bank_sel = offset / SZ_16M; 472 if (bank_sel == nor->bank_curr) 473 goto bar_end; 474 475 cmd = nor->bank_write_cmd; 476 write_enable(nor); 477 ret = nor->write_reg(nor, cmd, &bank_sel, 1); 478 if (ret < 0) { 479 debug("SF: fail to write bank register\n"); 480 return ret; 481 } 482 483 bar_end: 484 nor->bank_curr = bank_sel; 485 return nor->bank_curr; 486 } 487 488 static int read_bar(struct spi_nor *nor, const struct flash_info *info) 489 { 490 u8 curr_bank = 0; 491 int ret; 492 493 switch (JEDEC_MFR(info)) { 494 case SNOR_MFR_SPANSION: 495 nor->bank_read_cmd = SPINOR_OP_BRRD; 496 nor->bank_write_cmd = SPINOR_OP_BRWR; 497 break; 498 default: 499 nor->bank_read_cmd = SPINOR_OP_RDEAR; 500 nor->bank_write_cmd = SPINOR_OP_WREAR; 501 } 502 503 ret = nor->read_reg(nor, nor->bank_read_cmd, 504 &curr_bank, 1); 505 if (ret) { 506 debug("SF: fail to read bank addr register\n"); 507 return ret; 508 } 509 nor->bank_curr = curr_bank; 510 511 return 0; 512 } 513 #endif 514 515 /* 516 * Initiate the erasure of a single sector 517 */ 518 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 519 { 520 struct spi_mem_op op = 521 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1), 522 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), 523 SPI_MEM_OP_NO_DUMMY, 524 SPI_MEM_OP_NO_DATA); 525 526 if (nor->erase) 527 return nor->erase(nor, addr); 528 529 /* 530 * Default implementation, if driver doesn't have a specialized HW 531 * control 532 */ 533 return spi_mem_exec_op(nor->spi, &op); 534 } 535 536 /* 537 * Erase an address range on the nor chip. The address range may extend 538 * one or more erase sectors. Return an error is there is a problem erasing. 539 */ 540 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 541 { 542 struct spi_nor *nor = mtd_to_spi_nor(mtd); 543 u32 addr, len, rem; 544 int ret; 545 546 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 547 (long long)instr->len); 548 549 div_u64_rem(instr->len, mtd->erasesize, &rem); 550 if (rem) 551 return -EINVAL; 552 553 addr = instr->addr; 554 len = instr->len; 555 556 while (len) { 557 #ifdef CONFIG_SPI_FLASH_BAR 558 ret = write_bar(nor, addr); 559 if (ret < 0) 560 return ret; 561 #endif 562 write_enable(nor); 563 564 ret = spi_nor_erase_sector(nor, addr); 565 if (ret) 566 goto erase_err; 567 568 addr += mtd->erasesize; 569 len -= mtd->erasesize; 570 571 ret = spi_nor_wait_till_ready(nor); 572 if (ret) 573 goto erase_err; 574 } 575 576 erase_err: 577 #ifdef CONFIG_SPI_FLASH_BAR 578 ret = clean_bar(nor); 579 #endif 580 write_disable(nor); 581 582 return ret; 583 } 584 585 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 586 /* Write status register and ensure bits in mask match written values */ 587 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) 588 { 589 int ret; 590 591 write_enable(nor); 592 ret = write_sr(nor, status_new); 593 if (ret) 594 return ret; 595 596 ret = spi_nor_wait_till_ready(nor); 597 if (ret) 598 return ret; 599 600 ret = read_sr(nor); 601 if (ret < 0) 602 return ret; 603 604 return ((ret & mask) != (status_new & mask)) ? -EIO : 0; 605 } 606 607 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, 608 uint64_t *len) 609 { 610 struct mtd_info *mtd = &nor->mtd; 611 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 612 int shift = ffs(mask) - 1; 613 int pow; 614 615 if (!(sr & mask)) { 616 /* No protection */ 617 *ofs = 0; 618 *len = 0; 619 } else { 620 pow = ((sr & mask) ^ mask) >> shift; 621 *len = mtd->size >> pow; 622 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) 623 *ofs = 0; 624 else 625 *ofs = mtd->size - *len; 626 } 627 } 628 629 /* 630 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if 631 * @locked is false); 0 otherwise 632 */ 633 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len, 634 u8 sr, bool locked) 635 { 636 loff_t lock_offs; 637 uint64_t lock_len; 638 639 if (!len) 640 return 1; 641 642 stm_get_locked_range(nor, sr, &lock_offs, &lock_len); 643 644 if (locked) 645 /* Requested range is a sub-range of locked range */ 646 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 647 else 648 /* Requested range does not overlap with locked range */ 649 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); 650 } 651 652 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 653 u8 sr) 654 { 655 return stm_check_lock_status_sr(nor, ofs, len, sr, true); 656 } 657 658 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 659 u8 sr) 660 { 661 return stm_check_lock_status_sr(nor, ofs, len, sr, false); 662 } 663 664 /* 665 * Lock a region of the flash. Compatible with ST Micro and similar flash. 666 * Supports the block protection bits BP{0,1,2} in the status register 667 * (SR). Does not support these features found in newer SR bitfields: 668 * - SEC: sector/block protect - only handle SEC=0 (block protect) 669 * - CMP: complement protect - only support CMP=0 (range is not complemented) 670 * 671 * Support for the following is provided conditionally for some flash: 672 * - TB: top/bottom protect 673 * 674 * Sample table portion for 8MB flash (Winbond w25q64fw): 675 * 676 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 677 * -------------------------------------------------------------------------- 678 * X | X | 0 | 0 | 0 | NONE | NONE 679 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 680 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 681 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 682 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 683 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 684 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 685 * X | X | 1 | 1 | 1 | 8 MB | ALL 686 * ------|-------|-------|-------|-------|---------------|------------------- 687 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 688 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 689 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 690 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 691 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 692 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 693 * 694 * Returns negative on errors, 0 on success. 695 */ 696 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 697 { 698 struct mtd_info *mtd = &nor->mtd; 699 int status_old, status_new; 700 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 701 u8 shift = ffs(mask) - 1, pow, val; 702 loff_t lock_len; 703 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 704 bool use_top; 705 706 status_old = read_sr(nor); 707 if (status_old < 0) 708 return status_old; 709 710 /* If nothing in our range is unlocked, we don't need to do anything */ 711 if (stm_is_locked_sr(nor, ofs, len, status_old)) 712 return 0; 713 714 /* If anything below us is unlocked, we can't use 'bottom' protection */ 715 if (!stm_is_locked_sr(nor, 0, ofs, status_old)) 716 can_be_bottom = false; 717 718 /* If anything above us is unlocked, we can't use 'top' protection */ 719 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), 720 status_old)) 721 can_be_top = false; 722 723 if (!can_be_bottom && !can_be_top) 724 return -EINVAL; 725 726 /* Prefer top, if both are valid */ 727 use_top = can_be_top; 728 729 /* lock_len: length of region that should end up locked */ 730 if (use_top) 731 lock_len = mtd->size - ofs; 732 else 733 lock_len = ofs + len; 734 735 /* 736 * Need smallest pow such that: 737 * 738 * 1 / (2^pow) <= (len / size) 739 * 740 * so (assuming power-of-2 size) we do: 741 * 742 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 743 */ 744 pow = ilog2(mtd->size) - ilog2(lock_len); 745 val = mask - (pow << shift); 746 if (val & ~mask) 747 return -EINVAL; 748 /* Don't "lock" with no region! */ 749 if (!(val & mask)) 750 return -EINVAL; 751 752 status_new = (status_old & ~mask & ~SR_TB) | val; 753 754 /* Disallow further writes if WP pin is asserted */ 755 status_new |= SR_SRWD; 756 757 if (!use_top) 758 status_new |= SR_TB; 759 760 /* Don't bother if they're the same */ 761 if (status_new == status_old) 762 return 0; 763 764 /* Only modify protection if it will not unlock other areas */ 765 if ((status_new & mask) < (status_old & mask)) 766 return -EINVAL; 767 768 return write_sr_and_check(nor, status_new, mask); 769 } 770 771 /* 772 * Unlock a region of the flash. See stm_lock() for more info 773 * 774 * Returns negative on errors, 0 on success. 775 */ 776 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 777 { 778 struct mtd_info *mtd = &nor->mtd; 779 int status_old, status_new; 780 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 781 u8 shift = ffs(mask) - 1, pow, val; 782 loff_t lock_len; 783 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 784 bool use_top; 785 786 status_old = read_sr(nor); 787 if (status_old < 0) 788 return status_old; 789 790 /* If nothing in our range is locked, we don't need to do anything */ 791 if (stm_is_unlocked_sr(nor, ofs, len, status_old)) 792 return 0; 793 794 /* If anything below us is locked, we can't use 'top' protection */ 795 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) 796 can_be_top = false; 797 798 /* If anything above us is locked, we can't use 'bottom' protection */ 799 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), 800 status_old)) 801 can_be_bottom = false; 802 803 if (!can_be_bottom && !can_be_top) 804 return -EINVAL; 805 806 /* Prefer top, if both are valid */ 807 use_top = can_be_top; 808 809 /* lock_len: length of region that should remain locked */ 810 if (use_top) 811 lock_len = mtd->size - (ofs + len); 812 else 813 lock_len = ofs; 814 815 /* 816 * Need largest pow such that: 817 * 818 * 1 / (2^pow) >= (len / size) 819 * 820 * so (assuming power-of-2 size) we do: 821 * 822 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 823 */ 824 pow = ilog2(mtd->size) - order_base_2(lock_len); 825 if (lock_len == 0) { 826 val = 0; /* fully unlocked */ 827 } else { 828 val = mask - (pow << shift); 829 /* Some power-of-two sizes are not supported */ 830 if (val & ~mask) 831 return -EINVAL; 832 } 833 834 status_new = (status_old & ~mask & ~SR_TB) | val; 835 836 /* Don't protect status register if we're fully unlocked */ 837 if (lock_len == 0) 838 status_new &= ~SR_SRWD; 839 840 if (!use_top) 841 status_new |= SR_TB; 842 843 /* Don't bother if they're the same */ 844 if (status_new == status_old) 845 return 0; 846 847 /* Only modify protection if it will not lock other areas */ 848 if ((status_new & mask) > (status_old & mask)) 849 return -EINVAL; 850 851 return write_sr_and_check(nor, status_new, mask); 852 } 853 854 /* 855 * Check if a region of the flash is (completely) locked. See stm_lock() for 856 * more info. 857 * 858 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 859 * negative on errors. 860 */ 861 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 862 { 863 int status; 864 865 status = read_sr(nor); 866 if (status < 0) 867 return status; 868 869 return stm_is_locked_sr(nor, ofs, len, status); 870 } 871 #endif /* CONFIG_SPI_FLASH_STMICRO */ 872 873 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 874 { 875 int tmp; 876 u8 id[SPI_NOR_MAX_ID_LEN]; 877 const struct flash_info *info; 878 879 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); 880 if (tmp < 0) { 881 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); 882 return ERR_PTR(tmp); 883 } 884 885 info = spi_nor_ids; 886 for (; info->name; info++) { 887 if (info->id_len) { 888 if (!memcmp(info->id, id, info->id_len)) 889 return info; 890 } 891 } 892 893 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", 894 id[0], id[1], id[2]); 895 return ERR_PTR(-ENODEV); 896 } 897 898 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 899 size_t *retlen, u_char *buf) 900 { 901 struct spi_nor *nor = mtd_to_spi_nor(mtd); 902 int ret; 903 904 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 905 906 while (len) { 907 loff_t addr = from; 908 size_t read_len = len; 909 910 #ifdef CONFIG_SPI_FLASH_BAR 911 u32 remain_len; 912 913 ret = write_bar(nor, addr); 914 if (ret < 0) 915 return log_ret(ret); 916 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr; 917 918 if (len < remain_len) 919 read_len = len; 920 else 921 read_len = remain_len; 922 #endif 923 924 ret = nor->read(nor, addr, read_len, buf); 925 if (ret == 0) { 926 /* We shouldn't see 0-length reads */ 927 ret = -EIO; 928 goto read_err; 929 } 930 if (ret < 0) 931 goto read_err; 932 933 *retlen += ret; 934 buf += ret; 935 from += ret; 936 len -= ret; 937 } 938 ret = 0; 939 940 read_err: 941 #ifdef CONFIG_SPI_FLASH_BAR 942 ret = clean_bar(nor); 943 #endif 944 return ret; 945 } 946 947 #ifdef CONFIG_SPI_FLASH_SST 948 /* 949 * sst26 flash series has its own block protection implementation: 950 * 4x - 8 KByte blocks - read & write protection bits - upper addresses 951 * 1x - 32 KByte blocks - write protection bits 952 * rest - 64 KByte blocks - write protection bits 953 * 1x - 32 KByte blocks - write protection bits 954 * 4x - 8 KByte blocks - read & write protection bits - lower addresses 955 * 956 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region 957 * will be treated as single block. 958 */ 959 #define SST26_BPR_8K_NUM 4 960 #define SST26_MAX_BPR_REG_LEN (18 + 1) 961 #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K) 962 963 enum lock_ctl { 964 SST26_CTL_LOCK, 965 SST26_CTL_UNLOCK, 966 SST26_CTL_CHECK 967 }; 968 969 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) 970 { 971 switch (ctl) { 972 case SST26_CTL_LOCK: 973 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8); 974 break; 975 case SST26_CTL_UNLOCK: 976 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8); 977 break; 978 case SST26_CTL_CHECK: 979 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8)); 980 } 981 982 return false; 983 } 984 985 /* 986 * Lock, unlock or check lock status of the flash region of the flash (depending 987 * on the lock_ctl value) 988 */ 989 static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl) 990 { 991 struct mtd_info *mtd = &nor->mtd; 992 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size; 993 bool lower_64k = false, upper_64k = false; 994 u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {}; 995 int ret; 996 997 /* Check length and offset for 64k alignment */ 998 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) { 999 dev_err(nor->dev, "length or offset is not 64KiB allighned\n"); 1000 return -EINVAL; 1001 } 1002 1003 if (ofs + len > mtd->size) { 1004 dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n", 1005 ofs, len, mtd->size); 1006 return -EINVAL; 1007 } 1008 1009 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */ 1010 if (mtd->size != SZ_2M && 1011 mtd->size != SZ_4M && 1012 mtd->size != SZ_8M) 1013 return -EINVAL; 1014 1015 bpr_size = 2 + (mtd->size / SZ_64K / 8); 1016 1017 ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size); 1018 if (ret < 0) { 1019 dev_err(nor->dev, "fail to read block-protection register\n"); 1020 return ret; 1021 } 1022 1023 rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE); 1024 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE); 1025 1026 upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE)); 1027 lower_64k = (ofs < SST26_BOUND_REG_SIZE); 1028 1029 /* Lower bits in block-protection register are about 64k region */ 1030 bpr_ptr = lptr_64k / SZ_64K - 1; 1031 1032 /* Process 64K blocks region */ 1033 while (lptr_64k < rptr_64k) { 1034 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 1035 return EACCES; 1036 1037 bpr_ptr++; 1038 lptr_64k += SZ_64K; 1039 } 1040 1041 /* 32K and 8K region bits in BPR are after 64k region bits */ 1042 bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K; 1043 1044 /* Process lower 32K block region */ 1045 if (lower_64k) 1046 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 1047 return EACCES; 1048 1049 bpr_ptr++; 1050 1051 /* Process upper 32K block region */ 1052 if (upper_64k) 1053 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 1054 return EACCES; 1055 1056 bpr_ptr++; 1057 1058 /* Process lower 8K block regions */ 1059 for (i = 0; i < SST26_BPR_8K_NUM; i++) { 1060 if (lower_64k) 1061 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 1062 return EACCES; 1063 1064 /* In 8K area BPR has both read and write protection bits */ 1065 bpr_ptr += 2; 1066 } 1067 1068 /* Process upper 8K block regions */ 1069 for (i = 0; i < SST26_BPR_8K_NUM; i++) { 1070 if (upper_64k) 1071 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 1072 return EACCES; 1073 1074 /* In 8K area BPR has both read and write protection bits */ 1075 bpr_ptr += 2; 1076 } 1077 1078 /* If we check region status we don't need to write BPR back */ 1079 if (ctl == SST26_CTL_CHECK) 1080 return 0; 1081 1082 ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size); 1083 if (ret < 0) { 1084 dev_err(nor->dev, "fail to write block-protection register\n"); 1085 return ret; 1086 } 1087 1088 return 0; 1089 } 1090 1091 static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 1092 { 1093 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK); 1094 } 1095 1096 static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 1097 { 1098 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK); 1099 } 1100 1101 /* 1102 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked, 1103 * and negative on errors. 1104 */ 1105 static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 1106 { 1107 /* 1108 * is_locked function is used for check before reading or erasing flash 1109 * region, so offset and length might be not 64k allighned, so adjust 1110 * them to be 64k allighned as sst26_lock_ctl works only with 64k 1111 * allighned regions. 1112 */ 1113 ofs -= ofs & (SZ_64K - 1); 1114 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len; 1115 1116 return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK); 1117 } 1118 1119 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len, 1120 size_t *retlen, const u_char *buf) 1121 { 1122 size_t actual; 1123 int ret = 0; 1124 1125 for (actual = 0; actual < len; actual++) { 1126 nor->program_opcode = SPINOR_OP_BP; 1127 1128 write_enable(nor); 1129 /* write one byte. */ 1130 ret = nor->write(nor, to, 1, buf + actual); 1131 if (ret < 0) 1132 goto sst_write_err; 1133 ret = spi_nor_wait_till_ready(nor); 1134 if (ret) 1135 goto sst_write_err; 1136 to++; 1137 } 1138 1139 sst_write_err: 1140 write_disable(nor); 1141 return ret; 1142 } 1143 1144 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, 1145 size_t *retlen, const u_char *buf) 1146 { 1147 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1148 struct spi_slave *spi = nor->spi; 1149 size_t actual; 1150 int ret; 1151 1152 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 1153 if (spi->mode & SPI_TX_BYTE) 1154 return sst_write_byteprogram(nor, to, len, retlen, buf); 1155 1156 write_enable(nor); 1157 1158 nor->sst_write_second = false; 1159 1160 actual = to % 2; 1161 /* Start write from odd address. */ 1162 if (actual) { 1163 nor->program_opcode = SPINOR_OP_BP; 1164 1165 /* write one byte. */ 1166 ret = nor->write(nor, to, 1, buf); 1167 if (ret < 0) 1168 goto sst_write_err; 1169 ret = spi_nor_wait_till_ready(nor); 1170 if (ret) 1171 goto sst_write_err; 1172 } 1173 to += actual; 1174 1175 /* Write out most of the data here. */ 1176 for (; actual < len - 1; actual += 2) { 1177 nor->program_opcode = SPINOR_OP_AAI_WP; 1178 1179 /* write two bytes. */ 1180 ret = nor->write(nor, to, 2, buf + actual); 1181 if (ret < 0) 1182 goto sst_write_err; 1183 ret = spi_nor_wait_till_ready(nor); 1184 if (ret) 1185 goto sst_write_err; 1186 to += 2; 1187 nor->sst_write_second = true; 1188 } 1189 nor->sst_write_second = false; 1190 1191 write_disable(nor); 1192 ret = spi_nor_wait_till_ready(nor); 1193 if (ret) 1194 goto sst_write_err; 1195 1196 /* Write out trailing byte if it exists. */ 1197 if (actual != len) { 1198 write_enable(nor); 1199 1200 nor->program_opcode = SPINOR_OP_BP; 1201 ret = nor->write(nor, to, 1, buf + actual); 1202 if (ret < 0) 1203 goto sst_write_err; 1204 ret = spi_nor_wait_till_ready(nor); 1205 if (ret) 1206 goto sst_write_err; 1207 write_disable(nor); 1208 actual += 1; 1209 } 1210 sst_write_err: 1211 *retlen += actual; 1212 return ret; 1213 } 1214 #endif 1215 /* 1216 * Write an address range to the nor chip. Data must be written in 1217 * FLASH_PAGESIZE chunks. The address range may be any size provided 1218 * it is within the physical boundaries. 1219 */ 1220 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 1221 size_t *retlen, const u_char *buf) 1222 { 1223 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1224 size_t page_offset, page_remain, i; 1225 ssize_t ret; 1226 1227 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 1228 1229 for (i = 0; i < len; ) { 1230 ssize_t written; 1231 loff_t addr = to + i; 1232 1233 /* 1234 * If page_size is a power of two, the offset can be quickly 1235 * calculated with an AND operation. On the other cases we 1236 * need to do a modulus operation (more expensive). 1237 * Power of two numbers have only one bit set and we can use 1238 * the instruction hweight32 to detect if we need to do a 1239 * modulus (do_div()) or not. 1240 */ 1241 if (hweight32(nor->page_size) == 1) { 1242 page_offset = addr & (nor->page_size - 1); 1243 } else { 1244 u64 aux = addr; 1245 1246 page_offset = do_div(aux, nor->page_size); 1247 } 1248 /* the size of data remaining on the first page */ 1249 page_remain = min_t(size_t, 1250 nor->page_size - page_offset, len - i); 1251 1252 #ifdef CONFIG_SPI_FLASH_BAR 1253 ret = write_bar(nor, addr); 1254 if (ret < 0) 1255 return ret; 1256 #endif 1257 write_enable(nor); 1258 ret = nor->write(nor, addr, page_remain, buf + i); 1259 if (ret < 0) 1260 goto write_err; 1261 written = ret; 1262 1263 ret = spi_nor_wait_till_ready(nor); 1264 if (ret) 1265 goto write_err; 1266 *retlen += written; 1267 i += written; 1268 } 1269 1270 write_err: 1271 #ifdef CONFIG_SPI_FLASH_BAR 1272 ret = clean_bar(nor); 1273 #endif 1274 return ret; 1275 } 1276 1277 #ifdef CONFIG_SPI_FLASH_MACRONIX 1278 /** 1279 * macronix_quad_enable() - set QE bit in Status Register. 1280 * @nor: pointer to a 'struct spi_nor' 1281 * 1282 * Set the Quad Enable (QE) bit in the Status Register. 1283 * 1284 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. 1285 * 1286 * Return: 0 on success, -errno otherwise. 1287 */ 1288 static int macronix_quad_enable(struct spi_nor *nor) 1289 { 1290 int ret, val; 1291 1292 val = read_sr(nor); 1293 if (val < 0) 1294 return val; 1295 if (val & SR_QUAD_EN_MX) 1296 return 0; 1297 1298 write_enable(nor); 1299 1300 write_sr(nor, val | SR_QUAD_EN_MX); 1301 1302 ret = spi_nor_wait_till_ready(nor); 1303 if (ret) 1304 return ret; 1305 1306 ret = read_sr(nor); 1307 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { 1308 dev_err(nor->dev, "Macronix Quad bit not set\n"); 1309 return -EINVAL; 1310 } 1311 1312 return 0; 1313 } 1314 #endif 1315 1316 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1317 /* 1318 * Write status Register and configuration register with 2 bytes 1319 * The first byte will be written to the status register, while the 1320 * second byte will be written to the configuration register. 1321 * Return negative if error occurred. 1322 */ 1323 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) 1324 { 1325 int ret; 1326 1327 write_enable(nor); 1328 1329 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2); 1330 if (ret < 0) { 1331 dev_dbg(nor->dev, 1332 "error while writing configuration register\n"); 1333 return -EINVAL; 1334 } 1335 1336 ret = spi_nor_wait_till_ready(nor); 1337 if (ret) { 1338 dev_dbg(nor->dev, 1339 "timeout while writing configuration register\n"); 1340 return ret; 1341 } 1342 1343 return 0; 1344 } 1345 1346 /** 1347 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. 1348 * @nor: pointer to a 'struct spi_nor' 1349 * 1350 * Set the Quad Enable (QE) bit in the Configuration Register. 1351 * This function should be used with QSPI memories supporting the Read 1352 * Configuration Register (35h) instruction. 1353 * 1354 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1355 * memories. 1356 * 1357 * Return: 0 on success, -errno otherwise. 1358 */ 1359 static int spansion_read_cr_quad_enable(struct spi_nor *nor) 1360 { 1361 u8 sr_cr[2]; 1362 int ret; 1363 1364 /* Check current Quad Enable bit value. */ 1365 ret = read_cr(nor); 1366 if (ret < 0) { 1367 dev_dbg(dev, "error while reading configuration register\n"); 1368 return -EINVAL; 1369 } 1370 1371 if (ret & CR_QUAD_EN_SPAN) 1372 return 0; 1373 1374 sr_cr[1] = ret | CR_QUAD_EN_SPAN; 1375 1376 /* Keep the current value of the Status Register. */ 1377 ret = read_sr(nor); 1378 if (ret < 0) { 1379 dev_dbg(dev, "error while reading status register\n"); 1380 return -EINVAL; 1381 } 1382 sr_cr[0] = ret; 1383 1384 ret = write_sr_cr(nor, sr_cr); 1385 if (ret) 1386 return ret; 1387 1388 /* Read back and check it. */ 1389 ret = read_cr(nor); 1390 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { 1391 dev_dbg(nor->dev, "Spansion Quad bit not set\n"); 1392 return -EINVAL; 1393 } 1394 1395 return 0; 1396 } 1397 1398 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1399 /** 1400 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register. 1401 * @nor: pointer to a 'struct spi_nor' 1402 * 1403 * Set the Quad Enable (QE) bit in the Configuration Register. 1404 * This function should be used with QSPI memories not supporting the Read 1405 * Configuration Register (35h) instruction. 1406 * 1407 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1408 * memories. 1409 * 1410 * Return: 0 on success, -errno otherwise. 1411 */ 1412 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) 1413 { 1414 u8 sr_cr[2]; 1415 int ret; 1416 1417 /* Keep the current value of the Status Register. */ 1418 ret = read_sr(nor); 1419 if (ret < 0) { 1420 dev_dbg(nor->dev, "error while reading status register\n"); 1421 return -EINVAL; 1422 } 1423 sr_cr[0] = ret; 1424 sr_cr[1] = CR_QUAD_EN_SPAN; 1425 1426 return write_sr_cr(nor, sr_cr); 1427 } 1428 1429 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */ 1430 #endif /* CONFIG_SPI_FLASH_SPANSION */ 1431 1432 struct spi_nor_read_command { 1433 u8 num_mode_clocks; 1434 u8 num_wait_states; 1435 u8 opcode; 1436 enum spi_nor_protocol proto; 1437 }; 1438 1439 struct spi_nor_pp_command { 1440 u8 opcode; 1441 enum spi_nor_protocol proto; 1442 }; 1443 1444 enum spi_nor_read_command_index { 1445 SNOR_CMD_READ, 1446 SNOR_CMD_READ_FAST, 1447 SNOR_CMD_READ_1_1_1_DTR, 1448 1449 /* Dual SPI */ 1450 SNOR_CMD_READ_1_1_2, 1451 SNOR_CMD_READ_1_2_2, 1452 SNOR_CMD_READ_2_2_2, 1453 SNOR_CMD_READ_1_2_2_DTR, 1454 1455 /* Quad SPI */ 1456 SNOR_CMD_READ_1_1_4, 1457 SNOR_CMD_READ_1_4_4, 1458 SNOR_CMD_READ_4_4_4, 1459 SNOR_CMD_READ_1_4_4_DTR, 1460 1461 /* Octo SPI */ 1462 SNOR_CMD_READ_1_1_8, 1463 SNOR_CMD_READ_1_8_8, 1464 SNOR_CMD_READ_8_8_8, 1465 SNOR_CMD_READ_1_8_8_DTR, 1466 1467 SNOR_CMD_READ_MAX 1468 }; 1469 1470 enum spi_nor_pp_command_index { 1471 SNOR_CMD_PP, 1472 1473 /* Quad SPI */ 1474 SNOR_CMD_PP_1_1_4, 1475 SNOR_CMD_PP_1_4_4, 1476 SNOR_CMD_PP_4_4_4, 1477 1478 /* Octo SPI */ 1479 SNOR_CMD_PP_1_1_8, 1480 SNOR_CMD_PP_1_8_8, 1481 SNOR_CMD_PP_8_8_8, 1482 1483 SNOR_CMD_PP_MAX 1484 }; 1485 1486 struct spi_nor_flash_parameter { 1487 u64 size; 1488 u32 page_size; 1489 1490 struct spi_nor_hwcaps hwcaps; 1491 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; 1492 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; 1493 1494 int (*quad_enable)(struct spi_nor *nor); 1495 }; 1496 1497 static void 1498 spi_nor_set_read_settings(struct spi_nor_read_command *read, 1499 u8 num_mode_clocks, 1500 u8 num_wait_states, 1501 u8 opcode, 1502 enum spi_nor_protocol proto) 1503 { 1504 read->num_mode_clocks = num_mode_clocks; 1505 read->num_wait_states = num_wait_states; 1506 read->opcode = opcode; 1507 read->proto = proto; 1508 } 1509 1510 static void 1511 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, 1512 u8 opcode, 1513 enum spi_nor_protocol proto) 1514 { 1515 pp->opcode = opcode; 1516 pp->proto = proto; 1517 } 1518 1519 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1520 /* 1521 * Serial Flash Discoverable Parameters (SFDP) parsing. 1522 */ 1523 1524 /** 1525 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters. 1526 * @nor: pointer to a 'struct spi_nor' 1527 * @addr: offset in the SFDP area to start reading data from 1528 * @len: number of bytes to read 1529 * @buf: buffer where the SFDP data are copied into (dma-safe memory) 1530 * 1531 * Whatever the actual numbers of bytes for address and dummy cycles are 1532 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always 1533 * followed by a 3-byte address and 8 dummy clock cycles. 1534 * 1535 * Return: 0 on success, -errno otherwise. 1536 */ 1537 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr, 1538 size_t len, void *buf) 1539 { 1540 u8 addr_width, read_opcode, read_dummy; 1541 int ret; 1542 1543 read_opcode = nor->read_opcode; 1544 addr_width = nor->addr_width; 1545 read_dummy = nor->read_dummy; 1546 1547 nor->read_opcode = SPINOR_OP_RDSFDP; 1548 nor->addr_width = 3; 1549 nor->read_dummy = 8; 1550 1551 while (len) { 1552 ret = nor->read(nor, addr, len, (u8 *)buf); 1553 if (!ret || ret > len) { 1554 ret = -EIO; 1555 goto read_err; 1556 } 1557 if (ret < 0) 1558 goto read_err; 1559 1560 buf += ret; 1561 addr += ret; 1562 len -= ret; 1563 } 1564 ret = 0; 1565 1566 read_err: 1567 nor->read_opcode = read_opcode; 1568 nor->addr_width = addr_width; 1569 nor->read_dummy = read_dummy; 1570 1571 return ret; 1572 } 1573 1574 struct sfdp_parameter_header { 1575 u8 id_lsb; 1576 u8 minor; 1577 u8 major; 1578 u8 length; /* in double words */ 1579 u8 parameter_table_pointer[3]; /* byte address */ 1580 u8 id_msb; 1581 }; 1582 1583 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) 1584 #define SFDP_PARAM_HEADER_PTP(p) \ 1585 (((p)->parameter_table_pointer[2] << 16) | \ 1586 ((p)->parameter_table_pointer[1] << 8) | \ 1587 ((p)->parameter_table_pointer[0] << 0)) 1588 1589 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ 1590 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ 1591 1592 #define SFDP_SIGNATURE 0x50444653U 1593 #define SFDP_JESD216_MAJOR 1 1594 #define SFDP_JESD216_MINOR 0 1595 #define SFDP_JESD216A_MINOR 5 1596 #define SFDP_JESD216B_MINOR 6 1597 1598 struct sfdp_header { 1599 u32 signature; /* Ox50444653U <=> "SFDP" */ 1600 u8 minor; 1601 u8 major; 1602 u8 nph; /* 0-base number of parameter headers */ 1603 u8 unused; 1604 1605 /* Basic Flash Parameter Table. */ 1606 struct sfdp_parameter_header bfpt_header; 1607 }; 1608 1609 /* Basic Flash Parameter Table */ 1610 1611 /* 1612 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. 1613 * They are indexed from 1 but C arrays are indexed from 0. 1614 */ 1615 #define BFPT_DWORD(i) ((i) - 1) 1616 #define BFPT_DWORD_MAX 16 1617 1618 /* The first version of JESB216 defined only 9 DWORDs. */ 1619 #define BFPT_DWORD_MAX_JESD216 9 1620 1621 /* 1st DWORD. */ 1622 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) 1623 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) 1624 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) 1625 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) 1626 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) 1627 #define BFPT_DWORD1_DTR BIT(19) 1628 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) 1629 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) 1630 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) 1631 1632 /* 5th DWORD. */ 1633 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) 1634 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) 1635 1636 /* 11th DWORD. */ 1637 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 1638 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) 1639 1640 /* 15th DWORD. */ 1641 1642 /* 1643 * (from JESD216 rev B) 1644 * Quad Enable Requirements (QER): 1645 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 1646 * reads based on instruction. DQ3/HOLD# functions are hold during 1647 * instruction phase. 1648 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with 1649 * two data bytes where bit 1 of the second byte is one. 1650 * [...] 1651 * Writing only one byte to the status register has the side-effect of 1652 * clearing status register 2, including the QE bit. The 100b code is 1653 * used if writing one byte to the status register does not modify 1654 * status register 2. 1655 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with 1656 * one data byte where bit 6 is one. 1657 * [...] 1658 * - 011b: QE is bit 7 of status register 2. It is set via Write status 1659 * register 2 instruction 3Eh with one data byte where bit 7 is one. 1660 * [...] 1661 * The status register 2 is read using instruction 3Fh. 1662 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with 1663 * two data bytes where bit 1 of the second byte is one. 1664 * [...] 1665 * In contrast to the 001b code, writing one byte to the status 1666 * register does not modify status register 2. 1667 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using 1668 * Read Status instruction 05h. Status register2 is read using 1669 * instruction 35h. QE is set via Writ Status instruction 01h with 1670 * two data bytes where bit 1 of the second byte is one. 1671 * [...] 1672 */ 1673 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) 1674 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ 1675 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) 1676 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ 1677 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) 1678 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) 1679 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ 1680 1681 struct sfdp_bfpt { 1682 u32 dwords[BFPT_DWORD_MAX]; 1683 }; 1684 1685 /* Fast Read settings. */ 1686 1687 static void 1688 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read, 1689 u16 half, 1690 enum spi_nor_protocol proto) 1691 { 1692 read->num_mode_clocks = (half >> 5) & 0x07; 1693 read->num_wait_states = (half >> 0) & 0x1f; 1694 read->opcode = (half >> 8) & 0xff; 1695 read->proto = proto; 1696 } 1697 1698 struct sfdp_bfpt_read { 1699 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */ 1700 u32 hwcaps; 1701 1702 /* 1703 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us 1704 * whether the Fast Read x-y-z command is supported. 1705 */ 1706 u32 supported_dword; 1707 u32 supported_bit; 1708 1709 /* 1710 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD 1711 * encodes the op code, the number of mode clocks and the number of wait 1712 * states to be used by Fast Read x-y-z command. 1713 */ 1714 u32 settings_dword; 1715 u32 settings_shift; 1716 1717 /* The SPI protocol for this Fast Read x-y-z command. */ 1718 enum spi_nor_protocol proto; 1719 }; 1720 1721 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = { 1722 /* Fast Read 1-1-2 */ 1723 { 1724 SNOR_HWCAPS_READ_1_1_2, 1725 BFPT_DWORD(1), BIT(16), /* Supported bit */ 1726 BFPT_DWORD(4), 0, /* Settings */ 1727 SNOR_PROTO_1_1_2, 1728 }, 1729 1730 /* Fast Read 1-2-2 */ 1731 { 1732 SNOR_HWCAPS_READ_1_2_2, 1733 BFPT_DWORD(1), BIT(20), /* Supported bit */ 1734 BFPT_DWORD(4), 16, /* Settings */ 1735 SNOR_PROTO_1_2_2, 1736 }, 1737 1738 /* Fast Read 2-2-2 */ 1739 { 1740 SNOR_HWCAPS_READ_2_2_2, 1741 BFPT_DWORD(5), BIT(0), /* Supported bit */ 1742 BFPT_DWORD(6), 16, /* Settings */ 1743 SNOR_PROTO_2_2_2, 1744 }, 1745 1746 /* Fast Read 1-1-4 */ 1747 { 1748 SNOR_HWCAPS_READ_1_1_4, 1749 BFPT_DWORD(1), BIT(22), /* Supported bit */ 1750 BFPT_DWORD(3), 16, /* Settings */ 1751 SNOR_PROTO_1_1_4, 1752 }, 1753 1754 /* Fast Read 1-4-4 */ 1755 { 1756 SNOR_HWCAPS_READ_1_4_4, 1757 BFPT_DWORD(1), BIT(21), /* Supported bit */ 1758 BFPT_DWORD(3), 0, /* Settings */ 1759 SNOR_PROTO_1_4_4, 1760 }, 1761 1762 /* Fast Read 4-4-4 */ 1763 { 1764 SNOR_HWCAPS_READ_4_4_4, 1765 BFPT_DWORD(5), BIT(4), /* Supported bit */ 1766 BFPT_DWORD(7), 16, /* Settings */ 1767 SNOR_PROTO_4_4_4, 1768 }, 1769 }; 1770 1771 struct sfdp_bfpt_erase { 1772 /* 1773 * The half-word at offset <shift> in DWORD <dwoard> encodes the 1774 * op code and erase sector size to be used by Sector Erase commands. 1775 */ 1776 u32 dword; 1777 u32 shift; 1778 }; 1779 1780 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = { 1781 /* Erase Type 1 in DWORD8 bits[15:0] */ 1782 {BFPT_DWORD(8), 0}, 1783 1784 /* Erase Type 2 in DWORD8 bits[31:16] */ 1785 {BFPT_DWORD(8), 16}, 1786 1787 /* Erase Type 3 in DWORD9 bits[15:0] */ 1788 {BFPT_DWORD(9), 0}, 1789 1790 /* Erase Type 4 in DWORD9 bits[31:16] */ 1791 {BFPT_DWORD(9), 16}, 1792 }; 1793 1794 static int spi_nor_hwcaps_read2cmd(u32 hwcaps); 1795 1796 /** 1797 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table. 1798 * @nor: pointer to a 'struct spi_nor' 1799 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing 1800 * the Basic Flash Parameter Table length and version 1801 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 1802 * filled 1803 * 1804 * The Basic Flash Parameter Table is the main and only mandatory table as 1805 * defined by the SFDP (JESD216) specification. 1806 * It provides us with the total size (memory density) of the data array and 1807 * the number of address bytes for Fast Read, Page Program and Sector Erase 1808 * commands. 1809 * For Fast READ commands, it also gives the number of mode clock cycles and 1810 * wait states (regrouped in the number of dummy clock cycles) for each 1811 * supported instruction op code. 1812 * For Page Program, the page size is now available since JESD216 rev A, however 1813 * the supported instruction op codes are still not provided. 1814 * For Sector Erase commands, this table stores the supported instruction op 1815 * codes and the associated sector sizes. 1816 * Finally, the Quad Enable Requirements (QER) are also available since JESD216 1817 * rev A. The QER bits encode the manufacturer dependent procedure to be 1818 * executed to set the Quad Enable (QE) bit in some internal register of the 1819 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before 1820 * sending any Quad SPI command to the memory. Actually, setting the QE bit 1821 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2 1822 * and IO3 hence enabling 4 (Quad) I/O lines. 1823 * 1824 * Return: 0 on success, -errno otherwise. 1825 */ 1826 static int spi_nor_parse_bfpt(struct spi_nor *nor, 1827 const struct sfdp_parameter_header *bfpt_header, 1828 struct spi_nor_flash_parameter *params) 1829 { 1830 struct mtd_info *mtd = &nor->mtd; 1831 struct sfdp_bfpt bfpt; 1832 size_t len; 1833 int i, cmd, err; 1834 u32 addr; 1835 u16 half; 1836 1837 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */ 1838 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216) 1839 return -EINVAL; 1840 1841 /* Read the Basic Flash Parameter Table. */ 1842 len = min_t(size_t, sizeof(bfpt), 1843 bfpt_header->length * sizeof(u32)); 1844 addr = SFDP_PARAM_HEADER_PTP(bfpt_header); 1845 memset(&bfpt, 0, sizeof(bfpt)); 1846 err = spi_nor_read_sfdp(nor, addr, len, &bfpt); 1847 if (err < 0) 1848 return err; 1849 1850 /* Fix endianness of the BFPT DWORDs. */ 1851 for (i = 0; i < BFPT_DWORD_MAX; i++) 1852 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]); 1853 1854 /* Number of address bytes. */ 1855 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) { 1856 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: 1857 nor->addr_width = 3; 1858 break; 1859 1860 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: 1861 nor->addr_width = 4; 1862 break; 1863 1864 default: 1865 break; 1866 } 1867 1868 /* Flash Memory Density (in bits). */ 1869 params->size = bfpt.dwords[BFPT_DWORD(2)]; 1870 if (params->size & BIT(31)) { 1871 params->size &= ~BIT(31); 1872 1873 /* 1874 * Prevent overflows on params->size. Anyway, a NOR of 2^64 1875 * bits is unlikely to exist so this error probably means 1876 * the BFPT we are reading is corrupted/wrong. 1877 */ 1878 if (params->size > 63) 1879 return -EINVAL; 1880 1881 params->size = 1ULL << params->size; 1882 } else { 1883 params->size++; 1884 } 1885 params->size >>= 3; /* Convert to bytes. */ 1886 1887 /* Fast Read settings. */ 1888 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) { 1889 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i]; 1890 struct spi_nor_read_command *read; 1891 1892 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) { 1893 params->hwcaps.mask &= ~rd->hwcaps; 1894 continue; 1895 } 1896 1897 params->hwcaps.mask |= rd->hwcaps; 1898 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps); 1899 read = ¶ms->reads[cmd]; 1900 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift; 1901 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto); 1902 } 1903 1904 /* Sector Erase settings. */ 1905 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) { 1906 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i]; 1907 u32 erasesize; 1908 u8 opcode; 1909 1910 half = bfpt.dwords[er->dword] >> er->shift; 1911 erasesize = half & 0xff; 1912 1913 /* erasesize == 0 means this Erase Type is not supported. */ 1914 if (!erasesize) 1915 continue; 1916 1917 erasesize = 1U << erasesize; 1918 opcode = (half >> 8) & 0xff; 1919 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS 1920 if (erasesize == SZ_4K) { 1921 nor->erase_opcode = opcode; 1922 mtd->erasesize = erasesize; 1923 break; 1924 } 1925 #endif 1926 if (!mtd->erasesize || mtd->erasesize < erasesize) { 1927 nor->erase_opcode = opcode; 1928 mtd->erasesize = erasesize; 1929 } 1930 } 1931 1932 /* Stop here if not JESD216 rev A or later. */ 1933 if (bfpt_header->length < BFPT_DWORD_MAX) 1934 return 0; 1935 1936 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */ 1937 params->page_size = bfpt.dwords[BFPT_DWORD(11)]; 1938 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK; 1939 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT; 1940 params->page_size = 1U << params->page_size; 1941 1942 /* Quad Enable Requirements. */ 1943 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { 1944 case BFPT_DWORD15_QER_NONE: 1945 params->quad_enable = NULL; 1946 break; 1947 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1948 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: 1949 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: 1950 params->quad_enable = spansion_no_read_cr_quad_enable; 1951 break; 1952 #endif 1953 #ifdef CONFIG_SPI_FLASH_MACRONIX 1954 case BFPT_DWORD15_QER_SR1_BIT6: 1955 params->quad_enable = macronix_quad_enable; 1956 break; 1957 #endif 1958 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1959 case BFPT_DWORD15_QER_SR2_BIT1: 1960 params->quad_enable = spansion_read_cr_quad_enable; 1961 break; 1962 #endif 1963 default: 1964 return -EINVAL; 1965 } 1966 1967 return 0; 1968 } 1969 1970 /** 1971 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters. 1972 * @nor: pointer to a 'struct spi_nor' 1973 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 1974 * filled 1975 * 1976 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216 1977 * specification. This is a standard which tends to supported by almost all 1978 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at 1979 * runtime the main parameters needed to perform basic SPI flash operations such 1980 * as Fast Read, Page Program or Sector Erase commands. 1981 * 1982 * Return: 0 on success, -errno otherwise. 1983 */ 1984 static int spi_nor_parse_sfdp(struct spi_nor *nor, 1985 struct spi_nor_flash_parameter *params) 1986 { 1987 const struct sfdp_parameter_header *param_header, *bfpt_header; 1988 struct sfdp_parameter_header *param_headers = NULL; 1989 struct sfdp_header header; 1990 size_t psize; 1991 int i, err; 1992 1993 /* Get the SFDP header. */ 1994 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header); 1995 if (err < 0) 1996 return err; 1997 1998 /* Check the SFDP header version. */ 1999 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE || 2000 header.major != SFDP_JESD216_MAJOR) 2001 return -EINVAL; 2002 2003 /* 2004 * Verify that the first and only mandatory parameter header is a 2005 * Basic Flash Parameter Table header as specified in JESD216. 2006 */ 2007 bfpt_header = &header.bfpt_header; 2008 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID || 2009 bfpt_header->major != SFDP_JESD216_MAJOR) 2010 return -EINVAL; 2011 2012 /* 2013 * Allocate memory then read all parameter headers with a single 2014 * Read SFDP command. These parameter headers will actually be parsed 2015 * twice: a first time to get the latest revision of the basic flash 2016 * parameter table, then a second time to handle the supported optional 2017 * tables. 2018 * Hence we read the parameter headers once for all to reduce the 2019 * processing time. Also we use kmalloc() instead of devm_kmalloc() 2020 * because we don't need to keep these parameter headers: the allocated 2021 * memory is always released with kfree() before exiting this function. 2022 */ 2023 if (header.nph) { 2024 psize = header.nph * sizeof(*param_headers); 2025 2026 param_headers = kmalloc(psize, GFP_KERNEL); 2027 if (!param_headers) 2028 return -ENOMEM; 2029 2030 err = spi_nor_read_sfdp(nor, sizeof(header), 2031 psize, param_headers); 2032 if (err < 0) { 2033 dev_err(dev, "failed to read SFDP parameter headers\n"); 2034 goto exit; 2035 } 2036 } 2037 2038 /* 2039 * Check other parameter headers to get the latest revision of 2040 * the basic flash parameter table. 2041 */ 2042 for (i = 0; i < header.nph; i++) { 2043 param_header = ¶m_headers[i]; 2044 2045 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID && 2046 param_header->major == SFDP_JESD216_MAJOR && 2047 (param_header->minor > bfpt_header->minor || 2048 (param_header->minor == bfpt_header->minor && 2049 param_header->length > bfpt_header->length))) 2050 bfpt_header = param_header; 2051 } 2052 2053 err = spi_nor_parse_bfpt(nor, bfpt_header, params); 2054 if (err) 2055 goto exit; 2056 2057 /* Parse other parameter headers. */ 2058 for (i = 0; i < header.nph; i++) { 2059 param_header = ¶m_headers[i]; 2060 2061 switch (SFDP_PARAM_HEADER_ID(param_header)) { 2062 case SFDP_SECTOR_MAP_ID: 2063 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n"); 2064 break; 2065 2066 default: 2067 break; 2068 } 2069 2070 if (err) 2071 goto exit; 2072 } 2073 2074 exit: 2075 kfree(param_headers); 2076 return err; 2077 } 2078 #else 2079 static int spi_nor_parse_sfdp(struct spi_nor *nor, 2080 struct spi_nor_flash_parameter *params) 2081 { 2082 return -EINVAL; 2083 } 2084 #endif /* SPI_FLASH_SFDP_SUPPORT */ 2085 2086 static int spi_nor_init_params(struct spi_nor *nor, 2087 const struct flash_info *info, 2088 struct spi_nor_flash_parameter *params) 2089 { 2090 /* Set legacy flash parameters as default. */ 2091 memset(params, 0, sizeof(*params)); 2092 2093 /* Set SPI NOR sizes. */ 2094 params->size = info->sector_size * info->n_sectors; 2095 params->page_size = info->page_size; 2096 2097 /* (Fast) Read settings. */ 2098 params->hwcaps.mask |= SNOR_HWCAPS_READ; 2099 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 2100 0, 0, SPINOR_OP_READ, 2101 SNOR_PROTO_1_1_1); 2102 2103 if (!(info->flags & SPI_NOR_NO_FR)) { 2104 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 2105 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 2106 0, 8, SPINOR_OP_READ_FAST, 2107 SNOR_PROTO_1_1_1); 2108 } 2109 2110 if (info->flags & SPI_NOR_DUAL_READ) { 2111 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2112 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 2113 0, 8, SPINOR_OP_READ_1_1_2, 2114 SNOR_PROTO_1_1_2); 2115 } 2116 2117 if (info->flags & SPI_NOR_QUAD_READ) { 2118 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2119 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 2120 0, 8, SPINOR_OP_READ_1_1_4, 2121 SNOR_PROTO_1_1_4); 2122 } 2123 2124 /* Page Program settings. */ 2125 params->hwcaps.mask |= SNOR_HWCAPS_PP; 2126 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 2127 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 2128 2129 if (info->flags & SPI_NOR_QUAD_READ) { 2130 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; 2131 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], 2132 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4); 2133 } 2134 2135 /* Select the procedure to set the Quad Enable bit. */ 2136 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD | 2137 SNOR_HWCAPS_PP_QUAD)) { 2138 switch (JEDEC_MFR(info)) { 2139 #ifdef CONFIG_SPI_FLASH_MACRONIX 2140 case SNOR_MFR_MACRONIX: 2141 params->quad_enable = macronix_quad_enable; 2142 break; 2143 #endif 2144 case SNOR_MFR_ST: 2145 case SNOR_MFR_MICRON: 2146 break; 2147 2148 default: 2149 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 2150 /* Kept only for backward compatibility purpose. */ 2151 params->quad_enable = spansion_read_cr_quad_enable; 2152 #endif 2153 break; 2154 } 2155 } 2156 2157 /* Override the parameters with data read from SFDP tables. */ 2158 nor->addr_width = 0; 2159 nor->mtd.erasesize = 0; 2160 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) && 2161 !(info->flags & SPI_NOR_SKIP_SFDP)) { 2162 struct spi_nor_flash_parameter sfdp_params; 2163 2164 memcpy(&sfdp_params, params, sizeof(sfdp_params)); 2165 if (spi_nor_parse_sfdp(nor, &sfdp_params)) { 2166 nor->addr_width = 0; 2167 nor->mtd.erasesize = 0; 2168 } else { 2169 memcpy(params, &sfdp_params, sizeof(*params)); 2170 } 2171 } 2172 2173 return 0; 2174 } 2175 2176 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 2177 { 2178 size_t i; 2179 2180 for (i = 0; i < size; i++) 2181 if (table[i][0] == (int)hwcaps) 2182 return table[i][1]; 2183 2184 return -EINVAL; 2185 } 2186 2187 static int spi_nor_hwcaps_read2cmd(u32 hwcaps) 2188 { 2189 static const int hwcaps_read2cmd[][2] = { 2190 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 2191 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 2192 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 2193 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 2194 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 2195 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 2196 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 2197 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 2198 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 2199 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 2200 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 2201 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 2202 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 2203 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 2204 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 2205 }; 2206 2207 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 2208 ARRAY_SIZE(hwcaps_read2cmd)); 2209 } 2210 2211 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 2212 { 2213 static const int hwcaps_pp2cmd[][2] = { 2214 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 2215 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 2216 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 2217 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 2218 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 2219 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 2220 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 2221 }; 2222 2223 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 2224 ARRAY_SIZE(hwcaps_pp2cmd)); 2225 } 2226 2227 static int spi_nor_select_read(struct spi_nor *nor, 2228 const struct spi_nor_flash_parameter *params, 2229 u32 shared_hwcaps) 2230 { 2231 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2232 const struct spi_nor_read_command *read; 2233 2234 if (best_match < 0) 2235 return -EINVAL; 2236 2237 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2238 if (cmd < 0) 2239 return -EINVAL; 2240 2241 read = ¶ms->reads[cmd]; 2242 nor->read_opcode = read->opcode; 2243 nor->read_proto = read->proto; 2244 2245 /* 2246 * In the spi-nor framework, we don't need to make the difference 2247 * between mode clock cycles and wait state clock cycles. 2248 * Indeed, the value of the mode clock cycles is used by a QSPI 2249 * flash memory to know whether it should enter or leave its 0-4-4 2250 * (Continuous Read / XIP) mode. 2251 * eXecution In Place is out of the scope of the mtd sub-system. 2252 * Hence we choose to merge both mode and wait state clock cycles 2253 * into the so called dummy clock cycles. 2254 */ 2255 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2256 return 0; 2257 } 2258 2259 static int spi_nor_select_pp(struct spi_nor *nor, 2260 const struct spi_nor_flash_parameter *params, 2261 u32 shared_hwcaps) 2262 { 2263 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2264 const struct spi_nor_pp_command *pp; 2265 2266 if (best_match < 0) 2267 return -EINVAL; 2268 2269 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2270 if (cmd < 0) 2271 return -EINVAL; 2272 2273 pp = ¶ms->page_programs[cmd]; 2274 nor->program_opcode = pp->opcode; 2275 nor->write_proto = pp->proto; 2276 return 0; 2277 } 2278 2279 static int spi_nor_select_erase(struct spi_nor *nor, 2280 const struct flash_info *info) 2281 { 2282 struct mtd_info *mtd = &nor->mtd; 2283 2284 /* Do nothing if already configured from SFDP. */ 2285 if (mtd->erasesize) 2286 return 0; 2287 2288 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 2289 /* prefer "small sector" erase if possible */ 2290 if (info->flags & SECT_4K) { 2291 nor->erase_opcode = SPINOR_OP_BE_4K; 2292 mtd->erasesize = 4096; 2293 } else if (info->flags & SECT_4K_PMC) { 2294 nor->erase_opcode = SPINOR_OP_BE_4K_PMC; 2295 mtd->erasesize = 4096; 2296 } else 2297 #endif 2298 { 2299 nor->erase_opcode = SPINOR_OP_SE; 2300 mtd->erasesize = info->sector_size; 2301 } 2302 return 0; 2303 } 2304 2305 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, 2306 const struct spi_nor_flash_parameter *params, 2307 const struct spi_nor_hwcaps *hwcaps) 2308 { 2309 u32 ignored_mask, shared_mask; 2310 bool enable_quad_io; 2311 int err; 2312 2313 /* 2314 * Keep only the hardware capabilities supported by both the SPI 2315 * controller and the SPI flash memory. 2316 */ 2317 shared_mask = hwcaps->mask & params->hwcaps.mask; 2318 2319 /* SPI n-n-n protocols are not supported yet. */ 2320 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 | 2321 SNOR_HWCAPS_READ_4_4_4 | 2322 SNOR_HWCAPS_READ_8_8_8 | 2323 SNOR_HWCAPS_PP_4_4_4 | 2324 SNOR_HWCAPS_PP_8_8_8); 2325 if (shared_mask & ignored_mask) { 2326 dev_dbg(nor->dev, 2327 "SPI n-n-n protocols are not supported yet.\n"); 2328 shared_mask &= ~ignored_mask; 2329 } 2330 2331 /* Select the (Fast) Read command. */ 2332 err = spi_nor_select_read(nor, params, shared_mask); 2333 if (err) { 2334 dev_dbg(nor->dev, 2335 "can't select read settings supported by both the SPI controller and memory.\n"); 2336 return err; 2337 } 2338 2339 /* Select the Page Program command. */ 2340 err = spi_nor_select_pp(nor, params, shared_mask); 2341 if (err) { 2342 dev_dbg(nor->dev, 2343 "can't select write settings supported by both the SPI controller and memory.\n"); 2344 return err; 2345 } 2346 2347 /* Select the Sector Erase command. */ 2348 err = spi_nor_select_erase(nor, info); 2349 if (err) { 2350 dev_dbg(nor->dev, 2351 "can't select erase settings supported by both the SPI controller and memory.\n"); 2352 return err; 2353 } 2354 2355 /* Enable Quad I/O if needed. */ 2356 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 || 2357 spi_nor_get_protocol_width(nor->write_proto) == 4); 2358 if (enable_quad_io && params->quad_enable) 2359 nor->quad_enable = params->quad_enable; 2360 else 2361 nor->quad_enable = NULL; 2362 2363 return 0; 2364 } 2365 2366 static int spi_nor_init(struct spi_nor *nor) 2367 { 2368 int err; 2369 2370 /* 2371 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up 2372 * with the software protection bits set 2373 */ 2374 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || 2375 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || 2376 JEDEC_MFR(nor->info) == SNOR_MFR_SST || 2377 nor->info->flags & SPI_NOR_HAS_LOCK) { 2378 write_enable(nor); 2379 write_sr(nor, 0); 2380 spi_nor_wait_till_ready(nor); 2381 } 2382 2383 if (nor->quad_enable) { 2384 err = nor->quad_enable(nor); 2385 if (err) { 2386 dev_dbg(nor->dev, "quad mode not supported\n"); 2387 return err; 2388 } 2389 } 2390 2391 if (nor->addr_width == 4 && 2392 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) && 2393 !(nor->info->flags & SPI_NOR_4B_OPCODES)) { 2394 /* 2395 * If the RESET# pin isn't hooked up properly, or the system 2396 * otherwise doesn't perform a reset command in the boot 2397 * sequence, it's impossible to 100% protect against unexpected 2398 * reboots (e.g., crashes). Warn the user (or hopefully, system 2399 * designer) that this is bad. 2400 */ 2401 if (nor->flags & SNOR_F_BROKEN_RESET) 2402 printf("enabling reset hack; may not recover from unexpected reboots\n"); 2403 set_4byte(nor, nor->info, 1); 2404 } 2405 2406 return 0; 2407 } 2408 2409 int spi_nor_scan(struct spi_nor *nor) 2410 { 2411 struct spi_nor_flash_parameter params; 2412 const struct flash_info *info = NULL; 2413 struct mtd_info *mtd = &nor->mtd; 2414 struct spi_nor_hwcaps hwcaps = { 2415 .mask = SNOR_HWCAPS_READ | 2416 SNOR_HWCAPS_READ_FAST | 2417 SNOR_HWCAPS_PP, 2418 }; 2419 struct spi_slave *spi = nor->spi; 2420 int ret; 2421 2422 /* Reset SPI protocol for all commands. */ 2423 nor->reg_proto = SNOR_PROTO_1_1_1; 2424 nor->read_proto = SNOR_PROTO_1_1_1; 2425 nor->write_proto = SNOR_PROTO_1_1_1; 2426 nor->read = spi_nor_read_data; 2427 nor->write = spi_nor_write_data; 2428 nor->read_reg = spi_nor_read_reg; 2429 nor->write_reg = spi_nor_write_reg; 2430 2431 if (spi->mode & SPI_RX_QUAD) { 2432 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2433 2434 if (spi->mode & SPI_TX_QUAD) 2435 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 | 2436 SNOR_HWCAPS_PP_1_1_4 | 2437 SNOR_HWCAPS_PP_1_4_4); 2438 } else if (spi->mode & SPI_RX_DUAL) { 2439 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2440 2441 if (spi->mode & SPI_TX_DUAL) 2442 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2; 2443 } 2444 2445 info = spi_nor_read_id(nor); 2446 if (IS_ERR_OR_NULL(info)) 2447 return -ENOENT; 2448 /* Parse the Serial Flash Discoverable Parameters table. */ 2449 ret = spi_nor_init_params(nor, info, ¶ms); 2450 if (ret) 2451 return ret; 2452 2453 if (!mtd->name) 2454 mtd->name = info->name; 2455 mtd->priv = nor; 2456 mtd->type = MTD_NORFLASH; 2457 mtd->writesize = 1; 2458 mtd->flags = MTD_CAP_NORFLASH; 2459 mtd->size = params.size; 2460 mtd->_erase = spi_nor_erase; 2461 mtd->_read = spi_nor_read; 2462 2463 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 2464 /* NOR protection support for STmicro/Micron chips and similar */ 2465 if (JEDEC_MFR(info) == SNOR_MFR_ST || 2466 JEDEC_MFR(info) == SNOR_MFR_MICRON || 2467 JEDEC_MFR(info) == SNOR_MFR_SST || 2468 info->flags & SPI_NOR_HAS_LOCK) { 2469 nor->flash_lock = stm_lock; 2470 nor->flash_unlock = stm_unlock; 2471 nor->flash_is_locked = stm_is_locked; 2472 } 2473 #endif 2474 2475 #ifdef CONFIG_SPI_FLASH_SST 2476 /* 2477 * sst26 series block protection implementation differs from other 2478 * series. 2479 */ 2480 if (info->flags & SPI_NOR_HAS_SST26LOCK) { 2481 nor->flash_lock = sst26_lock; 2482 nor->flash_unlock = sst26_unlock; 2483 nor->flash_is_locked = sst26_is_locked; 2484 } 2485 2486 /* sst nor chips use AAI word program */ 2487 if (info->flags & SST_WRITE) 2488 mtd->_write = sst_write; 2489 else 2490 #endif 2491 mtd->_write = spi_nor_write; 2492 2493 if (info->flags & USE_FSR) 2494 nor->flags |= SNOR_F_USE_FSR; 2495 if (info->flags & SPI_NOR_HAS_TB) 2496 nor->flags |= SNOR_F_HAS_SR_TB; 2497 if (info->flags & NO_CHIP_ERASE) 2498 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 2499 if (info->flags & USE_CLSR) 2500 nor->flags |= SNOR_F_USE_CLSR; 2501 2502 if (info->flags & SPI_NOR_NO_ERASE) 2503 mtd->flags |= MTD_NO_ERASE; 2504 2505 nor->page_size = params.page_size; 2506 mtd->writebufsize = nor->page_size; 2507 2508 /* Some devices cannot do fast-read, no matter what DT tells us */ 2509 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW)) 2510 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 2511 2512 /* 2513 * Configure the SPI memory: 2514 * - select op codes for (Fast) Read, Page Program and Sector Erase. 2515 * - set the number of dummy cycles (mode cycles + wait states). 2516 * - set the SPI protocols for register and memory accesses. 2517 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos). 2518 */ 2519 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps); 2520 if (ret) 2521 return ret; 2522 2523 if (nor->addr_width) { 2524 /* already configured from SFDP */ 2525 } else if (info->addr_width) { 2526 nor->addr_width = info->addr_width; 2527 } else if (mtd->size > SZ_16M) { 2528 #ifndef CONFIG_SPI_FLASH_BAR 2529 /* enable 4-byte addressing if the device exceeds 16MiB */ 2530 nor->addr_width = 4; 2531 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || 2532 info->flags & SPI_NOR_4B_OPCODES) 2533 spi_nor_set_4byte_opcodes(nor, info); 2534 #else 2535 /* Configure the BAR - discover bank cmds and read current bank */ 2536 nor->addr_width = 3; 2537 ret = read_bar(nor, info); 2538 if (ret < 0) 2539 return ret; 2540 #endif 2541 } else { 2542 nor->addr_width = 3; 2543 } 2544 2545 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 2546 dev_dbg(dev, "address width is too large: %u\n", 2547 nor->addr_width); 2548 return -EINVAL; 2549 } 2550 2551 /* Send all the required SPI flash commands to initialize device */ 2552 nor->info = info; 2553 ret = spi_nor_init(nor); 2554 if (ret) 2555 return ret; 2556 2557 nor->name = mtd->name; 2558 nor->size = mtd->size; 2559 nor->erase_size = mtd->erasesize; 2560 nor->sector_size = mtd->erasesize; 2561 2562 #ifndef CONFIG_SPL_BUILD 2563 printf("SF: Detected %s with page size ", nor->name); 2564 print_size(nor->page_size, ", erase size "); 2565 print_size(nor->erase_size, ", total "); 2566 print_size(nor->size, ""); 2567 puts("\n"); 2568 #endif 2569 2570 return 0; 2571 } 2572 2573 /* U-Boot specific functions, need to extend MTD to support these */ 2574 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor) 2575 { 2576 int sr = read_sr(nor); 2577 2578 if (sr < 0) 2579 return sr; 2580 2581 return (sr >> 2) & 7; 2582 } 2583