1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 * 9 * Synced from Linux v4.19 10 */ 11 12 #include <common.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/log2.h> 16 #include <linux/math64.h> 17 #include <linux/sizes.h> 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/mtd/spi-nor.h> 21 #include <spi-mem.h> 22 #include <spi.h> 23 24 /* Define max times to check status register before we give up. */ 25 26 /* 27 * For everything but full-chip erase; probably could be much smaller, but kept 28 * around for safety for now 29 */ 30 31 #define HZ CONFIG_SYS_HZ 32 33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 34 35 #define SPI_NOR_MAX_ID_LEN 6 36 #define SPI_NOR_MAX_ADDR_WIDTH 4 37 38 struct flash_info { 39 char *name; 40 41 /* 42 * This array stores the ID bytes. 43 * The first three bytes are the JEDIC ID. 44 * JEDEC ID zero means "no ID" (mostly older chips). 45 */ 46 u8 id[SPI_NOR_MAX_ID_LEN]; 47 u8 id_len; 48 49 /* The size listed here is what works with SPINOR_OP_SE, which isn't 50 * necessarily called a "sector" by the vendor. 51 */ 52 unsigned int sector_size; 53 u16 n_sectors; 54 55 u16 page_size; 56 u16 addr_width; 57 58 u16 flags; 59 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ 60 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ 61 #define SST_WRITE BIT(2) /* use SST byte programming */ 62 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ 63 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ 64 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ 65 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ 66 #define USE_FSR BIT(7) /* use flag status register */ 67 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ 68 #define SPI_NOR_HAS_TB BIT(9) /* 69 * Flash SR has Top/Bottom (TB) protect 70 * bit. Must be used with 71 * SPI_NOR_HAS_LOCK. 72 */ 73 #define SPI_S3AN BIT(10) /* 74 * Xilinx Spartan 3AN In-System Flash 75 * (MFR cannot be used for probing 76 * because it has the same value as 77 * ATMEL flashes) 78 */ 79 #define SPI_NOR_4B_OPCODES BIT(11) /* 80 * Use dedicated 4byte address op codes 81 * to support memory size above 128Mib. 82 */ 83 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ 84 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ 85 #define USE_CLSR BIT(14) /* use CLSR command */ 86 87 int (*quad_enable)(struct spi_nor *nor); 88 }; 89 90 #define JEDEC_MFR(info) ((info)->id[0]) 91 92 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op 93 *op, void *buf) 94 { 95 if (op->data.dir == SPI_MEM_DATA_IN) 96 op->data.buf.in = buf; 97 else 98 op->data.buf.out = buf; 99 return spi_mem_exec_op(nor->spi, op); 100 } 101 102 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) 103 { 104 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1), 105 SPI_MEM_OP_NO_ADDR, 106 SPI_MEM_OP_NO_DUMMY, 107 SPI_MEM_OP_DATA_IN(len, NULL, 1)); 108 int ret; 109 110 ret = spi_nor_read_write_reg(nor, &op, val); 111 if (ret < 0) 112 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret, 113 code); 114 115 return ret; 116 } 117 118 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) 119 { 120 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1), 121 SPI_MEM_OP_NO_ADDR, 122 SPI_MEM_OP_NO_DUMMY, 123 SPI_MEM_OP_DATA_OUT(len, NULL, 1)); 124 125 return spi_nor_read_write_reg(nor, &op, buf); 126 } 127 128 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, 129 u_char *buf) 130 { 131 struct spi_mem_op op = 132 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), 133 SPI_MEM_OP_ADDR(nor->addr_width, from, 1), 134 SPI_MEM_OP_DUMMY(nor->read_dummy, 1), 135 SPI_MEM_OP_DATA_IN(len, buf, 1)); 136 size_t remaining = len; 137 int ret; 138 139 /* get transfer protocols. */ 140 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); 141 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); 142 op.dummy.buswidth = op.addr.buswidth; 143 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 144 145 /* convert the dummy cycles to the number of bytes */ 146 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 147 148 while (remaining) { 149 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; 150 ret = spi_mem_adjust_op_size(nor->spi, &op); 151 if (ret) 152 return ret; 153 154 ret = spi_mem_exec_op(nor->spi, &op); 155 if (ret) 156 return ret; 157 158 op.addr.val += op.data.nbytes; 159 remaining -= op.data.nbytes; 160 op.data.buf.in += op.data.nbytes; 161 } 162 163 return len; 164 } 165 166 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 167 const u_char *buf) 168 { 169 struct spi_mem_op op = 170 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1), 171 SPI_MEM_OP_ADDR(nor->addr_width, to, 1), 172 SPI_MEM_OP_NO_DUMMY, 173 SPI_MEM_OP_DATA_OUT(len, buf, 1)); 174 size_t remaining = len; 175 int ret; 176 177 /* get transfer protocols. */ 178 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto); 179 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); 180 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 181 182 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 183 op.addr.nbytes = 0; 184 185 while (remaining) { 186 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; 187 ret = spi_mem_adjust_op_size(nor->spi, &op); 188 if (ret) 189 return ret; 190 191 ret = spi_mem_exec_op(nor->spi, &op); 192 if (ret) 193 return ret; 194 195 op.addr.val += op.data.nbytes; 196 remaining -= op.data.nbytes; 197 op.data.buf.out += op.data.nbytes; 198 } 199 200 return len; 201 } 202 203 /* 204 * Read the status register, returning its value in the location 205 * Return the status register value. 206 * Returns negative if error occurred. 207 */ 208 static int read_sr(struct spi_nor *nor) 209 { 210 int ret; 211 u8 val; 212 213 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); 214 if (ret < 0) { 215 pr_debug("error %d reading SR\n", (int)ret); 216 return ret; 217 } 218 219 return val; 220 } 221 222 /* 223 * Read the flag status register, returning its value in the location 224 * Return the status register value. 225 * Returns negative if error occurred. 226 */ 227 static int read_fsr(struct spi_nor *nor) 228 { 229 int ret; 230 u8 val; 231 232 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); 233 if (ret < 0) { 234 pr_debug("error %d reading FSR\n", ret); 235 return ret; 236 } 237 238 return val; 239 } 240 241 /* 242 * Read configuration register, returning its value in the 243 * location. Return the configuration register value. 244 * Returns negative if error occurred. 245 */ 246 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 247 static int read_cr(struct spi_nor *nor) 248 { 249 int ret; 250 u8 val; 251 252 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); 253 if (ret < 0) { 254 dev_dbg(nor->dev, "error %d reading CR\n", ret); 255 return ret; 256 } 257 258 return val; 259 } 260 #endif 261 262 /* 263 * Write status register 1 byte 264 * Returns negative if error occurred. 265 */ 266 static int write_sr(struct spi_nor *nor, u8 val) 267 { 268 nor->cmd_buf[0] = val; 269 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); 270 } 271 272 /* 273 * Set write enable latch with Write Enable command. 274 * Returns negative if error occurred. 275 */ 276 static int write_enable(struct spi_nor *nor) 277 { 278 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); 279 } 280 281 /* 282 * Send write disable instruction to the chip. 283 */ 284 static int write_disable(struct spi_nor *nor) 285 { 286 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); 287 } 288 289 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) 290 { 291 return mtd->priv; 292 } 293 294 #ifndef CONFIG_SPI_FLASH_BAR 295 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 296 { 297 size_t i; 298 299 for (i = 0; i < size; i++) 300 if (table[i][0] == opcode) 301 return table[i][1]; 302 303 /* No conversion found, keep input op code. */ 304 return opcode; 305 } 306 307 static u8 spi_nor_convert_3to4_read(u8 opcode) 308 { 309 static const u8 spi_nor_3to4_read[][2] = { 310 { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 311 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 312 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 313 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 314 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 315 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 316 317 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 318 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 319 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 320 }; 321 322 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 323 ARRAY_SIZE(spi_nor_3to4_read)); 324 } 325 326 static u8 spi_nor_convert_3to4_program(u8 opcode) 327 { 328 static const u8 spi_nor_3to4_program[][2] = { 329 { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 330 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 331 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 332 }; 333 334 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 335 ARRAY_SIZE(spi_nor_3to4_program)); 336 } 337 338 static u8 spi_nor_convert_3to4_erase(u8 opcode) 339 { 340 static const u8 spi_nor_3to4_erase[][2] = { 341 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 342 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 343 { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 344 }; 345 346 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 347 ARRAY_SIZE(spi_nor_3to4_erase)); 348 } 349 350 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, 351 const struct flash_info *info) 352 { 353 /* Do some manufacturer fixups first */ 354 switch (JEDEC_MFR(info)) { 355 case SNOR_MFR_SPANSION: 356 /* No small sector erase for 4-byte command set */ 357 nor->erase_opcode = SPINOR_OP_SE; 358 nor->mtd.erasesize = info->sector_size; 359 break; 360 361 default: 362 break; 363 } 364 365 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 366 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 367 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 368 } 369 #endif /* !CONFIG_SPI_FLASH_BAR */ 370 371 /* Enable/disable 4-byte addressing mode. */ 372 static int set_4byte(struct spi_nor *nor, const struct flash_info *info, 373 int enable) 374 { 375 int status; 376 bool need_wren = false; 377 u8 cmd; 378 379 switch (JEDEC_MFR(info)) { 380 case SNOR_MFR_ST: 381 case SNOR_MFR_MICRON: 382 /* Some Micron need WREN command; all will accept it */ 383 need_wren = true; 384 case SNOR_MFR_MACRONIX: 385 case SNOR_MFR_WINBOND: 386 if (need_wren) 387 write_enable(nor); 388 389 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; 390 status = nor->write_reg(nor, cmd, NULL, 0); 391 if (need_wren) 392 write_disable(nor); 393 394 if (!status && !enable && 395 JEDEC_MFR(info) == SNOR_MFR_WINBOND) { 396 /* 397 * On Winbond W25Q256FV, leaving 4byte mode causes 398 * the Extended Address Register to be set to 1, so all 399 * 3-byte-address reads come from the second 16M. 400 * We must clear the register to enable normal behavior. 401 */ 402 write_enable(nor); 403 nor->cmd_buf[0] = 0; 404 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1); 405 write_disable(nor); 406 } 407 408 return status; 409 default: 410 /* Spansion style */ 411 nor->cmd_buf[0] = enable << 7; 412 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); 413 } 414 } 415 416 static int spi_nor_sr_ready(struct spi_nor *nor) 417 { 418 int sr = read_sr(nor); 419 420 if (sr < 0) 421 return sr; 422 423 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) { 424 if (sr & SR_E_ERR) 425 dev_dbg(nor->dev, "Erase Error occurred\n"); 426 else 427 dev_dbg(nor->dev, "Programming Error occurred\n"); 428 429 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0); 430 return -EIO; 431 } 432 433 return !(sr & SR_WIP); 434 } 435 436 static int spi_nor_fsr_ready(struct spi_nor *nor) 437 { 438 int fsr = read_fsr(nor); 439 440 if (fsr < 0) 441 return fsr; 442 443 if (fsr & (FSR_E_ERR | FSR_P_ERR)) { 444 if (fsr & FSR_E_ERR) 445 dev_dbg(nor->dev, "Erase operation failed.\n"); 446 else 447 dev_dbg(nor->dev, "Program operation failed.\n"); 448 449 if (fsr & FSR_PT_ERR) 450 dev_dbg(nor->dev, 451 "Attempted to modify a protected sector.\n"); 452 453 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0); 454 return -EIO; 455 } 456 457 return fsr & FSR_READY; 458 } 459 460 static int spi_nor_ready(struct spi_nor *nor) 461 { 462 int sr, fsr; 463 464 sr = spi_nor_sr_ready(nor); 465 if (sr < 0) 466 return sr; 467 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; 468 if (fsr < 0) 469 return fsr; 470 return sr && fsr; 471 } 472 473 /* 474 * Service routine to read status register until ready, or timeout occurs. 475 * Returns non-zero if error. 476 */ 477 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 478 unsigned long timeout) 479 { 480 unsigned long timebase; 481 int ret; 482 483 timebase = get_timer(0); 484 485 while (get_timer(timebase) < timeout) { 486 ret = spi_nor_ready(nor); 487 if (ret < 0) 488 return ret; 489 if (ret) 490 return 0; 491 } 492 493 dev_err(nor->dev, "flash operation timed out\n"); 494 495 return -ETIMEDOUT; 496 } 497 498 static int spi_nor_wait_till_ready(struct spi_nor *nor) 499 { 500 return spi_nor_wait_till_ready_with_timeout(nor, 501 DEFAULT_READY_WAIT_JIFFIES); 502 } 503 504 #ifdef CONFIG_SPI_FLASH_BAR 505 /* 506 * This "clean_bar" is necessary in a situation when one was accessing 507 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit. 508 * 509 * After it the BA24 bit shall be cleared to allow access to correct 510 * memory region after SW reset (by calling "reset" command). 511 * 512 * Otherwise, the BA24 bit may be left set and then after reset, the 513 * ROM would read/write/erase SPL from 16 MiB * bank_sel address. 514 */ 515 static int clean_bar(struct spi_nor *nor) 516 { 517 u8 cmd, bank_sel = 0; 518 519 if (nor->bank_curr == 0) 520 return 0; 521 cmd = nor->bank_write_cmd; 522 nor->bank_curr = 0; 523 write_enable(nor); 524 525 return nor->write_reg(nor, cmd, &bank_sel, 1); 526 } 527 528 static int write_bar(struct spi_nor *nor, u32 offset) 529 { 530 u8 cmd, bank_sel; 531 int ret; 532 533 bank_sel = offset / SZ_16M; 534 if (bank_sel == nor->bank_curr) 535 goto bar_end; 536 537 cmd = nor->bank_write_cmd; 538 write_enable(nor); 539 ret = nor->write_reg(nor, cmd, &bank_sel, 1); 540 if (ret < 0) { 541 debug("SF: fail to write bank register\n"); 542 return ret; 543 } 544 545 bar_end: 546 nor->bank_curr = bank_sel; 547 return nor->bank_curr; 548 } 549 550 static int read_bar(struct spi_nor *nor, const struct flash_info *info) 551 { 552 u8 curr_bank = 0; 553 int ret; 554 555 switch (JEDEC_MFR(info)) { 556 case SNOR_MFR_SPANSION: 557 nor->bank_read_cmd = SPINOR_OP_BRRD; 558 nor->bank_write_cmd = SPINOR_OP_BRWR; 559 break; 560 default: 561 nor->bank_read_cmd = SPINOR_OP_RDEAR; 562 nor->bank_write_cmd = SPINOR_OP_WREAR; 563 } 564 565 ret = nor->read_reg(nor, nor->bank_read_cmd, 566 &curr_bank, 1); 567 if (ret) { 568 debug("SF: fail to read bank addr register\n"); 569 return ret; 570 } 571 nor->bank_curr = curr_bank; 572 573 return 0; 574 } 575 #endif 576 577 /* 578 * Initiate the erasure of a single sector 579 */ 580 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 581 { 582 u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; 583 int i; 584 585 if (nor->erase) 586 return nor->erase(nor, addr); 587 588 /* 589 * Default implementation, if driver doesn't have a specialized HW 590 * control 591 */ 592 for (i = nor->addr_width - 1; i >= 0; i--) { 593 buf[i] = addr & 0xff; 594 addr >>= 8; 595 } 596 597 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); 598 } 599 600 /* 601 * Erase an address range on the nor chip. The address range may extend 602 * one or more erase sectors. Return an error is there is a problem erasing. 603 */ 604 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 605 { 606 struct spi_nor *nor = mtd_to_spi_nor(mtd); 607 u32 addr, len, rem; 608 int ret; 609 610 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 611 (long long)instr->len); 612 613 div_u64_rem(instr->len, mtd->erasesize, &rem); 614 if (rem) 615 return -EINVAL; 616 617 addr = instr->addr; 618 len = instr->len; 619 620 while (len) { 621 #ifdef CONFIG_SPI_FLASH_BAR 622 ret = write_bar(nor, addr); 623 if (ret < 0) 624 return ret; 625 #endif 626 write_enable(nor); 627 628 ret = spi_nor_erase_sector(nor, addr); 629 if (ret) 630 goto erase_err; 631 632 addr += mtd->erasesize; 633 len -= mtd->erasesize; 634 635 ret = spi_nor_wait_till_ready(nor); 636 if (ret) 637 goto erase_err; 638 } 639 640 erase_err: 641 #ifdef CONFIG_SPI_FLASH_BAR 642 ret = clean_bar(nor); 643 #endif 644 write_disable(nor); 645 646 return ret; 647 } 648 649 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 650 /* Write status register and ensure bits in mask match written values */ 651 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) 652 { 653 int ret; 654 655 write_enable(nor); 656 ret = write_sr(nor, status_new); 657 if (ret) 658 return ret; 659 660 ret = spi_nor_wait_till_ready(nor); 661 if (ret) 662 return ret; 663 664 ret = read_sr(nor); 665 if (ret < 0) 666 return ret; 667 668 return ((ret & mask) != (status_new & mask)) ? -EIO : 0; 669 } 670 671 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, 672 uint64_t *len) 673 { 674 struct mtd_info *mtd = &nor->mtd; 675 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 676 int shift = ffs(mask) - 1; 677 int pow; 678 679 if (!(sr & mask)) { 680 /* No protection */ 681 *ofs = 0; 682 *len = 0; 683 } else { 684 pow = ((sr & mask) ^ mask) >> shift; 685 *len = mtd->size >> pow; 686 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) 687 *ofs = 0; 688 else 689 *ofs = mtd->size - *len; 690 } 691 } 692 693 /* 694 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if 695 * @locked is false); 0 otherwise 696 */ 697 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len, 698 u8 sr, bool locked) 699 { 700 loff_t lock_offs; 701 uint64_t lock_len; 702 703 if (!len) 704 return 1; 705 706 stm_get_locked_range(nor, sr, &lock_offs, &lock_len); 707 708 if (locked) 709 /* Requested range is a sub-range of locked range */ 710 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 711 else 712 /* Requested range does not overlap with locked range */ 713 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); 714 } 715 716 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 717 u8 sr) 718 { 719 return stm_check_lock_status_sr(nor, ofs, len, sr, true); 720 } 721 722 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 723 u8 sr) 724 { 725 return stm_check_lock_status_sr(nor, ofs, len, sr, false); 726 } 727 728 /* 729 * Lock a region of the flash. Compatible with ST Micro and similar flash. 730 * Supports the block protection bits BP{0,1,2} in the status register 731 * (SR). Does not support these features found in newer SR bitfields: 732 * - SEC: sector/block protect - only handle SEC=0 (block protect) 733 * - CMP: complement protect - only support CMP=0 (range is not complemented) 734 * 735 * Support for the following is provided conditionally for some flash: 736 * - TB: top/bottom protect 737 * 738 * Sample table portion for 8MB flash (Winbond w25q64fw): 739 * 740 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 741 * -------------------------------------------------------------------------- 742 * X | X | 0 | 0 | 0 | NONE | NONE 743 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 744 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 745 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 746 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 747 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 748 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 749 * X | X | 1 | 1 | 1 | 8 MB | ALL 750 * ------|-------|-------|-------|-------|---------------|------------------- 751 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 752 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 753 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 754 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 755 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 756 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 757 * 758 * Returns negative on errors, 0 on success. 759 */ 760 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 761 { 762 struct mtd_info *mtd = &nor->mtd; 763 int status_old, status_new; 764 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 765 u8 shift = ffs(mask) - 1, pow, val; 766 loff_t lock_len; 767 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 768 bool use_top; 769 770 status_old = read_sr(nor); 771 if (status_old < 0) 772 return status_old; 773 774 /* If nothing in our range is unlocked, we don't need to do anything */ 775 if (stm_is_locked_sr(nor, ofs, len, status_old)) 776 return 0; 777 778 /* If anything below us is unlocked, we can't use 'bottom' protection */ 779 if (!stm_is_locked_sr(nor, 0, ofs, status_old)) 780 can_be_bottom = false; 781 782 /* If anything above us is unlocked, we can't use 'top' protection */ 783 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), 784 status_old)) 785 can_be_top = false; 786 787 if (!can_be_bottom && !can_be_top) 788 return -EINVAL; 789 790 /* Prefer top, if both are valid */ 791 use_top = can_be_top; 792 793 /* lock_len: length of region that should end up locked */ 794 if (use_top) 795 lock_len = mtd->size - ofs; 796 else 797 lock_len = ofs + len; 798 799 /* 800 * Need smallest pow such that: 801 * 802 * 1 / (2^pow) <= (len / size) 803 * 804 * so (assuming power-of-2 size) we do: 805 * 806 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 807 */ 808 pow = ilog2(mtd->size) - ilog2(lock_len); 809 val = mask - (pow << shift); 810 if (val & ~mask) 811 return -EINVAL; 812 /* Don't "lock" with no region! */ 813 if (!(val & mask)) 814 return -EINVAL; 815 816 status_new = (status_old & ~mask & ~SR_TB) | val; 817 818 /* Disallow further writes if WP pin is asserted */ 819 status_new |= SR_SRWD; 820 821 if (!use_top) 822 status_new |= SR_TB; 823 824 /* Don't bother if they're the same */ 825 if (status_new == status_old) 826 return 0; 827 828 /* Only modify protection if it will not unlock other areas */ 829 if ((status_new & mask) < (status_old & mask)) 830 return -EINVAL; 831 832 return write_sr_and_check(nor, status_new, mask); 833 } 834 835 /* 836 * Unlock a region of the flash. See stm_lock() for more info 837 * 838 * Returns negative on errors, 0 on success. 839 */ 840 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 841 { 842 struct mtd_info *mtd = &nor->mtd; 843 int status_old, status_new; 844 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 845 u8 shift = ffs(mask) - 1, pow, val; 846 loff_t lock_len; 847 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 848 bool use_top; 849 850 status_old = read_sr(nor); 851 if (status_old < 0) 852 return status_old; 853 854 /* If nothing in our range is locked, we don't need to do anything */ 855 if (stm_is_unlocked_sr(nor, ofs, len, status_old)) 856 return 0; 857 858 /* If anything below us is locked, we can't use 'top' protection */ 859 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) 860 can_be_top = false; 861 862 /* If anything above us is locked, we can't use 'bottom' protection */ 863 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), 864 status_old)) 865 can_be_bottom = false; 866 867 if (!can_be_bottom && !can_be_top) 868 return -EINVAL; 869 870 /* Prefer top, if both are valid */ 871 use_top = can_be_top; 872 873 /* lock_len: length of region that should remain locked */ 874 if (use_top) 875 lock_len = mtd->size - (ofs + len); 876 else 877 lock_len = ofs; 878 879 /* 880 * Need largest pow such that: 881 * 882 * 1 / (2^pow) >= (len / size) 883 * 884 * so (assuming power-of-2 size) we do: 885 * 886 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 887 */ 888 pow = ilog2(mtd->size) - order_base_2(lock_len); 889 if (lock_len == 0) { 890 val = 0; /* fully unlocked */ 891 } else { 892 val = mask - (pow << shift); 893 /* Some power-of-two sizes are not supported */ 894 if (val & ~mask) 895 return -EINVAL; 896 } 897 898 status_new = (status_old & ~mask & ~SR_TB) | val; 899 900 /* Don't protect status register if we're fully unlocked */ 901 if (lock_len == 0) 902 status_new &= ~SR_SRWD; 903 904 if (!use_top) 905 status_new |= SR_TB; 906 907 /* Don't bother if they're the same */ 908 if (status_new == status_old) 909 return 0; 910 911 /* Only modify protection if it will not lock other areas */ 912 if ((status_new & mask) > (status_old & mask)) 913 return -EINVAL; 914 915 return write_sr_and_check(nor, status_new, mask); 916 } 917 918 /* 919 * Check if a region of the flash is (completely) locked. See stm_lock() for 920 * more info. 921 * 922 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 923 * negative on errors. 924 */ 925 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 926 { 927 int status; 928 929 status = read_sr(nor); 930 if (status < 0) 931 return status; 932 933 return stm_is_locked_sr(nor, ofs, len, status); 934 } 935 #endif /* CONFIG_SPI_FLASH_STMICRO */ 936 937 /* Used when the "_ext_id" is two bytes at most */ 938 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 939 .id = { \ 940 ((_jedec_id) >> 16) & 0xff, \ 941 ((_jedec_id) >> 8) & 0xff, \ 942 (_jedec_id) & 0xff, \ 943 ((_ext_id) >> 8) & 0xff, \ 944 (_ext_id) & 0xff, \ 945 }, \ 946 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 947 .sector_size = (_sector_size), \ 948 .n_sectors = (_n_sectors), \ 949 .page_size = 256, \ 950 .flags = (_flags), 951 952 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 953 .id = { \ 954 ((_jedec_id) >> 16) & 0xff, \ 955 ((_jedec_id) >> 8) & 0xff, \ 956 (_jedec_id) & 0xff, \ 957 ((_ext_id) >> 16) & 0xff, \ 958 ((_ext_id) >> 8) & 0xff, \ 959 (_ext_id) & 0xff, \ 960 }, \ 961 .id_len = 6, \ 962 .sector_size = (_sector_size), \ 963 .n_sectors = (_n_sectors), \ 964 .page_size = 256, \ 965 .flags = (_flags), 966 967 /* NOTE: double check command sets and memory organization when you add 968 * more nor chips. This current list focusses on newer chips, which 969 * have been converging on command sets which including JEDEC ID. 970 * 971 * All newly added entries should describe *hardware* and should use SECT_4K 972 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage 973 * scenarios excluding small sectors there is config option that can be 974 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. 975 * For historical (and compatibility) reasons (before we got above config) some 976 * old entries may be missing 4K flag. 977 */ 978 const struct flash_info spi_nor_ids[] = { 979 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ 980 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 981 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 982 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 983 984 { "at45db011d", INFO(0x1f2200, 0, 64 * 1024, 4, SECT_4K) }, 985 { "at45db021d", INFO(0x1f2300, 0, 64 * 1024, 8, SECT_4K) }, 986 { "at45db041d", INFO(0x1f2400, 0, 64 * 1024, 8, SECT_4K) }, 987 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 988 { "at45db161d", INFO(0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, 989 { "at45db321d", INFO(0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, 990 { "at45db641d", INFO(0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, 991 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 992 #endif 993 #ifdef CONFIG_SPI_FLASH_EON /* EON */ 994 /* EON -- en25xxx */ 995 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, 996 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 997 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, 998 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, 999 #endif 1000 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ 1001 /* GigaDevice */ 1002 { 1003 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32, 1004 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1005 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1006 }, 1007 { 1008 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, 1009 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1010 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1011 }, 1012 { 1013 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64, 1014 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1015 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1016 }, 1017 { 1018 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, 1019 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1020 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1021 }, 1022 #endif 1023 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ 1024 /* ISSI */ 1025 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8, 1026 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1027 { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64, 0) }, 1028 { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128, 0) }, 1029 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256, 1030 SECT_4K | SPI_NOR_DUAL_READ) }, 1031 { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512, 1032 SECT_4K | SPI_NOR_DUAL_READ) }, 1033 { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64, 1034 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1035 { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128, 1036 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1037 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256, 1038 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1039 #endif 1040 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ 1041 /* Macronix */ 1042 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 1043 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 1044 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, 1045 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 1046 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) }, 1047 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) }, 1048 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) }, 1049 { "mx25u1635e", INFO(0xc22535, 0, 64 * 1024, 32, SECT_4K) }, 1050 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 1051 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, 1052 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, 1053 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1054 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, 1055 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, 1056 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 1057 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 1058 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1059 { "mx25l1633e", INFO(0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, 1060 #endif 1061 1062 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 1063 /* Micron */ 1064 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, 1065 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 1066 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 1067 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 1068 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 1069 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 1070 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 1071 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1072 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, 1073 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 1074 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 1075 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 1076 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 1077 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 1078 #endif 1079 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ 1080 /* Spansion/Cypress -- single (large) sector size only, at least 1081 * for the chips listed here (without boot sectors). 1082 */ 1083 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1084 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1085 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) }, 1086 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1087 { "s25fl512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1088 { "s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1089 { "s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1090 { "s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1091 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, 1092 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, 1093 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1094 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1095 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 1096 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, 1097 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, 1098 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, 1099 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, 1100 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1101 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, 1102 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, 1103 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 1104 #endif 1105 #ifdef CONFIG_SPI_FLASH_SST /* SST */ 1106 /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 1107 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 1108 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 1109 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, 1110 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, 1111 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, 1112 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, 1113 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, 1114 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, 1115 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, 1116 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, 1117 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 1118 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 1119 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1120 { "sst26wf016", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K) }, 1121 { "sst26wf032", INFO(0xbf2622, 0, 64 * 1024, 64, SECT_4K) }, 1122 { "sst26wf064", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K) }, 1123 #endif 1124 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 1125 /* ST Microelectronics -- newer production may have feature updates */ 1126 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, 1127 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, 1128 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, 1129 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, 1130 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, 1131 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, 1132 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, 1133 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, 1134 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, 1135 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1136 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, 1137 #endif 1138 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ 1139 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 1140 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 1141 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, 1142 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, 1143 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 1144 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, 1145 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 1146 { 1147 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32, 1148 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1149 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1150 }, 1151 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 1152 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 1153 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 1154 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 1155 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, 1156 { 1157 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, 1158 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1159 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1160 }, 1161 { 1162 "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64, 1163 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1164 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1165 }, 1166 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 1167 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, 1168 { 1169 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, 1170 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1171 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1172 }, 1173 { 1174 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, 1175 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1176 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1177 }, 1178 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 1179 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, 1180 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, 1181 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1182 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, 1183 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, 1184 #endif 1185 #ifdef CONFIG_SPI_FLASH_XMC 1186 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 1187 { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1188 { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1189 #endif 1190 { }, 1191 }; 1192 1193 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 1194 { 1195 int tmp; 1196 u8 id[SPI_NOR_MAX_ID_LEN]; 1197 const struct flash_info *info; 1198 1199 if (!ARRAY_SIZE(spi_nor_ids)) 1200 return ERR_PTR(-ENODEV); 1201 1202 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); 1203 if (tmp < 0) { 1204 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); 1205 return ERR_PTR(tmp); 1206 } 1207 1208 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { 1209 info = &spi_nor_ids[tmp]; 1210 if (info->id_len) { 1211 if (!memcmp(info->id, id, info->id_len)) 1212 return &spi_nor_ids[tmp]; 1213 } 1214 } 1215 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", 1216 id[0], id[1], id[2]); 1217 return ERR_PTR(-ENODEV); 1218 } 1219 1220 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 1221 size_t *retlen, u_char *buf) 1222 { 1223 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1224 int ret; 1225 1226 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 1227 1228 while (len) { 1229 loff_t addr = from; 1230 size_t read_len = len; 1231 1232 #ifdef CONFIG_SPI_FLASH_BAR 1233 u32 remain_len; 1234 1235 ret = write_bar(nor, addr); 1236 if (ret < 0) 1237 return log_ret(ret); 1238 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr; 1239 1240 if (len < remain_len) 1241 read_len = len; 1242 else 1243 read_len = remain_len; 1244 #endif 1245 1246 ret = nor->read(nor, addr, read_len, buf); 1247 if (ret == 0) { 1248 /* We shouldn't see 0-length reads */ 1249 ret = -EIO; 1250 goto read_err; 1251 } 1252 if (ret < 0) 1253 goto read_err; 1254 1255 *retlen += ret; 1256 buf += ret; 1257 from += ret; 1258 len -= ret; 1259 } 1260 ret = 0; 1261 1262 read_err: 1263 #ifdef CONFIG_SPI_FLASH_BAR 1264 ret = clean_bar(nor); 1265 #endif 1266 return ret; 1267 } 1268 1269 #ifdef CONFIG_SPI_FLASH_SST 1270 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len, 1271 size_t *retlen, const u_char *buf) 1272 { 1273 size_t actual; 1274 int ret = 0; 1275 1276 for (actual = 0; actual < len; actual++) { 1277 nor->program_opcode = SPINOR_OP_BP; 1278 1279 write_enable(nor); 1280 /* write one byte. */ 1281 ret = nor->write(nor, to, 1, buf + actual); 1282 if (ret < 0) 1283 goto sst_write_err; 1284 ret = spi_nor_wait_till_ready(nor); 1285 if (ret) 1286 goto sst_write_err; 1287 to++; 1288 } 1289 1290 sst_write_err: 1291 write_disable(nor); 1292 return ret; 1293 } 1294 1295 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, 1296 size_t *retlen, const u_char *buf) 1297 { 1298 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1299 struct spi_slave *spi = nor->spi; 1300 size_t actual; 1301 int ret; 1302 1303 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 1304 if (spi->mode & SPI_TX_BYTE) 1305 return sst_write_byteprogram(nor, to, len, retlen, buf); 1306 1307 write_enable(nor); 1308 1309 nor->sst_write_second = false; 1310 1311 actual = to % 2; 1312 /* Start write from odd address. */ 1313 if (actual) { 1314 nor->program_opcode = SPINOR_OP_BP; 1315 1316 /* write one byte. */ 1317 ret = nor->write(nor, to, 1, buf); 1318 if (ret < 0) 1319 goto sst_write_err; 1320 ret = spi_nor_wait_till_ready(nor); 1321 if (ret) 1322 goto sst_write_err; 1323 } 1324 to += actual; 1325 1326 /* Write out most of the data here. */ 1327 for (; actual < len - 1; actual += 2) { 1328 nor->program_opcode = SPINOR_OP_AAI_WP; 1329 1330 /* write two bytes. */ 1331 ret = nor->write(nor, to, 2, buf + actual); 1332 if (ret < 0) 1333 goto sst_write_err; 1334 ret = spi_nor_wait_till_ready(nor); 1335 if (ret) 1336 goto sst_write_err; 1337 to += 2; 1338 nor->sst_write_second = true; 1339 } 1340 nor->sst_write_second = false; 1341 1342 write_disable(nor); 1343 ret = spi_nor_wait_till_ready(nor); 1344 if (ret) 1345 goto sst_write_err; 1346 1347 /* Write out trailing byte if it exists. */ 1348 if (actual != len) { 1349 write_enable(nor); 1350 1351 nor->program_opcode = SPINOR_OP_BP; 1352 ret = nor->write(nor, to, 1, buf + actual); 1353 if (ret < 0) 1354 goto sst_write_err; 1355 ret = spi_nor_wait_till_ready(nor); 1356 if (ret) 1357 goto sst_write_err; 1358 write_disable(nor); 1359 actual += 1; 1360 } 1361 sst_write_err: 1362 *retlen += actual; 1363 return ret; 1364 } 1365 #endif 1366 /* 1367 * Write an address range to the nor chip. Data must be written in 1368 * FLASH_PAGESIZE chunks. The address range may be any size provided 1369 * it is within the physical boundaries. 1370 */ 1371 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 1372 size_t *retlen, const u_char *buf) 1373 { 1374 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1375 size_t page_offset, page_remain, i; 1376 ssize_t ret; 1377 1378 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 1379 1380 for (i = 0; i < len; ) { 1381 ssize_t written; 1382 loff_t addr = to + i; 1383 1384 /* 1385 * If page_size is a power of two, the offset can be quickly 1386 * calculated with an AND operation. On the other cases we 1387 * need to do a modulus operation (more expensive). 1388 * Power of two numbers have only one bit set and we can use 1389 * the instruction hweight32 to detect if we need to do a 1390 * modulus (do_div()) or not. 1391 */ 1392 if (hweight32(nor->page_size) == 1) { 1393 page_offset = addr & (nor->page_size - 1); 1394 } else { 1395 u64 aux = addr; 1396 1397 page_offset = do_div(aux, nor->page_size); 1398 } 1399 /* the size of data remaining on the first page */ 1400 page_remain = min_t(size_t, 1401 nor->page_size - page_offset, len - i); 1402 1403 #ifdef CONFIG_SPI_FLASH_BAR 1404 ret = write_bar(nor, addr); 1405 if (ret < 0) 1406 return ret; 1407 #endif 1408 write_enable(nor); 1409 ret = nor->write(nor, addr, page_remain, buf + i); 1410 if (ret < 0) 1411 goto write_err; 1412 written = ret; 1413 1414 ret = spi_nor_wait_till_ready(nor); 1415 if (ret) 1416 goto write_err; 1417 *retlen += written; 1418 i += written; 1419 if (written != page_remain) { 1420 ret = -EIO; 1421 goto write_err; 1422 } 1423 } 1424 1425 write_err: 1426 #ifdef CONFIG_SPI_FLASH_BAR 1427 ret = clean_bar(nor); 1428 #endif 1429 return ret; 1430 } 1431 1432 #ifdef CONFIG_SPI_FLASH_MACRONIX 1433 /** 1434 * macronix_quad_enable() - set QE bit in Status Register. 1435 * @nor: pointer to a 'struct spi_nor' 1436 * 1437 * Set the Quad Enable (QE) bit in the Status Register. 1438 * 1439 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. 1440 * 1441 * Return: 0 on success, -errno otherwise. 1442 */ 1443 static int macronix_quad_enable(struct spi_nor *nor) 1444 { 1445 int ret, val; 1446 1447 val = read_sr(nor); 1448 if (val < 0) 1449 return val; 1450 if (val & SR_QUAD_EN_MX) 1451 return 0; 1452 1453 write_enable(nor); 1454 1455 write_sr(nor, val | SR_QUAD_EN_MX); 1456 1457 ret = spi_nor_wait_till_ready(nor); 1458 if (ret) 1459 return ret; 1460 1461 ret = read_sr(nor); 1462 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { 1463 dev_err(nor->dev, "Macronix Quad bit not set\n"); 1464 return -EINVAL; 1465 } 1466 1467 return 0; 1468 } 1469 #endif 1470 1471 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1472 /* 1473 * Write status Register and configuration register with 2 bytes 1474 * The first byte will be written to the status register, while the 1475 * second byte will be written to the configuration register. 1476 * Return negative if error occurred. 1477 */ 1478 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) 1479 { 1480 int ret; 1481 1482 write_enable(nor); 1483 1484 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2); 1485 if (ret < 0) { 1486 dev_dbg(nor->dev, 1487 "error while writing configuration register\n"); 1488 return -EINVAL; 1489 } 1490 1491 ret = spi_nor_wait_till_ready(nor); 1492 if (ret) { 1493 dev_dbg(nor->dev, 1494 "timeout while writing configuration register\n"); 1495 return ret; 1496 } 1497 1498 return 0; 1499 } 1500 1501 /** 1502 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. 1503 * @nor: pointer to a 'struct spi_nor' 1504 * 1505 * Set the Quad Enable (QE) bit in the Configuration Register. 1506 * This function should be used with QSPI memories supporting the Read 1507 * Configuration Register (35h) instruction. 1508 * 1509 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1510 * memories. 1511 * 1512 * Return: 0 on success, -errno otherwise. 1513 */ 1514 static int spansion_read_cr_quad_enable(struct spi_nor *nor) 1515 { 1516 u8 sr_cr[2]; 1517 int ret; 1518 1519 /* Check current Quad Enable bit value. */ 1520 ret = read_cr(nor); 1521 if (ret < 0) { 1522 dev_dbg(dev, "error while reading configuration register\n"); 1523 return -EINVAL; 1524 } 1525 1526 if (ret & CR_QUAD_EN_SPAN) 1527 return 0; 1528 1529 sr_cr[1] = ret | CR_QUAD_EN_SPAN; 1530 1531 /* Keep the current value of the Status Register. */ 1532 ret = read_sr(nor); 1533 if (ret < 0) { 1534 dev_dbg(dev, "error while reading status register\n"); 1535 return -EINVAL; 1536 } 1537 sr_cr[0] = ret; 1538 1539 ret = write_sr_cr(nor, sr_cr); 1540 if (ret) 1541 return ret; 1542 1543 /* Read back and check it. */ 1544 ret = read_cr(nor); 1545 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { 1546 dev_dbg(nor->dev, "Spansion Quad bit not set\n"); 1547 return -EINVAL; 1548 } 1549 1550 return 0; 1551 } 1552 1553 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1554 /** 1555 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register. 1556 * @nor: pointer to a 'struct spi_nor' 1557 * 1558 * Set the Quad Enable (QE) bit in the Configuration Register. 1559 * This function should be used with QSPI memories not supporting the Read 1560 * Configuration Register (35h) instruction. 1561 * 1562 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1563 * memories. 1564 * 1565 * Return: 0 on success, -errno otherwise. 1566 */ 1567 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) 1568 { 1569 u8 sr_cr[2]; 1570 int ret; 1571 1572 /* Keep the current value of the Status Register. */ 1573 ret = read_sr(nor); 1574 if (ret < 0) { 1575 dev_dbg(nor->dev, "error while reading status register\n"); 1576 return -EINVAL; 1577 } 1578 sr_cr[0] = ret; 1579 sr_cr[1] = CR_QUAD_EN_SPAN; 1580 1581 return write_sr_cr(nor, sr_cr); 1582 } 1583 1584 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */ 1585 #endif /* CONFIG_SPI_FLASH_SPANSION */ 1586 1587 struct spi_nor_read_command { 1588 u8 num_mode_clocks; 1589 u8 num_wait_states; 1590 u8 opcode; 1591 enum spi_nor_protocol proto; 1592 }; 1593 1594 struct spi_nor_pp_command { 1595 u8 opcode; 1596 enum spi_nor_protocol proto; 1597 }; 1598 1599 enum spi_nor_read_command_index { 1600 SNOR_CMD_READ, 1601 SNOR_CMD_READ_FAST, 1602 SNOR_CMD_READ_1_1_1_DTR, 1603 1604 /* Dual SPI */ 1605 SNOR_CMD_READ_1_1_2, 1606 SNOR_CMD_READ_1_2_2, 1607 SNOR_CMD_READ_2_2_2, 1608 SNOR_CMD_READ_1_2_2_DTR, 1609 1610 /* Quad SPI */ 1611 SNOR_CMD_READ_1_1_4, 1612 SNOR_CMD_READ_1_4_4, 1613 SNOR_CMD_READ_4_4_4, 1614 SNOR_CMD_READ_1_4_4_DTR, 1615 1616 /* Octo SPI */ 1617 SNOR_CMD_READ_1_1_8, 1618 SNOR_CMD_READ_1_8_8, 1619 SNOR_CMD_READ_8_8_8, 1620 SNOR_CMD_READ_1_8_8_DTR, 1621 1622 SNOR_CMD_READ_MAX 1623 }; 1624 1625 enum spi_nor_pp_command_index { 1626 SNOR_CMD_PP, 1627 1628 /* Quad SPI */ 1629 SNOR_CMD_PP_1_1_4, 1630 SNOR_CMD_PP_1_4_4, 1631 SNOR_CMD_PP_4_4_4, 1632 1633 /* Octo SPI */ 1634 SNOR_CMD_PP_1_1_8, 1635 SNOR_CMD_PP_1_8_8, 1636 SNOR_CMD_PP_8_8_8, 1637 1638 SNOR_CMD_PP_MAX 1639 }; 1640 1641 struct spi_nor_flash_parameter { 1642 u64 size; 1643 u32 page_size; 1644 1645 struct spi_nor_hwcaps hwcaps; 1646 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; 1647 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; 1648 1649 int (*quad_enable)(struct spi_nor *nor); 1650 }; 1651 1652 static void 1653 spi_nor_set_read_settings(struct spi_nor_read_command *read, 1654 u8 num_mode_clocks, 1655 u8 num_wait_states, 1656 u8 opcode, 1657 enum spi_nor_protocol proto) 1658 { 1659 read->num_mode_clocks = num_mode_clocks; 1660 read->num_wait_states = num_wait_states; 1661 read->opcode = opcode; 1662 read->proto = proto; 1663 } 1664 1665 static void 1666 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, 1667 u8 opcode, 1668 enum spi_nor_protocol proto) 1669 { 1670 pp->opcode = opcode; 1671 pp->proto = proto; 1672 } 1673 1674 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1675 /* 1676 * Serial Flash Discoverable Parameters (SFDP) parsing. 1677 */ 1678 1679 /** 1680 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters. 1681 * @nor: pointer to a 'struct spi_nor' 1682 * @addr: offset in the SFDP area to start reading data from 1683 * @len: number of bytes to read 1684 * @buf: buffer where the SFDP data are copied into (dma-safe memory) 1685 * 1686 * Whatever the actual numbers of bytes for address and dummy cycles are 1687 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always 1688 * followed by a 3-byte address and 8 dummy clock cycles. 1689 * 1690 * Return: 0 on success, -errno otherwise. 1691 */ 1692 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr, 1693 size_t len, void *buf) 1694 { 1695 u8 addr_width, read_opcode, read_dummy; 1696 int ret; 1697 1698 read_opcode = nor->read_opcode; 1699 addr_width = nor->addr_width; 1700 read_dummy = nor->read_dummy; 1701 1702 nor->read_opcode = SPINOR_OP_RDSFDP; 1703 nor->addr_width = 3; 1704 nor->read_dummy = 8; 1705 1706 while (len) { 1707 ret = nor->read(nor, addr, len, (u8 *)buf); 1708 if (!ret || ret > len) { 1709 ret = -EIO; 1710 goto read_err; 1711 } 1712 if (ret < 0) 1713 goto read_err; 1714 1715 buf += ret; 1716 addr += ret; 1717 len -= ret; 1718 } 1719 ret = 0; 1720 1721 read_err: 1722 nor->read_opcode = read_opcode; 1723 nor->addr_width = addr_width; 1724 nor->read_dummy = read_dummy; 1725 1726 return ret; 1727 } 1728 1729 struct sfdp_parameter_header { 1730 u8 id_lsb; 1731 u8 minor; 1732 u8 major; 1733 u8 length; /* in double words */ 1734 u8 parameter_table_pointer[3]; /* byte address */ 1735 u8 id_msb; 1736 }; 1737 1738 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) 1739 #define SFDP_PARAM_HEADER_PTP(p) \ 1740 (((p)->parameter_table_pointer[2] << 16) | \ 1741 ((p)->parameter_table_pointer[1] << 8) | \ 1742 ((p)->parameter_table_pointer[0] << 0)) 1743 1744 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ 1745 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ 1746 1747 #define SFDP_SIGNATURE 0x50444653U 1748 #define SFDP_JESD216_MAJOR 1 1749 #define SFDP_JESD216_MINOR 0 1750 #define SFDP_JESD216A_MINOR 5 1751 #define SFDP_JESD216B_MINOR 6 1752 1753 struct sfdp_header { 1754 u32 signature; /* Ox50444653U <=> "SFDP" */ 1755 u8 minor; 1756 u8 major; 1757 u8 nph; /* 0-base number of parameter headers */ 1758 u8 unused; 1759 1760 /* Basic Flash Parameter Table. */ 1761 struct sfdp_parameter_header bfpt_header; 1762 }; 1763 1764 /* Basic Flash Parameter Table */ 1765 1766 /* 1767 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. 1768 * They are indexed from 1 but C arrays are indexed from 0. 1769 */ 1770 #define BFPT_DWORD(i) ((i) - 1) 1771 #define BFPT_DWORD_MAX 16 1772 1773 /* The first version of JESB216 defined only 9 DWORDs. */ 1774 #define BFPT_DWORD_MAX_JESD216 9 1775 1776 /* 1st DWORD. */ 1777 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) 1778 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) 1779 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) 1780 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) 1781 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) 1782 #define BFPT_DWORD1_DTR BIT(19) 1783 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) 1784 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) 1785 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) 1786 1787 /* 5th DWORD. */ 1788 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) 1789 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) 1790 1791 /* 11th DWORD. */ 1792 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 1793 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) 1794 1795 /* 15th DWORD. */ 1796 1797 /* 1798 * (from JESD216 rev B) 1799 * Quad Enable Requirements (QER): 1800 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 1801 * reads based on instruction. DQ3/HOLD# functions are hold during 1802 * instruction phase. 1803 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with 1804 * two data bytes where bit 1 of the second byte is one. 1805 * [...] 1806 * Writing only one byte to the status register has the side-effect of 1807 * clearing status register 2, including the QE bit. The 100b code is 1808 * used if writing one byte to the status register does not modify 1809 * status register 2. 1810 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with 1811 * one data byte where bit 6 is one. 1812 * [...] 1813 * - 011b: QE is bit 7 of status register 2. It is set via Write status 1814 * register 2 instruction 3Eh with one data byte where bit 7 is one. 1815 * [...] 1816 * The status register 2 is read using instruction 3Fh. 1817 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with 1818 * two data bytes where bit 1 of the second byte is one. 1819 * [...] 1820 * In contrast to the 001b code, writing one byte to the status 1821 * register does not modify status register 2. 1822 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using 1823 * Read Status instruction 05h. Status register2 is read using 1824 * instruction 35h. QE is set via Writ Status instruction 01h with 1825 * two data bytes where bit 1 of the second byte is one. 1826 * [...] 1827 */ 1828 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) 1829 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ 1830 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) 1831 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ 1832 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) 1833 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) 1834 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ 1835 1836 struct sfdp_bfpt { 1837 u32 dwords[BFPT_DWORD_MAX]; 1838 }; 1839 1840 /* Fast Read settings. */ 1841 1842 static void 1843 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read, 1844 u16 half, 1845 enum spi_nor_protocol proto) 1846 { 1847 read->num_mode_clocks = (half >> 5) & 0x07; 1848 read->num_wait_states = (half >> 0) & 0x1f; 1849 read->opcode = (half >> 8) & 0xff; 1850 read->proto = proto; 1851 } 1852 1853 struct sfdp_bfpt_read { 1854 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */ 1855 u32 hwcaps; 1856 1857 /* 1858 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us 1859 * whether the Fast Read x-y-z command is supported. 1860 */ 1861 u32 supported_dword; 1862 u32 supported_bit; 1863 1864 /* 1865 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD 1866 * encodes the op code, the number of mode clocks and the number of wait 1867 * states to be used by Fast Read x-y-z command. 1868 */ 1869 u32 settings_dword; 1870 u32 settings_shift; 1871 1872 /* The SPI protocol for this Fast Read x-y-z command. */ 1873 enum spi_nor_protocol proto; 1874 }; 1875 1876 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = { 1877 /* Fast Read 1-1-2 */ 1878 { 1879 SNOR_HWCAPS_READ_1_1_2, 1880 BFPT_DWORD(1), BIT(16), /* Supported bit */ 1881 BFPT_DWORD(4), 0, /* Settings */ 1882 SNOR_PROTO_1_1_2, 1883 }, 1884 1885 /* Fast Read 1-2-2 */ 1886 { 1887 SNOR_HWCAPS_READ_1_2_2, 1888 BFPT_DWORD(1), BIT(20), /* Supported bit */ 1889 BFPT_DWORD(4), 16, /* Settings */ 1890 SNOR_PROTO_1_2_2, 1891 }, 1892 1893 /* Fast Read 2-2-2 */ 1894 { 1895 SNOR_HWCAPS_READ_2_2_2, 1896 BFPT_DWORD(5), BIT(0), /* Supported bit */ 1897 BFPT_DWORD(6), 16, /* Settings */ 1898 SNOR_PROTO_2_2_2, 1899 }, 1900 1901 /* Fast Read 1-1-4 */ 1902 { 1903 SNOR_HWCAPS_READ_1_1_4, 1904 BFPT_DWORD(1), BIT(22), /* Supported bit */ 1905 BFPT_DWORD(3), 16, /* Settings */ 1906 SNOR_PROTO_1_1_4, 1907 }, 1908 1909 /* Fast Read 1-4-4 */ 1910 { 1911 SNOR_HWCAPS_READ_1_4_4, 1912 BFPT_DWORD(1), BIT(21), /* Supported bit */ 1913 BFPT_DWORD(3), 0, /* Settings */ 1914 SNOR_PROTO_1_4_4, 1915 }, 1916 1917 /* Fast Read 4-4-4 */ 1918 { 1919 SNOR_HWCAPS_READ_4_4_4, 1920 BFPT_DWORD(5), BIT(4), /* Supported bit */ 1921 BFPT_DWORD(7), 16, /* Settings */ 1922 SNOR_PROTO_4_4_4, 1923 }, 1924 }; 1925 1926 struct sfdp_bfpt_erase { 1927 /* 1928 * The half-word at offset <shift> in DWORD <dwoard> encodes the 1929 * op code and erase sector size to be used by Sector Erase commands. 1930 */ 1931 u32 dword; 1932 u32 shift; 1933 }; 1934 1935 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = { 1936 /* Erase Type 1 in DWORD8 bits[15:0] */ 1937 {BFPT_DWORD(8), 0}, 1938 1939 /* Erase Type 2 in DWORD8 bits[31:16] */ 1940 {BFPT_DWORD(8), 16}, 1941 1942 /* Erase Type 3 in DWORD9 bits[15:0] */ 1943 {BFPT_DWORD(9), 0}, 1944 1945 /* Erase Type 4 in DWORD9 bits[31:16] */ 1946 {BFPT_DWORD(9), 16}, 1947 }; 1948 1949 static int spi_nor_hwcaps_read2cmd(u32 hwcaps); 1950 1951 /** 1952 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table. 1953 * @nor: pointer to a 'struct spi_nor' 1954 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing 1955 * the Basic Flash Parameter Table length and version 1956 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 1957 * filled 1958 * 1959 * The Basic Flash Parameter Table is the main and only mandatory table as 1960 * defined by the SFDP (JESD216) specification. 1961 * It provides us with the total size (memory density) of the data array and 1962 * the number of address bytes for Fast Read, Page Program and Sector Erase 1963 * commands. 1964 * For Fast READ commands, it also gives the number of mode clock cycles and 1965 * wait states (regrouped in the number of dummy clock cycles) for each 1966 * supported instruction op code. 1967 * For Page Program, the page size is now available since JESD216 rev A, however 1968 * the supported instruction op codes are still not provided. 1969 * For Sector Erase commands, this table stores the supported instruction op 1970 * codes and the associated sector sizes. 1971 * Finally, the Quad Enable Requirements (QER) are also available since JESD216 1972 * rev A. The QER bits encode the manufacturer dependent procedure to be 1973 * executed to set the Quad Enable (QE) bit in some internal register of the 1974 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before 1975 * sending any Quad SPI command to the memory. Actually, setting the QE bit 1976 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2 1977 * and IO3 hence enabling 4 (Quad) I/O lines. 1978 * 1979 * Return: 0 on success, -errno otherwise. 1980 */ 1981 static int spi_nor_parse_bfpt(struct spi_nor *nor, 1982 const struct sfdp_parameter_header *bfpt_header, 1983 struct spi_nor_flash_parameter *params) 1984 { 1985 struct mtd_info *mtd = &nor->mtd; 1986 struct sfdp_bfpt bfpt; 1987 size_t len; 1988 int i, cmd, err; 1989 u32 addr; 1990 u16 half; 1991 1992 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */ 1993 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216) 1994 return -EINVAL; 1995 1996 /* Read the Basic Flash Parameter Table. */ 1997 len = min_t(size_t, sizeof(bfpt), 1998 bfpt_header->length * sizeof(u32)); 1999 addr = SFDP_PARAM_HEADER_PTP(bfpt_header); 2000 memset(&bfpt, 0, sizeof(bfpt)); 2001 err = spi_nor_read_sfdp(nor, addr, len, &bfpt); 2002 if (err < 0) 2003 return err; 2004 2005 /* Fix endianness of the BFPT DWORDs. */ 2006 for (i = 0; i < BFPT_DWORD_MAX; i++) 2007 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]); 2008 2009 /* Number of address bytes. */ 2010 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) { 2011 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: 2012 nor->addr_width = 3; 2013 break; 2014 2015 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: 2016 nor->addr_width = 4; 2017 break; 2018 2019 default: 2020 break; 2021 } 2022 2023 /* Flash Memory Density (in bits). */ 2024 params->size = bfpt.dwords[BFPT_DWORD(2)]; 2025 if (params->size & BIT(31)) { 2026 params->size &= ~BIT(31); 2027 2028 /* 2029 * Prevent overflows on params->size. Anyway, a NOR of 2^64 2030 * bits is unlikely to exist so this error probably means 2031 * the BFPT we are reading is corrupted/wrong. 2032 */ 2033 if (params->size > 63) 2034 return -EINVAL; 2035 2036 params->size = 1ULL << params->size; 2037 } else { 2038 params->size++; 2039 } 2040 params->size >>= 3; /* Convert to bytes. */ 2041 2042 /* Fast Read settings. */ 2043 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) { 2044 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i]; 2045 struct spi_nor_read_command *read; 2046 2047 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) { 2048 params->hwcaps.mask &= ~rd->hwcaps; 2049 continue; 2050 } 2051 2052 params->hwcaps.mask |= rd->hwcaps; 2053 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps); 2054 read = ¶ms->reads[cmd]; 2055 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift; 2056 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto); 2057 } 2058 2059 /* Sector Erase settings. */ 2060 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) { 2061 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i]; 2062 u32 erasesize; 2063 u8 opcode; 2064 2065 half = bfpt.dwords[er->dword] >> er->shift; 2066 erasesize = half & 0xff; 2067 2068 /* erasesize == 0 means this Erase Type is not supported. */ 2069 if (!erasesize) 2070 continue; 2071 2072 erasesize = 1U << erasesize; 2073 opcode = (half >> 8) & 0xff; 2074 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS 2075 if (erasesize == SZ_4K) { 2076 nor->erase_opcode = opcode; 2077 mtd->erasesize = erasesize; 2078 break; 2079 } 2080 #endif 2081 if (!mtd->erasesize || mtd->erasesize < erasesize) { 2082 nor->erase_opcode = opcode; 2083 mtd->erasesize = erasesize; 2084 } 2085 } 2086 2087 /* Stop here if not JESD216 rev A or later. */ 2088 if (bfpt_header->length < BFPT_DWORD_MAX) 2089 return 0; 2090 2091 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */ 2092 params->page_size = bfpt.dwords[BFPT_DWORD(11)]; 2093 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK; 2094 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT; 2095 params->page_size = 1U << params->page_size; 2096 2097 /* Quad Enable Requirements. */ 2098 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { 2099 case BFPT_DWORD15_QER_NONE: 2100 params->quad_enable = NULL; 2101 break; 2102 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 2103 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: 2104 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: 2105 params->quad_enable = spansion_no_read_cr_quad_enable; 2106 break; 2107 #endif 2108 #ifdef CONFIG_SPI_FLASH_MACRONIX 2109 case BFPT_DWORD15_QER_SR1_BIT6: 2110 params->quad_enable = macronix_quad_enable; 2111 break; 2112 #endif 2113 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 2114 case BFPT_DWORD15_QER_SR2_BIT1: 2115 params->quad_enable = spansion_read_cr_quad_enable; 2116 break; 2117 #endif 2118 default: 2119 return -EINVAL; 2120 } 2121 2122 return 0; 2123 } 2124 2125 /** 2126 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters. 2127 * @nor: pointer to a 'struct spi_nor' 2128 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 2129 * filled 2130 * 2131 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216 2132 * specification. This is a standard which tends to supported by almost all 2133 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at 2134 * runtime the main parameters needed to perform basic SPI flash operations such 2135 * as Fast Read, Page Program or Sector Erase commands. 2136 * 2137 * Return: 0 on success, -errno otherwise. 2138 */ 2139 static int spi_nor_parse_sfdp(struct spi_nor *nor, 2140 struct spi_nor_flash_parameter *params) 2141 { 2142 const struct sfdp_parameter_header *param_header, *bfpt_header; 2143 struct sfdp_parameter_header *param_headers = NULL; 2144 struct sfdp_header header; 2145 size_t psize; 2146 int i, err; 2147 2148 /* Get the SFDP header. */ 2149 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header); 2150 if (err < 0) 2151 return err; 2152 2153 /* Check the SFDP header version. */ 2154 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE || 2155 header.major != SFDP_JESD216_MAJOR) 2156 return -EINVAL; 2157 2158 /* 2159 * Verify that the first and only mandatory parameter header is a 2160 * Basic Flash Parameter Table header as specified in JESD216. 2161 */ 2162 bfpt_header = &header.bfpt_header; 2163 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID || 2164 bfpt_header->major != SFDP_JESD216_MAJOR) 2165 return -EINVAL; 2166 2167 /* 2168 * Allocate memory then read all parameter headers with a single 2169 * Read SFDP command. These parameter headers will actually be parsed 2170 * twice: a first time to get the latest revision of the basic flash 2171 * parameter table, then a second time to handle the supported optional 2172 * tables. 2173 * Hence we read the parameter headers once for all to reduce the 2174 * processing time. Also we use kmalloc() instead of devm_kmalloc() 2175 * because we don't need to keep these parameter headers: the allocated 2176 * memory is always released with kfree() before exiting this function. 2177 */ 2178 if (header.nph) { 2179 psize = header.nph * sizeof(*param_headers); 2180 2181 param_headers = kmalloc(psize, GFP_KERNEL); 2182 if (!param_headers) 2183 return -ENOMEM; 2184 2185 err = spi_nor_read_sfdp(nor, sizeof(header), 2186 psize, param_headers); 2187 if (err < 0) { 2188 dev_err(dev, "failed to read SFDP parameter headers\n"); 2189 goto exit; 2190 } 2191 } 2192 2193 /* 2194 * Check other parameter headers to get the latest revision of 2195 * the basic flash parameter table. 2196 */ 2197 for (i = 0; i < header.nph; i++) { 2198 param_header = ¶m_headers[i]; 2199 2200 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID && 2201 param_header->major == SFDP_JESD216_MAJOR && 2202 (param_header->minor > bfpt_header->minor || 2203 (param_header->minor == bfpt_header->minor && 2204 param_header->length > bfpt_header->length))) 2205 bfpt_header = param_header; 2206 } 2207 2208 err = spi_nor_parse_bfpt(nor, bfpt_header, params); 2209 if (err) 2210 goto exit; 2211 2212 /* Parse other parameter headers. */ 2213 for (i = 0; i < header.nph; i++) { 2214 param_header = ¶m_headers[i]; 2215 2216 switch (SFDP_PARAM_HEADER_ID(param_header)) { 2217 case SFDP_SECTOR_MAP_ID: 2218 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n"); 2219 break; 2220 2221 default: 2222 break; 2223 } 2224 2225 if (err) 2226 goto exit; 2227 } 2228 2229 exit: 2230 kfree(param_headers); 2231 return err; 2232 } 2233 #else 2234 static int spi_nor_parse_sfdp(struct spi_nor *nor, 2235 struct spi_nor_flash_parameter *params) 2236 { 2237 return -EINVAL; 2238 } 2239 #endif /* SPI_FLASH_SFDP_SUPPORT */ 2240 2241 static int spi_nor_init_params(struct spi_nor *nor, 2242 const struct flash_info *info, 2243 struct spi_nor_flash_parameter *params) 2244 { 2245 /* Set legacy flash parameters as default. */ 2246 memset(params, 0, sizeof(*params)); 2247 2248 /* Set SPI NOR sizes. */ 2249 params->size = info->sector_size * info->n_sectors; 2250 params->page_size = info->page_size; 2251 2252 /* (Fast) Read settings. */ 2253 params->hwcaps.mask |= SNOR_HWCAPS_READ; 2254 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 2255 0, 0, SPINOR_OP_READ, 2256 SNOR_PROTO_1_1_1); 2257 2258 if (!(info->flags & SPI_NOR_NO_FR)) { 2259 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 2260 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 2261 0, 8, SPINOR_OP_READ_FAST, 2262 SNOR_PROTO_1_1_1); 2263 } 2264 2265 if (info->flags & SPI_NOR_DUAL_READ) { 2266 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2267 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 2268 0, 8, SPINOR_OP_READ_1_1_2, 2269 SNOR_PROTO_1_1_2); 2270 } 2271 2272 if (info->flags & SPI_NOR_QUAD_READ) { 2273 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2274 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 2275 0, 8, SPINOR_OP_READ_1_1_4, 2276 SNOR_PROTO_1_1_4); 2277 } 2278 2279 /* Page Program settings. */ 2280 params->hwcaps.mask |= SNOR_HWCAPS_PP; 2281 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 2282 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 2283 2284 if (info->flags & SPI_NOR_QUAD_READ) { 2285 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; 2286 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], 2287 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4); 2288 } 2289 2290 /* Select the procedure to set the Quad Enable bit. */ 2291 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD | 2292 SNOR_HWCAPS_PP_QUAD)) { 2293 switch (JEDEC_MFR(info)) { 2294 #ifdef CONFIG_SPI_FLASH_MACRONIX 2295 case SNOR_MFR_MACRONIX: 2296 params->quad_enable = macronix_quad_enable; 2297 break; 2298 #endif 2299 case SNOR_MFR_ST: 2300 case SNOR_MFR_MICRON: 2301 break; 2302 2303 default: 2304 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 2305 /* Kept only for backward compatibility purpose. */ 2306 params->quad_enable = spansion_read_cr_quad_enable; 2307 #endif 2308 break; 2309 } 2310 } 2311 2312 /* Override the parameters with data read from SFDP tables. */ 2313 nor->addr_width = 0; 2314 nor->mtd.erasesize = 0; 2315 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) && 2316 !(info->flags & SPI_NOR_SKIP_SFDP)) { 2317 struct spi_nor_flash_parameter sfdp_params; 2318 2319 memcpy(&sfdp_params, params, sizeof(sfdp_params)); 2320 if (spi_nor_parse_sfdp(nor, &sfdp_params)) { 2321 nor->addr_width = 0; 2322 nor->mtd.erasesize = 0; 2323 } else { 2324 memcpy(params, &sfdp_params, sizeof(*params)); 2325 } 2326 } 2327 2328 return 0; 2329 } 2330 2331 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 2332 { 2333 size_t i; 2334 2335 for (i = 0; i < size; i++) 2336 if (table[i][0] == (int)hwcaps) 2337 return table[i][1]; 2338 2339 return -EINVAL; 2340 } 2341 2342 static int spi_nor_hwcaps_read2cmd(u32 hwcaps) 2343 { 2344 static const int hwcaps_read2cmd[][2] = { 2345 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 2346 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 2347 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 2348 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 2349 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 2350 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 2351 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 2352 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 2353 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 2354 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 2355 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 2356 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 2357 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 2358 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 2359 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 2360 }; 2361 2362 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 2363 ARRAY_SIZE(hwcaps_read2cmd)); 2364 } 2365 2366 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 2367 { 2368 static const int hwcaps_pp2cmd[][2] = { 2369 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 2370 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 2371 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 2372 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 2373 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 2374 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 2375 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 2376 }; 2377 2378 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 2379 ARRAY_SIZE(hwcaps_pp2cmd)); 2380 } 2381 2382 static int spi_nor_select_read(struct spi_nor *nor, 2383 const struct spi_nor_flash_parameter *params, 2384 u32 shared_hwcaps) 2385 { 2386 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2387 const struct spi_nor_read_command *read; 2388 2389 if (best_match < 0) 2390 return -EINVAL; 2391 2392 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2393 if (cmd < 0) 2394 return -EINVAL; 2395 2396 read = ¶ms->reads[cmd]; 2397 nor->read_opcode = read->opcode; 2398 nor->read_proto = read->proto; 2399 2400 /* 2401 * In the spi-nor framework, we don't need to make the difference 2402 * between mode clock cycles and wait state clock cycles. 2403 * Indeed, the value of the mode clock cycles is used by a QSPI 2404 * flash memory to know whether it should enter or leave its 0-4-4 2405 * (Continuous Read / XIP) mode. 2406 * eXecution In Place is out of the scope of the mtd sub-system. 2407 * Hence we choose to merge both mode and wait state clock cycles 2408 * into the so called dummy clock cycles. 2409 */ 2410 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2411 return 0; 2412 } 2413 2414 static int spi_nor_select_pp(struct spi_nor *nor, 2415 const struct spi_nor_flash_parameter *params, 2416 u32 shared_hwcaps) 2417 { 2418 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2419 const struct spi_nor_pp_command *pp; 2420 2421 if (best_match < 0) 2422 return -EINVAL; 2423 2424 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2425 if (cmd < 0) 2426 return -EINVAL; 2427 2428 pp = ¶ms->page_programs[cmd]; 2429 nor->program_opcode = pp->opcode; 2430 nor->write_proto = pp->proto; 2431 return 0; 2432 } 2433 2434 static int spi_nor_select_erase(struct spi_nor *nor, 2435 const struct flash_info *info) 2436 { 2437 struct mtd_info *mtd = &nor->mtd; 2438 2439 /* Do nothing if already configured from SFDP. */ 2440 if (mtd->erasesize) 2441 return 0; 2442 2443 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 2444 /* prefer "small sector" erase if possible */ 2445 if (info->flags & SECT_4K) { 2446 nor->erase_opcode = SPINOR_OP_BE_4K; 2447 mtd->erasesize = 4096; 2448 } else if (info->flags & SECT_4K_PMC) { 2449 nor->erase_opcode = SPINOR_OP_BE_4K_PMC; 2450 mtd->erasesize = 4096; 2451 } else 2452 #endif 2453 { 2454 nor->erase_opcode = SPINOR_OP_SE; 2455 mtd->erasesize = info->sector_size; 2456 } 2457 return 0; 2458 } 2459 2460 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, 2461 const struct spi_nor_flash_parameter *params, 2462 const struct spi_nor_hwcaps *hwcaps) 2463 { 2464 u32 ignored_mask, shared_mask; 2465 bool enable_quad_io; 2466 int err; 2467 2468 /* 2469 * Keep only the hardware capabilities supported by both the SPI 2470 * controller and the SPI flash memory. 2471 */ 2472 shared_mask = hwcaps->mask & params->hwcaps.mask; 2473 2474 /* SPI n-n-n protocols are not supported yet. */ 2475 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 | 2476 SNOR_HWCAPS_READ_4_4_4 | 2477 SNOR_HWCAPS_READ_8_8_8 | 2478 SNOR_HWCAPS_PP_4_4_4 | 2479 SNOR_HWCAPS_PP_8_8_8); 2480 if (shared_mask & ignored_mask) { 2481 dev_dbg(nor->dev, 2482 "SPI n-n-n protocols are not supported yet.\n"); 2483 shared_mask &= ~ignored_mask; 2484 } 2485 2486 /* Select the (Fast) Read command. */ 2487 err = spi_nor_select_read(nor, params, shared_mask); 2488 if (err) { 2489 dev_dbg(nor->dev, 2490 "can't select read settings supported by both the SPI controller and memory.\n"); 2491 return err; 2492 } 2493 2494 /* Select the Page Program command. */ 2495 err = spi_nor_select_pp(nor, params, shared_mask); 2496 if (err) { 2497 dev_dbg(nor->dev, 2498 "can't select write settings supported by both the SPI controller and memory.\n"); 2499 return err; 2500 } 2501 2502 /* Select the Sector Erase command. */ 2503 err = spi_nor_select_erase(nor, info); 2504 if (err) { 2505 dev_dbg(nor->dev, 2506 "can't select erase settings supported by both the SPI controller and memory.\n"); 2507 return err; 2508 } 2509 2510 /* Enable Quad I/O if needed. */ 2511 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 || 2512 spi_nor_get_protocol_width(nor->write_proto) == 4); 2513 if (enable_quad_io && params->quad_enable) 2514 nor->quad_enable = params->quad_enable; 2515 else 2516 nor->quad_enable = NULL; 2517 2518 return 0; 2519 } 2520 2521 static int spi_nor_init(struct spi_nor *nor) 2522 { 2523 int err; 2524 2525 /* 2526 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up 2527 * with the software protection bits set 2528 */ 2529 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || 2530 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || 2531 JEDEC_MFR(nor->info) == SNOR_MFR_SST || 2532 nor->info->flags & SPI_NOR_HAS_LOCK) { 2533 write_enable(nor); 2534 write_sr(nor, 0); 2535 spi_nor_wait_till_ready(nor); 2536 } 2537 2538 if (nor->quad_enable) { 2539 err = nor->quad_enable(nor); 2540 if (err) { 2541 dev_dbg(nor->dev, "quad mode not supported\n"); 2542 return err; 2543 } 2544 } 2545 2546 if (nor->addr_width == 4 && 2547 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) && 2548 !(nor->info->flags & SPI_NOR_4B_OPCODES)) { 2549 /* 2550 * If the RESET# pin isn't hooked up properly, or the system 2551 * otherwise doesn't perform a reset command in the boot 2552 * sequence, it's impossible to 100% protect against unexpected 2553 * reboots (e.g., crashes). Warn the user (or hopefully, system 2554 * designer) that this is bad. 2555 */ 2556 if (nor->flags & SNOR_F_BROKEN_RESET) 2557 printf("enabling reset hack; may not recover from unexpected reboots\n"); 2558 set_4byte(nor, nor->info, 1); 2559 } 2560 2561 return 0; 2562 } 2563 2564 int spi_nor_scan(struct spi_nor *nor) 2565 { 2566 struct spi_nor_flash_parameter params; 2567 const struct flash_info *info = NULL; 2568 struct mtd_info *mtd = &nor->mtd; 2569 struct spi_nor_hwcaps hwcaps = { 2570 .mask = SNOR_HWCAPS_READ | 2571 SNOR_HWCAPS_READ_FAST | 2572 SNOR_HWCAPS_PP, 2573 }; 2574 struct spi_slave *spi = nor->spi; 2575 int ret; 2576 2577 /* Reset SPI protocol for all commands. */ 2578 nor->reg_proto = SNOR_PROTO_1_1_1; 2579 nor->read_proto = SNOR_PROTO_1_1_1; 2580 nor->write_proto = SNOR_PROTO_1_1_1; 2581 nor->read = spi_nor_read_data; 2582 nor->write = spi_nor_write_data; 2583 nor->read_reg = spi_nor_read_reg; 2584 nor->write_reg = spi_nor_write_reg; 2585 2586 if (spi->mode & SPI_RX_QUAD) { 2587 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2588 2589 if (spi->mode & SPI_TX_QUAD) 2590 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 | 2591 SNOR_HWCAPS_PP_1_1_4 | 2592 SNOR_HWCAPS_PP_1_4_4); 2593 } else if (spi->mode & SPI_RX_DUAL) { 2594 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2595 2596 if (spi->mode & SPI_TX_DUAL) 2597 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2; 2598 } 2599 2600 info = spi_nor_read_id(nor); 2601 if (IS_ERR_OR_NULL(info)) 2602 return -ENOENT; 2603 /* Parse the Serial Flash Discoverable Parameters table. */ 2604 ret = spi_nor_init_params(nor, info, ¶ms); 2605 if (ret) 2606 return ret; 2607 2608 if (!mtd->name) 2609 mtd->name = info->name; 2610 mtd->priv = nor; 2611 mtd->type = MTD_NORFLASH; 2612 mtd->writesize = 1; 2613 mtd->flags = MTD_CAP_NORFLASH; 2614 mtd->size = params.size; 2615 mtd->_erase = spi_nor_erase; 2616 mtd->_read = spi_nor_read; 2617 2618 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 2619 /* NOR protection support for STmicro/Micron chips and similar */ 2620 if (JEDEC_MFR(info) == SNOR_MFR_ST || 2621 JEDEC_MFR(info) == SNOR_MFR_MICRON || 2622 JEDEC_MFR(info) == SNOR_MFR_SST || 2623 info->flags & SPI_NOR_HAS_LOCK) { 2624 nor->flash_lock = stm_lock; 2625 nor->flash_unlock = stm_unlock; 2626 nor->flash_is_locked = stm_is_locked; 2627 } 2628 #endif 2629 2630 #ifdef CONFIG_SPI_FLASH_SST 2631 /* sst nor chips use AAI word program */ 2632 if (info->flags & SST_WRITE) 2633 mtd->_write = sst_write; 2634 else 2635 #endif 2636 mtd->_write = spi_nor_write; 2637 2638 if (info->flags & USE_FSR) 2639 nor->flags |= SNOR_F_USE_FSR; 2640 if (info->flags & SPI_NOR_HAS_TB) 2641 nor->flags |= SNOR_F_HAS_SR_TB; 2642 if (info->flags & NO_CHIP_ERASE) 2643 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 2644 if (info->flags & USE_CLSR) 2645 nor->flags |= SNOR_F_USE_CLSR; 2646 2647 if (info->flags & SPI_NOR_NO_ERASE) 2648 mtd->flags |= MTD_NO_ERASE; 2649 2650 nor->page_size = params.page_size; 2651 mtd->writebufsize = nor->page_size; 2652 2653 /* Some devices cannot do fast-read, no matter what DT tells us */ 2654 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW)) 2655 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 2656 2657 /* 2658 * Configure the SPI memory: 2659 * - select op codes for (Fast) Read, Page Program and Sector Erase. 2660 * - set the number of dummy cycles (mode cycles + wait states). 2661 * - set the SPI protocols for register and memory accesses. 2662 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos). 2663 */ 2664 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps); 2665 if (ret) 2666 return ret; 2667 2668 if (nor->addr_width) { 2669 /* already configured from SFDP */ 2670 } else if (info->addr_width) { 2671 nor->addr_width = info->addr_width; 2672 } else if (mtd->size > SZ_16M) { 2673 #ifndef CONFIG_SPI_FLASH_BAR 2674 /* enable 4-byte addressing if the device exceeds 16MiB */ 2675 nor->addr_width = 4; 2676 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || 2677 info->flags & SPI_NOR_4B_OPCODES) 2678 spi_nor_set_4byte_opcodes(nor, info); 2679 #else 2680 /* Configure the BAR - discover bank cmds and read current bank */ 2681 nor->addr_width = 3; 2682 ret = read_bar(nor, info); 2683 if (ret < 0) 2684 return ret; 2685 #endif 2686 } else { 2687 nor->addr_width = 3; 2688 } 2689 2690 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 2691 dev_dbg(dev, "address width is too large: %u\n", 2692 nor->addr_width); 2693 return -EINVAL; 2694 } 2695 2696 /* Send all the required SPI flash commands to initialize device */ 2697 nor->info = info; 2698 ret = spi_nor_init(nor); 2699 if (ret) 2700 return ret; 2701 2702 nor->name = mtd->name; 2703 nor->size = mtd->size; 2704 nor->erase_size = mtd->erasesize; 2705 nor->sector_size = mtd->erasesize; 2706 2707 #ifndef CONFIG_SPL_BUILD 2708 printf("SF: Detected %s with page size ", nor->name); 2709 print_size(nor->page_size, ", erase size "); 2710 print_size(nor->erase_size, ", total "); 2711 print_size(nor->size, ""); 2712 puts("\n"); 2713 #endif 2714 2715 return 0; 2716 } 2717 2718 /* U-Boot specific functions, need to extend MTD to support these */ 2719 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor) 2720 { 2721 int sr = read_sr(nor); 2722 2723 if (sr < 0) 2724 return sr; 2725 2726 return (sr >> 2) & 7; 2727 } 2728