1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 * 9 * Synced from Linux v4.19 10 */ 11 12 #include <common.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/log2.h> 16 #include <linux/math64.h> 17 #include <linux/sizes.h> 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/mtd/spi-nor.h> 21 #include <spi-mem.h> 22 #include <spi.h> 23 24 /* Define max times to check status register before we give up. */ 25 26 /* 27 * For everything but full-chip erase; probably could be much smaller, but kept 28 * around for safety for now 29 */ 30 31 #define HZ CONFIG_SYS_HZ 32 33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 34 35 #define SPI_NOR_MAX_ID_LEN 6 36 #define SPI_NOR_MAX_ADDR_WIDTH 4 37 38 struct flash_info { 39 char *name; 40 41 /* 42 * This array stores the ID bytes. 43 * The first three bytes are the JEDIC ID. 44 * JEDEC ID zero means "no ID" (mostly older chips). 45 */ 46 u8 id[SPI_NOR_MAX_ID_LEN]; 47 u8 id_len; 48 49 /* The size listed here is what works with SPINOR_OP_SE, which isn't 50 * necessarily called a "sector" by the vendor. 51 */ 52 unsigned int sector_size; 53 u16 n_sectors; 54 55 u16 page_size; 56 u16 addr_width; 57 58 u16 flags; 59 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ 60 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ 61 #define SST_WRITE BIT(2) /* use SST byte programming */ 62 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ 63 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ 64 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ 65 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ 66 #define USE_FSR BIT(7) /* use flag status register */ 67 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ 68 #define SPI_NOR_HAS_TB BIT(9) /* 69 * Flash SR has Top/Bottom (TB) protect 70 * bit. Must be used with 71 * SPI_NOR_HAS_LOCK. 72 */ 73 #define SPI_S3AN BIT(10) /* 74 * Xilinx Spartan 3AN In-System Flash 75 * (MFR cannot be used for probing 76 * because it has the same value as 77 * ATMEL flashes) 78 */ 79 #define SPI_NOR_4B_OPCODES BIT(11) /* 80 * Use dedicated 4byte address op codes 81 * to support memory size above 128Mib. 82 */ 83 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ 84 #define USE_CLSR BIT(14) /* use CLSR command */ 85 86 int (*quad_enable)(struct spi_nor *nor); 87 }; 88 89 #define JEDEC_MFR(info) ((info)->id[0]) 90 91 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) 92 { 93 return -EINVAL; 94 } 95 96 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) 97 { 98 return -EINVAL; 99 } 100 101 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, 102 u_char *buf) 103 { 104 return -EINVAL; 105 } 106 107 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 108 const u_char *buf) 109 { 110 return -EINVAL; 111 } 112 113 /* 114 * Read the status register, returning its value in the location 115 * Return the status register value. 116 * Returns negative if error occurred. 117 */ 118 static int read_sr(struct spi_nor *nor) 119 { 120 int ret; 121 u8 val; 122 123 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); 124 if (ret < 0) { 125 pr_debug("error %d reading SR\n", (int)ret); 126 return ret; 127 } 128 129 return val; 130 } 131 132 /* 133 * Read the flag status register, returning its value in the location 134 * Return the status register value. 135 * Returns negative if error occurred. 136 */ 137 static int read_fsr(struct spi_nor *nor) 138 { 139 int ret; 140 u8 val; 141 142 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); 143 if (ret < 0) { 144 pr_debug("error %d reading FSR\n", ret); 145 return ret; 146 } 147 148 return val; 149 } 150 151 /* 152 * Read configuration register, returning its value in the 153 * location. Return the configuration register value. 154 * Returns negative if error occurred. 155 */ 156 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 157 static int read_cr(struct spi_nor *nor) 158 { 159 int ret; 160 u8 val; 161 162 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); 163 if (ret < 0) { 164 dev_dbg(nor->dev, "error %d reading CR\n", ret); 165 return ret; 166 } 167 168 return val; 169 } 170 #endif 171 172 /* 173 * Write status register 1 byte 174 * Returns negative if error occurred. 175 */ 176 static int write_sr(struct spi_nor *nor, u8 val) 177 { 178 nor->cmd_buf[0] = val; 179 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); 180 } 181 182 /* 183 * Set write enable latch with Write Enable command. 184 * Returns negative if error occurred. 185 */ 186 static int write_enable(struct spi_nor *nor) 187 { 188 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); 189 } 190 191 /* 192 * Send write disable instruction to the chip. 193 */ 194 static int write_disable(struct spi_nor *nor) 195 { 196 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); 197 } 198 199 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) 200 { 201 return mtd->priv; 202 } 203 204 static int spi_nor_sr_ready(struct spi_nor *nor) 205 { 206 int sr = read_sr(nor); 207 208 if (sr < 0) 209 return sr; 210 211 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) { 212 if (sr & SR_E_ERR) 213 dev_dbg(nor->dev, "Erase Error occurred\n"); 214 else 215 dev_dbg(nor->dev, "Programming Error occurred\n"); 216 217 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0); 218 return -EIO; 219 } 220 221 return !(sr & SR_WIP); 222 } 223 224 static int spi_nor_fsr_ready(struct spi_nor *nor) 225 { 226 int fsr = read_fsr(nor); 227 228 if (fsr < 0) 229 return fsr; 230 231 if (fsr & (FSR_E_ERR | FSR_P_ERR)) { 232 if (fsr & FSR_E_ERR) 233 dev_dbg(nor->dev, "Erase operation failed.\n"); 234 else 235 dev_dbg(nor->dev, "Program operation failed.\n"); 236 237 if (fsr & FSR_PT_ERR) 238 dev_dbg(nor->dev, 239 "Attempted to modify a protected sector.\n"); 240 241 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0); 242 return -EIO; 243 } 244 245 return fsr & FSR_READY; 246 } 247 248 static int spi_nor_ready(struct spi_nor *nor) 249 { 250 int sr, fsr; 251 252 sr = spi_nor_sr_ready(nor); 253 if (sr < 0) 254 return sr; 255 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; 256 if (fsr < 0) 257 return fsr; 258 return sr && fsr; 259 } 260 261 /* 262 * Service routine to read status register until ready, or timeout occurs. 263 * Returns non-zero if error. 264 */ 265 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 266 unsigned long timeout) 267 { 268 unsigned long timebase; 269 int ret; 270 271 timebase = get_timer(0); 272 273 while (get_timer(timebase) < timeout) { 274 ret = spi_nor_ready(nor); 275 if (ret < 0) 276 return ret; 277 if (ret) 278 return 0; 279 } 280 281 dev_err(nor->dev, "flash operation timed out\n"); 282 283 return -ETIMEDOUT; 284 } 285 286 static int spi_nor_wait_till_ready(struct spi_nor *nor) 287 { 288 return spi_nor_wait_till_ready_with_timeout(nor, 289 DEFAULT_READY_WAIT_JIFFIES); 290 } 291 292 /* 293 * Initiate the erasure of a single sector 294 */ 295 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 296 { 297 u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; 298 int i; 299 300 if (nor->erase) 301 return nor->erase(nor, addr); 302 303 /* 304 * Default implementation, if driver doesn't have a specialized HW 305 * control 306 */ 307 for (i = nor->addr_width - 1; i >= 0; i--) { 308 buf[i] = addr & 0xff; 309 addr >>= 8; 310 } 311 312 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); 313 } 314 315 /* 316 * Erase an address range on the nor chip. The address range may extend 317 * one or more erase sectors. Return an error is there is a problem erasing. 318 */ 319 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 320 { 321 struct spi_nor *nor = mtd_to_spi_nor(mtd); 322 u32 addr, len, rem; 323 int ret; 324 325 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 326 (long long)instr->len); 327 328 div_u64_rem(instr->len, mtd->erasesize, &rem); 329 if (rem) 330 return -EINVAL; 331 332 addr = instr->addr; 333 len = instr->len; 334 335 while (len) { 336 write_enable(nor); 337 338 ret = spi_nor_erase_sector(nor, addr); 339 if (ret) 340 goto erase_err; 341 342 addr += mtd->erasesize; 343 len -= mtd->erasesize; 344 345 ret = spi_nor_wait_till_ready(nor); 346 if (ret) 347 goto erase_err; 348 } 349 350 write_disable(nor); 351 352 erase_err: 353 return ret; 354 } 355 356 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 357 /* Write status register and ensure bits in mask match written values */ 358 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) 359 { 360 int ret; 361 362 write_enable(nor); 363 ret = write_sr(nor, status_new); 364 if (ret) 365 return ret; 366 367 ret = spi_nor_wait_till_ready(nor); 368 if (ret) 369 return ret; 370 371 ret = read_sr(nor); 372 if (ret < 0) 373 return ret; 374 375 return ((ret & mask) != (status_new & mask)) ? -EIO : 0; 376 } 377 378 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, 379 uint64_t *len) 380 { 381 struct mtd_info *mtd = &nor->mtd; 382 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 383 int shift = ffs(mask) - 1; 384 int pow; 385 386 if (!(sr & mask)) { 387 /* No protection */ 388 *ofs = 0; 389 *len = 0; 390 } else { 391 pow = ((sr & mask) ^ mask) >> shift; 392 *len = mtd->size >> pow; 393 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) 394 *ofs = 0; 395 else 396 *ofs = mtd->size - *len; 397 } 398 } 399 400 /* 401 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if 402 * @locked is false); 0 otherwise 403 */ 404 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len, 405 u8 sr, bool locked) 406 { 407 loff_t lock_offs; 408 uint64_t lock_len; 409 410 if (!len) 411 return 1; 412 413 stm_get_locked_range(nor, sr, &lock_offs, &lock_len); 414 415 if (locked) 416 /* Requested range is a sub-range of locked range */ 417 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 418 else 419 /* Requested range does not overlap with locked range */ 420 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); 421 } 422 423 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 424 u8 sr) 425 { 426 return stm_check_lock_status_sr(nor, ofs, len, sr, true); 427 } 428 429 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 430 u8 sr) 431 { 432 return stm_check_lock_status_sr(nor, ofs, len, sr, false); 433 } 434 435 /* 436 * Lock a region of the flash. Compatible with ST Micro and similar flash. 437 * Supports the block protection bits BP{0,1,2} in the status register 438 * (SR). Does not support these features found in newer SR bitfields: 439 * - SEC: sector/block protect - only handle SEC=0 (block protect) 440 * - CMP: complement protect - only support CMP=0 (range is not complemented) 441 * 442 * Support for the following is provided conditionally for some flash: 443 * - TB: top/bottom protect 444 * 445 * Sample table portion for 8MB flash (Winbond w25q64fw): 446 * 447 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 448 * -------------------------------------------------------------------------- 449 * X | X | 0 | 0 | 0 | NONE | NONE 450 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 451 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 452 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 453 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 454 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 455 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 456 * X | X | 1 | 1 | 1 | 8 MB | ALL 457 * ------|-------|-------|-------|-------|---------------|------------------- 458 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 459 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 460 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 461 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 462 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 463 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 464 * 465 * Returns negative on errors, 0 on success. 466 */ 467 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 468 { 469 struct mtd_info *mtd = &nor->mtd; 470 int status_old, status_new; 471 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 472 u8 shift = ffs(mask) - 1, pow, val; 473 loff_t lock_len; 474 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 475 bool use_top; 476 477 status_old = read_sr(nor); 478 if (status_old < 0) 479 return status_old; 480 481 /* If nothing in our range is unlocked, we don't need to do anything */ 482 if (stm_is_locked_sr(nor, ofs, len, status_old)) 483 return 0; 484 485 /* If anything below us is unlocked, we can't use 'bottom' protection */ 486 if (!stm_is_locked_sr(nor, 0, ofs, status_old)) 487 can_be_bottom = false; 488 489 /* If anything above us is unlocked, we can't use 'top' protection */ 490 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), 491 status_old)) 492 can_be_top = false; 493 494 if (!can_be_bottom && !can_be_top) 495 return -EINVAL; 496 497 /* Prefer top, if both are valid */ 498 use_top = can_be_top; 499 500 /* lock_len: length of region that should end up locked */ 501 if (use_top) 502 lock_len = mtd->size - ofs; 503 else 504 lock_len = ofs + len; 505 506 /* 507 * Need smallest pow such that: 508 * 509 * 1 / (2^pow) <= (len / size) 510 * 511 * so (assuming power-of-2 size) we do: 512 * 513 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 514 */ 515 pow = ilog2(mtd->size) - ilog2(lock_len); 516 val = mask - (pow << shift); 517 if (val & ~mask) 518 return -EINVAL; 519 /* Don't "lock" with no region! */ 520 if (!(val & mask)) 521 return -EINVAL; 522 523 status_new = (status_old & ~mask & ~SR_TB) | val; 524 525 /* Disallow further writes if WP pin is asserted */ 526 status_new |= SR_SRWD; 527 528 if (!use_top) 529 status_new |= SR_TB; 530 531 /* Don't bother if they're the same */ 532 if (status_new == status_old) 533 return 0; 534 535 /* Only modify protection if it will not unlock other areas */ 536 if ((status_new & mask) < (status_old & mask)) 537 return -EINVAL; 538 539 return write_sr_and_check(nor, status_new, mask); 540 } 541 542 /* 543 * Unlock a region of the flash. See stm_lock() for more info 544 * 545 * Returns negative on errors, 0 on success. 546 */ 547 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 548 { 549 struct mtd_info *mtd = &nor->mtd; 550 int status_old, status_new; 551 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 552 u8 shift = ffs(mask) - 1, pow, val; 553 loff_t lock_len; 554 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 555 bool use_top; 556 557 status_old = read_sr(nor); 558 if (status_old < 0) 559 return status_old; 560 561 /* If nothing in our range is locked, we don't need to do anything */ 562 if (stm_is_unlocked_sr(nor, ofs, len, status_old)) 563 return 0; 564 565 /* If anything below us is locked, we can't use 'top' protection */ 566 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) 567 can_be_top = false; 568 569 /* If anything above us is locked, we can't use 'bottom' protection */ 570 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), 571 status_old)) 572 can_be_bottom = false; 573 574 if (!can_be_bottom && !can_be_top) 575 return -EINVAL; 576 577 /* Prefer top, if both are valid */ 578 use_top = can_be_top; 579 580 /* lock_len: length of region that should remain locked */ 581 if (use_top) 582 lock_len = mtd->size - (ofs + len); 583 else 584 lock_len = ofs; 585 586 /* 587 * Need largest pow such that: 588 * 589 * 1 / (2^pow) >= (len / size) 590 * 591 * so (assuming power-of-2 size) we do: 592 * 593 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 594 */ 595 pow = ilog2(mtd->size) - order_base_2(lock_len); 596 if (lock_len == 0) { 597 val = 0; /* fully unlocked */ 598 } else { 599 val = mask - (pow << shift); 600 /* Some power-of-two sizes are not supported */ 601 if (val & ~mask) 602 return -EINVAL; 603 } 604 605 status_new = (status_old & ~mask & ~SR_TB) | val; 606 607 /* Don't protect status register if we're fully unlocked */ 608 if (lock_len == 0) 609 status_new &= ~SR_SRWD; 610 611 if (!use_top) 612 status_new |= SR_TB; 613 614 /* Don't bother if they're the same */ 615 if (status_new == status_old) 616 return 0; 617 618 /* Only modify protection if it will not lock other areas */ 619 if ((status_new & mask) > (status_old & mask)) 620 return -EINVAL; 621 622 return write_sr_and_check(nor, status_new, mask); 623 } 624 625 /* 626 * Check if a region of the flash is (completely) locked. See stm_lock() for 627 * more info. 628 * 629 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 630 * negative on errors. 631 */ 632 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 633 { 634 int status; 635 636 status = read_sr(nor); 637 if (status < 0) 638 return status; 639 640 return stm_is_locked_sr(nor, ofs, len, status); 641 } 642 #endif /* CONFIG_SPI_FLASH_STMICRO */ 643 644 /* Used when the "_ext_id" is two bytes at most */ 645 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 646 .id = { \ 647 ((_jedec_id) >> 16) & 0xff, \ 648 ((_jedec_id) >> 8) & 0xff, \ 649 (_jedec_id) & 0xff, \ 650 ((_ext_id) >> 8) & 0xff, \ 651 (_ext_id) & 0xff, \ 652 }, \ 653 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 654 .sector_size = (_sector_size), \ 655 .n_sectors = (_n_sectors), \ 656 .page_size = 256, \ 657 .flags = (_flags), 658 659 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 660 .id = { \ 661 ((_jedec_id) >> 16) & 0xff, \ 662 ((_jedec_id) >> 8) & 0xff, \ 663 (_jedec_id) & 0xff, \ 664 ((_ext_id) >> 16) & 0xff, \ 665 ((_ext_id) >> 8) & 0xff, \ 666 (_ext_id) & 0xff, \ 667 }, \ 668 .id_len = 6, \ 669 .sector_size = (_sector_size), \ 670 .n_sectors = (_n_sectors), \ 671 .page_size = 256, \ 672 .flags = (_flags), 673 674 /* NOTE: double check command sets and memory organization when you add 675 * more nor chips. This current list focusses on newer chips, which 676 * have been converging on command sets which including JEDEC ID. 677 * 678 * All newly added entries should describe *hardware* and should use SECT_4K 679 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage 680 * scenarios excluding small sectors there is config option that can be 681 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. 682 * For historical (and compatibility) reasons (before we got above config) some 683 * old entries may be missing 4K flag. 684 */ 685 const struct flash_info spi_nor_ids[] = { 686 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ 687 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 688 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 689 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 690 691 { "at45db011d", INFO(0x1f2200, 0, 64 * 1024, 4, SECT_4K) }, 692 { "at45db021d", INFO(0x1f2300, 0, 64 * 1024, 8, SECT_4K) }, 693 { "at45db041d", INFO(0x1f2400, 0, 64 * 1024, 8, SECT_4K) }, 694 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 695 { "at45db161d", INFO(0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, 696 { "at45db321d", INFO(0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, 697 { "at45db641d", INFO(0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, 698 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 699 #endif 700 #ifdef CONFIG_SPI_FLASH_EON /* EON */ 701 /* EON -- en25xxx */ 702 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, 703 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 704 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, 705 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, 706 #endif 707 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ 708 /* GigaDevice */ 709 { 710 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32, 711 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 712 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 713 }, 714 { 715 "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, 716 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 717 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 718 }, 719 { 720 "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64, 721 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 722 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 723 }, 724 { 725 "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, 726 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 727 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 728 }, 729 #endif 730 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ 731 /* ISSI */ 732 { "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8, 733 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 734 { "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64, 0) }, 735 { "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128, 0) }, 736 { "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256, 737 SECT_4K | SPI_NOR_DUAL_READ) }, 738 { "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512, 739 SECT_4K | SPI_NOR_DUAL_READ) }, 740 { "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64, 741 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 742 { "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128, 743 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 744 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256, 745 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 746 #endif 747 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ 748 /* Macronix */ 749 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 750 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 751 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, 752 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 753 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) }, 754 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) }, 755 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) }, 756 { "mx25u1635e", INFO(0xc22535, 0, 64 * 1024, 32, SECT_4K) }, 757 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 758 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, 759 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, 760 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 761 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, 762 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, 763 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 764 { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 765 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 766 { "mx25l1633e", INFO(0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, 767 #endif 768 769 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 770 /* Micron */ 771 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, 772 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 773 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 774 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 775 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 776 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 777 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 778 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 779 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, 780 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 781 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 782 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 783 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 784 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 785 #endif 786 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ 787 /* Spansion/Cypress -- single (large) sector size only, at least 788 * for the chips listed here (without boot sectors). 789 */ 790 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 791 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 792 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) }, 793 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 794 { "s25fl512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 795 { "s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 796 { "s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 797 { "s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 798 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, 799 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, 800 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 801 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 802 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 803 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, 804 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, 805 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, 806 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, 807 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 808 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, 809 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, 810 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 811 #endif 812 #ifdef CONFIG_SPI_FLASH_SST /* SST */ 813 /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 814 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 815 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 816 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, 817 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, 818 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, 819 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, 820 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, 821 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, 822 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, 823 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, 824 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 825 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 826 { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 827 { "sst26wf016", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K) }, 828 { "sst26wf032", INFO(0xbf2622, 0, 64 * 1024, 64, SECT_4K) }, 829 { "sst26wf064", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K) }, 830 #endif 831 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 832 /* ST Microelectronics -- newer production may have feature updates */ 833 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, 834 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, 835 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, 836 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, 837 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, 838 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, 839 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, 840 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, 841 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, 842 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 843 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, 844 #endif 845 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ 846 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 847 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 848 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, 849 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, 850 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 851 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, 852 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 853 { 854 "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32, 855 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 856 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 857 }, 858 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 859 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 860 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 861 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 862 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, 863 { 864 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, 865 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 866 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 867 }, 868 { 869 "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64, 870 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 871 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 872 }, 873 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 874 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, 875 { 876 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, 877 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 878 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 879 }, 880 { 881 "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, 882 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 883 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 884 }, 885 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 886 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, 887 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, 888 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 889 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, 890 SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, 891 #endif 892 #ifdef CONFIG_SPI_FLASH_XMC 893 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 894 { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 895 { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 896 #endif 897 { }, 898 }; 899 900 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 901 { 902 int tmp; 903 u8 id[SPI_NOR_MAX_ID_LEN]; 904 const struct flash_info *info; 905 906 if (!ARRAY_SIZE(spi_nor_ids)) 907 return ERR_PTR(-ENODEV); 908 909 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); 910 if (tmp < 0) { 911 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); 912 return ERR_PTR(tmp); 913 } 914 915 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { 916 info = &spi_nor_ids[tmp]; 917 if (info->id_len) { 918 if (!memcmp(info->id, id, info->id_len)) 919 return &spi_nor_ids[tmp]; 920 } 921 } 922 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", 923 id[0], id[1], id[2]); 924 return ERR_PTR(-ENODEV); 925 } 926 927 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 928 size_t *retlen, u_char *buf) 929 { 930 struct spi_nor *nor = mtd_to_spi_nor(mtd); 931 int ret; 932 933 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 934 935 while (len) { 936 loff_t addr = from; 937 938 ret = nor->read(nor, addr, len, buf); 939 if (ret == 0) { 940 /* We shouldn't see 0-length reads */ 941 ret = -EIO; 942 goto read_err; 943 } 944 if (ret < 0) 945 goto read_err; 946 947 *retlen += ret; 948 buf += ret; 949 from += ret; 950 len -= ret; 951 } 952 ret = 0; 953 954 read_err: 955 return ret; 956 } 957 958 #ifdef CONFIG_SPI_FLASH_SST 959 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, 960 size_t *retlen, const u_char *buf) 961 { 962 struct spi_nor *nor = mtd_to_spi_nor(mtd); 963 size_t actual; 964 int ret; 965 966 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 967 968 write_enable(nor); 969 970 nor->sst_write_second = false; 971 972 actual = to % 2; 973 /* Start write from odd address. */ 974 if (actual) { 975 nor->program_opcode = SPINOR_OP_BP; 976 977 /* write one byte. */ 978 ret = nor->write(nor, to, 1, buf); 979 if (ret < 0) 980 goto sst_write_err; 981 ret = spi_nor_wait_till_ready(nor); 982 if (ret) 983 goto sst_write_err; 984 } 985 to += actual; 986 987 /* Write out most of the data here. */ 988 for (; actual < len - 1; actual += 2) { 989 nor->program_opcode = SPINOR_OP_AAI_WP; 990 991 /* write two bytes. */ 992 ret = nor->write(nor, to, 2, buf + actual); 993 if (ret < 0) 994 goto sst_write_err; 995 ret = spi_nor_wait_till_ready(nor); 996 if (ret) 997 goto sst_write_err; 998 to += 2; 999 nor->sst_write_second = true; 1000 } 1001 nor->sst_write_second = false; 1002 1003 write_disable(nor); 1004 ret = spi_nor_wait_till_ready(nor); 1005 if (ret) 1006 goto sst_write_err; 1007 1008 /* Write out trailing byte if it exists. */ 1009 if (actual != len) { 1010 write_enable(nor); 1011 1012 nor->program_opcode = SPINOR_OP_BP; 1013 ret = nor->write(nor, to, 1, buf + actual); 1014 if (ret < 0) 1015 goto sst_write_err; 1016 ret = spi_nor_wait_till_ready(nor); 1017 if (ret) 1018 goto sst_write_err; 1019 write_disable(nor); 1020 actual += 1; 1021 } 1022 sst_write_err: 1023 *retlen += actual; 1024 return ret; 1025 } 1026 #endif 1027 /* 1028 * Write an address range to the nor chip. Data must be written in 1029 * FLASH_PAGESIZE chunks. The address range may be any size provided 1030 * it is within the physical boundaries. 1031 */ 1032 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 1033 size_t *retlen, const u_char *buf) 1034 { 1035 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1036 size_t page_offset, page_remain, i; 1037 ssize_t ret; 1038 1039 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 1040 1041 for (i = 0; i < len; ) { 1042 ssize_t written; 1043 loff_t addr = to + i; 1044 1045 /* 1046 * If page_size is a power of two, the offset can be quickly 1047 * calculated with an AND operation. On the other cases we 1048 * need to do a modulus operation (more expensive). 1049 * Power of two numbers have only one bit set and we can use 1050 * the instruction hweight32 to detect if we need to do a 1051 * modulus (do_div()) or not. 1052 */ 1053 if (hweight32(nor->page_size) == 1) { 1054 page_offset = addr & (nor->page_size - 1); 1055 } else { 1056 u64 aux = addr; 1057 1058 page_offset = do_div(aux, nor->page_size); 1059 } 1060 /* the size of data remaining on the first page */ 1061 page_remain = min_t(size_t, 1062 nor->page_size - page_offset, len - i); 1063 1064 write_enable(nor); 1065 ret = nor->write(nor, addr, page_remain, buf + i); 1066 if (ret < 0) 1067 goto write_err; 1068 written = ret; 1069 1070 ret = spi_nor_wait_till_ready(nor); 1071 if (ret) 1072 goto write_err; 1073 *retlen += written; 1074 i += written; 1075 if (written != page_remain) { 1076 ret = -EIO; 1077 goto write_err; 1078 } 1079 } 1080 1081 write_err: 1082 return ret; 1083 } 1084 1085 #ifdef CONFIG_SPI_FLASH_MACRONIX 1086 /** 1087 * macronix_quad_enable() - set QE bit in Status Register. 1088 * @nor: pointer to a 'struct spi_nor' 1089 * 1090 * Set the Quad Enable (QE) bit in the Status Register. 1091 * 1092 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. 1093 * 1094 * Return: 0 on success, -errno otherwise. 1095 */ 1096 static int macronix_quad_enable(struct spi_nor *nor) 1097 { 1098 int ret, val; 1099 1100 val = read_sr(nor); 1101 if (val < 0) 1102 return val; 1103 if (val & SR_QUAD_EN_MX) 1104 return 0; 1105 1106 write_enable(nor); 1107 1108 write_sr(nor, val | SR_QUAD_EN_MX); 1109 1110 ret = spi_nor_wait_till_ready(nor); 1111 if (ret) 1112 return ret; 1113 1114 ret = read_sr(nor); 1115 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { 1116 dev_err(nor->dev, "Macronix Quad bit not set\n"); 1117 return -EINVAL; 1118 } 1119 1120 return 0; 1121 } 1122 #endif 1123 1124 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1125 /* 1126 * Write status Register and configuration register with 2 bytes 1127 * The first byte will be written to the status register, while the 1128 * second byte will be written to the configuration register. 1129 * Return negative if error occurred. 1130 */ 1131 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) 1132 { 1133 int ret; 1134 1135 write_enable(nor); 1136 1137 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2); 1138 if (ret < 0) { 1139 dev_dbg(nor->dev, 1140 "error while writing configuration register\n"); 1141 return -EINVAL; 1142 } 1143 1144 ret = spi_nor_wait_till_ready(nor); 1145 if (ret) { 1146 dev_dbg(nor->dev, 1147 "timeout while writing configuration register\n"); 1148 return ret; 1149 } 1150 1151 return 0; 1152 } 1153 1154 /** 1155 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. 1156 * @nor: pointer to a 'struct spi_nor' 1157 * 1158 * Set the Quad Enable (QE) bit in the Configuration Register. 1159 * This function should be used with QSPI memories supporting the Read 1160 * Configuration Register (35h) instruction. 1161 * 1162 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1163 * memories. 1164 * 1165 * Return: 0 on success, -errno otherwise. 1166 */ 1167 static int spansion_read_cr_quad_enable(struct spi_nor *nor) 1168 { 1169 u8 sr_cr[2]; 1170 int ret; 1171 1172 /* Check current Quad Enable bit value. */ 1173 ret = read_cr(nor); 1174 if (ret < 0) { 1175 dev_dbg(dev, "error while reading configuration register\n"); 1176 return -EINVAL; 1177 } 1178 1179 if (ret & CR_QUAD_EN_SPAN) 1180 return 0; 1181 1182 sr_cr[1] = ret | CR_QUAD_EN_SPAN; 1183 1184 /* Keep the current value of the Status Register. */ 1185 ret = read_sr(nor); 1186 if (ret < 0) { 1187 dev_dbg(dev, "error while reading status register\n"); 1188 return -EINVAL; 1189 } 1190 sr_cr[0] = ret; 1191 1192 ret = write_sr_cr(nor, sr_cr); 1193 if (ret) 1194 return ret; 1195 1196 /* Read back and check it. */ 1197 ret = read_cr(nor); 1198 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { 1199 dev_dbg(nor->dev, "Spansion Quad bit not set\n"); 1200 return -EINVAL; 1201 } 1202 1203 return 0; 1204 } 1205 #endif /* CONFIG_SPI_FLASH_SPANSION */ 1206 1207 struct spi_nor_read_command { 1208 u8 num_mode_clocks; 1209 u8 num_wait_states; 1210 u8 opcode; 1211 enum spi_nor_protocol proto; 1212 }; 1213 1214 struct spi_nor_pp_command { 1215 u8 opcode; 1216 enum spi_nor_protocol proto; 1217 }; 1218 1219 enum spi_nor_read_command_index { 1220 SNOR_CMD_READ, 1221 SNOR_CMD_READ_FAST, 1222 SNOR_CMD_READ_1_1_1_DTR, 1223 1224 /* Dual SPI */ 1225 SNOR_CMD_READ_1_1_2, 1226 SNOR_CMD_READ_1_2_2, 1227 SNOR_CMD_READ_2_2_2, 1228 SNOR_CMD_READ_1_2_2_DTR, 1229 1230 /* Quad SPI */ 1231 SNOR_CMD_READ_1_1_4, 1232 SNOR_CMD_READ_1_4_4, 1233 SNOR_CMD_READ_4_4_4, 1234 SNOR_CMD_READ_1_4_4_DTR, 1235 1236 /* Octo SPI */ 1237 SNOR_CMD_READ_1_1_8, 1238 SNOR_CMD_READ_1_8_8, 1239 SNOR_CMD_READ_8_8_8, 1240 SNOR_CMD_READ_1_8_8_DTR, 1241 1242 SNOR_CMD_READ_MAX 1243 }; 1244 1245 enum spi_nor_pp_command_index { 1246 SNOR_CMD_PP, 1247 1248 /* Quad SPI */ 1249 SNOR_CMD_PP_1_1_4, 1250 SNOR_CMD_PP_1_4_4, 1251 SNOR_CMD_PP_4_4_4, 1252 1253 /* Octo SPI */ 1254 SNOR_CMD_PP_1_1_8, 1255 SNOR_CMD_PP_1_8_8, 1256 SNOR_CMD_PP_8_8_8, 1257 1258 SNOR_CMD_PP_MAX 1259 }; 1260 1261 struct spi_nor_flash_parameter { 1262 u64 size; 1263 u32 page_size; 1264 1265 struct spi_nor_hwcaps hwcaps; 1266 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; 1267 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; 1268 1269 int (*quad_enable)(struct spi_nor *nor); 1270 }; 1271 1272 static void 1273 spi_nor_set_read_settings(struct spi_nor_read_command *read, 1274 u8 num_mode_clocks, 1275 u8 num_wait_states, 1276 u8 opcode, 1277 enum spi_nor_protocol proto) 1278 { 1279 read->num_mode_clocks = num_mode_clocks; 1280 read->num_wait_states = num_wait_states; 1281 read->opcode = opcode; 1282 read->proto = proto; 1283 } 1284 1285 static void 1286 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, 1287 u8 opcode, 1288 enum spi_nor_protocol proto) 1289 { 1290 pp->opcode = opcode; 1291 pp->proto = proto; 1292 } 1293 1294 static int spi_nor_init_params(struct spi_nor *nor, 1295 const struct flash_info *info, 1296 struct spi_nor_flash_parameter *params) 1297 { 1298 /* Set legacy flash parameters as default. */ 1299 memset(params, 0, sizeof(*params)); 1300 1301 /* Set SPI NOR sizes. */ 1302 params->size = info->sector_size * info->n_sectors; 1303 params->page_size = info->page_size; 1304 1305 /* (Fast) Read settings. */ 1306 params->hwcaps.mask |= SNOR_HWCAPS_READ; 1307 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 1308 0, 0, SPINOR_OP_READ, 1309 SNOR_PROTO_1_1_1); 1310 1311 if (!(info->flags & SPI_NOR_NO_FR)) { 1312 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 1313 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 1314 0, 8, SPINOR_OP_READ_FAST, 1315 SNOR_PROTO_1_1_1); 1316 } 1317 1318 if (info->flags & SPI_NOR_DUAL_READ) { 1319 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 1320 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 1321 0, 8, SPINOR_OP_READ_1_1_2, 1322 SNOR_PROTO_1_1_2); 1323 } 1324 1325 if (info->flags & SPI_NOR_QUAD_READ) { 1326 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 1327 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 1328 0, 8, SPINOR_OP_READ_1_1_4, 1329 SNOR_PROTO_1_1_4); 1330 } 1331 1332 /* Page Program settings. */ 1333 params->hwcaps.mask |= SNOR_HWCAPS_PP; 1334 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 1335 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 1336 1337 if (info->flags & SPI_NOR_QUAD_READ) { 1338 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; 1339 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], 1340 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4); 1341 } 1342 1343 /* Select the procedure to set the Quad Enable bit. */ 1344 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD | 1345 SNOR_HWCAPS_PP_QUAD)) { 1346 switch (JEDEC_MFR(info)) { 1347 #ifdef CONFIG_SPI_FLASH_MACRONIX 1348 case SNOR_MFR_MACRONIX: 1349 params->quad_enable = macronix_quad_enable; 1350 break; 1351 #endif 1352 case SNOR_MFR_ST: 1353 case SNOR_MFR_MICRON: 1354 break; 1355 1356 default: 1357 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1358 /* Kept only for backward compatibility purpose. */ 1359 params->quad_enable = spansion_read_cr_quad_enable; 1360 #endif 1361 break; 1362 } 1363 } 1364 } 1365 1366 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 1367 { 1368 size_t i; 1369 1370 for (i = 0; i < size; i++) 1371 if (table[i][0] == (int)hwcaps) 1372 return table[i][1]; 1373 1374 return -EINVAL; 1375 } 1376 1377 static int spi_nor_hwcaps_read2cmd(u32 hwcaps) 1378 { 1379 static const int hwcaps_read2cmd[][2] = { 1380 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 1381 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 1382 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 1383 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 1384 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 1385 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 1386 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 1387 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 1388 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 1389 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 1390 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 1391 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 1392 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 1393 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 1394 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 1395 }; 1396 1397 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 1398 ARRAY_SIZE(hwcaps_read2cmd)); 1399 } 1400 1401 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 1402 { 1403 static const int hwcaps_pp2cmd[][2] = { 1404 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 1405 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 1406 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 1407 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 1408 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 1409 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 1410 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 1411 }; 1412 1413 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 1414 ARRAY_SIZE(hwcaps_pp2cmd)); 1415 } 1416 1417 static int spi_nor_select_read(struct spi_nor *nor, 1418 const struct spi_nor_flash_parameter *params, 1419 u32 shared_hwcaps) 1420 { 1421 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 1422 const struct spi_nor_read_command *read; 1423 1424 if (best_match < 0) 1425 return -EINVAL; 1426 1427 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 1428 if (cmd < 0) 1429 return -EINVAL; 1430 1431 read = ¶ms->reads[cmd]; 1432 nor->read_opcode = read->opcode; 1433 nor->read_proto = read->proto; 1434 1435 /* 1436 * In the spi-nor framework, we don't need to make the difference 1437 * between mode clock cycles and wait state clock cycles. 1438 * Indeed, the value of the mode clock cycles is used by a QSPI 1439 * flash memory to know whether it should enter or leave its 0-4-4 1440 * (Continuous Read / XIP) mode. 1441 * eXecution In Place is out of the scope of the mtd sub-system. 1442 * Hence we choose to merge both mode and wait state clock cycles 1443 * into the so called dummy clock cycles. 1444 */ 1445 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 1446 return 0; 1447 } 1448 1449 static int spi_nor_select_pp(struct spi_nor *nor, 1450 const struct spi_nor_flash_parameter *params, 1451 u32 shared_hwcaps) 1452 { 1453 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 1454 const struct spi_nor_pp_command *pp; 1455 1456 if (best_match < 0) 1457 return -EINVAL; 1458 1459 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 1460 if (cmd < 0) 1461 return -EINVAL; 1462 1463 pp = ¶ms->page_programs[cmd]; 1464 nor->program_opcode = pp->opcode; 1465 nor->write_proto = pp->proto; 1466 return 0; 1467 } 1468 1469 static int spi_nor_select_erase(struct spi_nor *nor, 1470 const struct flash_info *info) 1471 { 1472 struct mtd_info *mtd = &nor->mtd; 1473 1474 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 1475 /* prefer "small sector" erase if possible */ 1476 if (info->flags & SECT_4K) { 1477 nor->erase_opcode = SPINOR_OP_BE_4K; 1478 mtd->erasesize = 4096; 1479 } else if (info->flags & SECT_4K_PMC) { 1480 nor->erase_opcode = SPINOR_OP_BE_4K_PMC; 1481 mtd->erasesize = 4096; 1482 } else 1483 #endif 1484 { 1485 nor->erase_opcode = SPINOR_OP_SE; 1486 mtd->erasesize = info->sector_size; 1487 } 1488 return 0; 1489 } 1490 1491 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, 1492 const struct spi_nor_flash_parameter *params, 1493 const struct spi_nor_hwcaps *hwcaps) 1494 { 1495 u32 ignored_mask, shared_mask; 1496 bool enable_quad_io; 1497 int err; 1498 1499 /* 1500 * Keep only the hardware capabilities supported by both the SPI 1501 * controller and the SPI flash memory. 1502 */ 1503 shared_mask = hwcaps->mask & params->hwcaps.mask; 1504 1505 /* SPI n-n-n protocols are not supported yet. */ 1506 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 | 1507 SNOR_HWCAPS_READ_4_4_4 | 1508 SNOR_HWCAPS_READ_8_8_8 | 1509 SNOR_HWCAPS_PP_4_4_4 | 1510 SNOR_HWCAPS_PP_8_8_8); 1511 if (shared_mask & ignored_mask) { 1512 dev_dbg(nor->dev, 1513 "SPI n-n-n protocols are not supported yet.\n"); 1514 shared_mask &= ~ignored_mask; 1515 } 1516 1517 /* Select the (Fast) Read command. */ 1518 err = spi_nor_select_read(nor, params, shared_mask); 1519 if (err) { 1520 dev_dbg(nor->dev, 1521 "can't select read settings supported by both the SPI controller and memory.\n"); 1522 return err; 1523 } 1524 1525 /* Select the Page Program command. */ 1526 err = spi_nor_select_pp(nor, params, shared_mask); 1527 if (err) { 1528 dev_dbg(nor->dev, 1529 "can't select write settings supported by both the SPI controller and memory.\n"); 1530 return err; 1531 } 1532 1533 /* Select the Sector Erase command. */ 1534 err = spi_nor_select_erase(nor, info); 1535 if (err) { 1536 dev_dbg(nor->dev, 1537 "can't select erase settings supported by both the SPI controller and memory.\n"); 1538 return err; 1539 } 1540 1541 /* Enable Quad I/O if needed. */ 1542 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 || 1543 spi_nor_get_protocol_width(nor->write_proto) == 4); 1544 if (enable_quad_io && params->quad_enable) 1545 nor->quad_enable = params->quad_enable; 1546 else 1547 nor->quad_enable = NULL; 1548 1549 return 0; 1550 } 1551 1552 static int spi_nor_init(struct spi_nor *nor) 1553 { 1554 int err; 1555 1556 /* 1557 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up 1558 * with the software protection bits set 1559 */ 1560 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || 1561 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || 1562 JEDEC_MFR(nor->info) == SNOR_MFR_SST || 1563 nor->info->flags & SPI_NOR_HAS_LOCK) { 1564 write_enable(nor); 1565 write_sr(nor, 0); 1566 spi_nor_wait_till_ready(nor); 1567 } 1568 1569 if (nor->quad_enable) { 1570 err = nor->quad_enable(nor); 1571 if (err) { 1572 dev_dbg(nor->dev, "quad mode not supported\n"); 1573 return err; 1574 } 1575 } 1576 1577 return 0; 1578 } 1579 1580 int spi_nor_scan(struct spi_nor *nor) 1581 { 1582 struct spi_nor_flash_parameter params; 1583 const struct flash_info *info = NULL; 1584 struct mtd_info *mtd = &nor->mtd; 1585 struct spi_nor_hwcaps hwcaps = { 1586 .mask = SNOR_HWCAPS_READ | 1587 SNOR_HWCAPS_READ_FAST | 1588 SNOR_HWCAPS_PP, 1589 }; 1590 struct spi_slave *spi = nor->spi; 1591 int ret; 1592 1593 /* Reset SPI protocol for all commands. */ 1594 nor->reg_proto = SNOR_PROTO_1_1_1; 1595 nor->read_proto = SNOR_PROTO_1_1_1; 1596 nor->write_proto = SNOR_PROTO_1_1_1; 1597 nor->read = spi_nor_read_data; 1598 nor->write = spi_nor_write_data; 1599 nor->read_reg = spi_nor_read_reg; 1600 nor->write_reg = spi_nor_write_reg; 1601 1602 if (spi->mode & SPI_RX_QUAD) { 1603 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 1604 1605 if (spi->mode & SPI_TX_QUAD) 1606 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 | 1607 SNOR_HWCAPS_PP_1_1_4 | 1608 SNOR_HWCAPS_PP_1_4_4); 1609 } else if (spi->mode & SPI_RX_DUAL) { 1610 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 1611 1612 if (spi->mode & SPI_TX_DUAL) 1613 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2; 1614 } 1615 1616 info = spi_nor_read_id(nor); 1617 if (IS_ERR_OR_NULL(info)) 1618 return -ENOENT; 1619 1620 ret = spi_nor_init_params(nor, info, ¶ms); 1621 if (ret) 1622 return ret; 1623 1624 if (!mtd->name) 1625 mtd->name = info->name; 1626 mtd->priv = nor; 1627 mtd->type = MTD_NORFLASH; 1628 mtd->writesize = 1; 1629 mtd->flags = MTD_CAP_NORFLASH; 1630 mtd->size = params.size; 1631 mtd->_erase = spi_nor_erase; 1632 mtd->_read = spi_nor_read; 1633 1634 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 1635 /* NOR protection support for STmicro/Micron chips and similar */ 1636 if (JEDEC_MFR(info) == SNOR_MFR_ST || 1637 JEDEC_MFR(info) == SNOR_MFR_MICRON || 1638 JEDEC_MFR(info) == SNOR_MFR_SST || 1639 info->flags & SPI_NOR_HAS_LOCK) { 1640 nor->flash_lock = stm_lock; 1641 nor->flash_unlock = stm_unlock; 1642 nor->flash_is_locked = stm_is_locked; 1643 } 1644 #endif 1645 1646 #ifdef CONFIG_SPI_FLASH_SST 1647 /* sst nor chips use AAI word program */ 1648 if (info->flags & SST_WRITE) 1649 mtd->_write = sst_write; 1650 else 1651 #endif 1652 mtd->_write = spi_nor_write; 1653 1654 if (info->flags & USE_FSR) 1655 nor->flags |= SNOR_F_USE_FSR; 1656 if (info->flags & SPI_NOR_HAS_TB) 1657 nor->flags |= SNOR_F_HAS_SR_TB; 1658 if (info->flags & NO_CHIP_ERASE) 1659 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 1660 if (info->flags & USE_CLSR) 1661 nor->flags |= SNOR_F_USE_CLSR; 1662 1663 if (info->flags & SPI_NOR_NO_ERASE) 1664 mtd->flags |= MTD_NO_ERASE; 1665 1666 nor->page_size = params.page_size; 1667 mtd->writebufsize = nor->page_size; 1668 1669 /* Some devices cannot do fast-read, no matter what DT tells us */ 1670 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW)) 1671 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 1672 1673 /* 1674 * Configure the SPI memory: 1675 * - select op codes for (Fast) Read, Page Program and Sector Erase. 1676 * - set the number of dummy cycles (mode cycles + wait states). 1677 * - set the SPI protocols for register and memory accesses. 1678 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos). 1679 */ 1680 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps); 1681 if (ret) 1682 return ret; 1683 1684 if (info->addr_width) { 1685 nor->addr_width = info->addr_width; 1686 } else { 1687 nor->addr_width = 3; 1688 } 1689 1690 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 1691 dev_dbg(dev, "address width is too large: %u\n", 1692 nor->addr_width); 1693 return -EINVAL; 1694 } 1695 1696 /* Send all the required SPI flash commands to initialize device */ 1697 nor->info = info; 1698 ret = spi_nor_init(nor); 1699 if (ret) 1700 return ret; 1701 1702 nor->name = mtd->name; 1703 nor->size = mtd->size; 1704 nor->erase_size = mtd->erasesize; 1705 nor->sector_size = mtd->erasesize; 1706 1707 #ifndef CONFIG_SPL_BUILD 1708 printf("SF: Detected %s with page size ", nor->name); 1709 print_size(nor->page_size, ", erase size "); 1710 print_size(nor->erase_size, ", total "); 1711 print_size(nor->size, ""); 1712 puts("\n"); 1713 #endif 1714 1715 return 0; 1716 } 1717