| c1bad47f | 14-Apr-2020 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rv1126: Change APLL rate to 1008MHz
APLL from 600MHz to 1008MHz, increase cpu frequency.
Change-Id: If24475ff07f99c639a208cbfa23395544da4b6e8 Signed-off-by: Finley Xiao <finley.xiao@
clk: rockchip: rv1126: Change APLL rate to 1008MHz
APLL from 600MHz to 1008MHz, increase cpu frequency.
Change-Id: If24475ff07f99c639a208cbfa23395544da4b6e8 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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| 322971a6 | 14-Apr-2020 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rv1126: Change cpll and hpll rate
CPLL from 1000MHz to 500MHz, make clk_gmac_ethernet_out2io 25MHz comes from CPLL. HPLL form 1600MHz to 1400MHz, make npu 700MHz comes from HPLL.
Cha
clk: rockchip: rv1126: Change cpll and hpll rate
CPLL from 1000MHz to 500MHz, make clk_gmac_ethernet_out2io 25MHz comes from CPLL. HPLL form 1600MHz to 1400MHz, make npu 700MHz comes from HPLL.
Change-Id: I6633a83536054402ea8a9dc38abb33fe33503595 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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