1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 #include <asm/arch/cpu.h> 14 15 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 16 #define RK_FUNC_GPIO 0 17 #define MAX_ROCKCHIP_PINS_ENTRIES 30 18 19 enum rockchip_pinctrl_type { 20 PX30, 21 RV1108, 22 RV1126, 23 RK1808, 24 RK2928, 25 RK3066B, 26 RK3128, 27 RK3188, 28 RK3288, 29 RK3308, 30 RK3368, 31 RK3399, 32 }; 33 34 /** 35 * Encode variants of iomux registers into a type variable 36 */ 37 #define IOMUX_GPIO_ONLY BIT(0) 38 #define IOMUX_WIDTH_4BIT BIT(1) 39 #define IOMUX_SOURCE_PMU BIT(2) 40 #define IOMUX_UNROUTED BIT(3) 41 #define IOMUX_WIDTH_3BIT BIT(4) 42 #define IOMUX_8WIDTH_2BIT BIT(5) 43 #define IOMUX_WRITABLE_32BIT BIT(6) 44 #define IOMUX_L_SOURCE_PMU BIT(7) 45 46 /** 47 * @type: iomux variant using IOMUX_* constants 48 * @offset: if initialized to -1 it will be autocalculated, by specifying 49 * an initial offset value the relevant source offset can be reset 50 * to a new value for autocalculating the following iomux registers. 51 */ 52 struct rockchip_iomux { 53 int type; 54 int offset; 55 }; 56 57 #define DRV_TYPE_IO_MASK GENMASK(31, 16) 58 #define DRV_TYPE_WRITABLE_32BIT BIT(31) 59 60 /** 61 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 62 */ 63 enum rockchip_pin_drv_type { 64 DRV_TYPE_IO_DEFAULT = 0, 65 DRV_TYPE_IO_1V8_OR_3V0, 66 DRV_TYPE_IO_1V8_ONLY, 67 DRV_TYPE_IO_1V8_3V0_AUTO, 68 DRV_TYPE_IO_3V3_ONLY, 69 DRV_TYPE_MAX 70 }; 71 72 #define PULL_TYPE_IO_MASK GENMASK(31, 16) 73 #define PULL_TYPE_WRITABLE_32BIT BIT(31) 74 75 /** 76 * enum type index corresponding to rockchip_pull_list arrays index. 77 */ 78 enum rockchip_pin_pull_type { 79 PULL_TYPE_IO_DEFAULT = 0, 80 PULL_TYPE_IO_1V8_ONLY, 81 PULL_TYPE_MAX 82 }; 83 84 /** 85 * @drv_type: drive strength variant using rockchip_perpin_drv_type 86 * @offset: if initialized to -1 it will be autocalculated, by specifying 87 * an initial offset value the relevant source offset can be reset 88 * to a new value for autocalculating the following drive strength 89 * registers. if used chips own cal_drv func instead to calculate 90 * registers offset, the variant could be ignored. 91 */ 92 struct rockchip_drv { 93 enum rockchip_pin_drv_type drv_type; 94 int offset; 95 }; 96 97 /** 98 * @priv: common pinctrl private basedata 99 * @pin_base: first pin number 100 * @nr_pins: number of pins in this bank 101 * @name: name of the bank 102 * @bank_num: number of the bank, to account for holes 103 * @iomux: array describing the 4 iomux sources of the bank 104 * @drv: array describing the 4 drive strength sources of the bank 105 * @pull_type: array describing the 4 pull type sources of the bank 106 * @recalced_mask: bits describing the mux recalced pins of per bank 107 * @route_mask: bits describing the routing pins of per bank 108 */ 109 struct rockchip_pin_bank { 110 struct rockchip_pinctrl_priv *priv; 111 u32 pin_base; 112 u8 nr_pins; 113 char *name; 114 u8 bank_num; 115 struct rockchip_iomux iomux[4]; 116 struct rockchip_drv drv[4]; 117 enum rockchip_pin_pull_type pull_type[4]; 118 u32 recalced_mask; 119 u32 route_mask; 120 }; 121 122 #define PIN_BANK(id, pins, label) \ 123 { \ 124 .bank_num = id, \ 125 .nr_pins = pins, \ 126 .name = label, \ 127 .iomux = { \ 128 { .offset = -1 }, \ 129 { .offset = -1 }, \ 130 { .offset = -1 }, \ 131 { .offset = -1 }, \ 132 }, \ 133 } 134 135 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 136 { \ 137 .bank_num = id, \ 138 .nr_pins = pins, \ 139 .name = label, \ 140 .iomux = { \ 141 { .type = iom0, .offset = -1 }, \ 142 { .type = iom1, .offset = -1 }, \ 143 { .type = iom2, .offset = -1 }, \ 144 { .type = iom3, .offset = -1 }, \ 145 }, \ 146 } 147 148 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 149 { \ 150 .bank_num = id, \ 151 .nr_pins = pins, \ 152 .name = label, \ 153 .iomux = { \ 154 { .offset = -1 }, \ 155 { .offset = -1 }, \ 156 { .offset = -1 }, \ 157 { .offset = -1 }, \ 158 }, \ 159 .drv = { \ 160 { .drv_type = type0, .offset = -1 }, \ 161 { .drv_type = type1, .offset = -1 }, \ 162 { .drv_type = type2, .offset = -1 }, \ 163 { .drv_type = type3, .offset = -1 }, \ 164 }, \ 165 } 166 167 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 168 drv2, drv3, pull0, pull1, \ 169 pull2, pull3) \ 170 { \ 171 .bank_num = id, \ 172 .nr_pins = pins, \ 173 .name = label, \ 174 .iomux = { \ 175 { .offset = -1 }, \ 176 { .offset = -1 }, \ 177 { .offset = -1 }, \ 178 { .offset = -1 }, \ 179 }, \ 180 .drv = { \ 181 { .drv_type = drv0, .offset = -1 }, \ 182 { .drv_type = drv1, .offset = -1 }, \ 183 { .drv_type = drv2, .offset = -1 }, \ 184 { .drv_type = drv3, .offset = -1 }, \ 185 }, \ 186 .pull_type[0] = pull0, \ 187 .pull_type[1] = pull1, \ 188 .pull_type[2] = pull2, \ 189 .pull_type[3] = pull3, \ 190 } 191 192 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 193 iom2, iom3, drv0, drv1, drv2, \ 194 drv3, offset0, offset1, \ 195 offset2, offset3) \ 196 { \ 197 .bank_num = id, \ 198 .nr_pins = pins, \ 199 .name = label, \ 200 .iomux = { \ 201 { .type = iom0, .offset = -1 }, \ 202 { .type = iom1, .offset = -1 }, \ 203 { .type = iom2, .offset = -1 }, \ 204 { .type = iom3, .offset = -1 }, \ 205 }, \ 206 .drv = { \ 207 { .drv_type = drv0, .offset = offset0 }, \ 208 { .drv_type = drv1, .offset = offset1 }, \ 209 { .drv_type = drv2, .offset = offset2 }, \ 210 { .drv_type = drv3, .offset = offset3 }, \ 211 }, \ 212 } 213 214 #define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ 215 iom2, iom3, drv0, drv1, drv2, \ 216 drv3, pull0, pull1, pull2, \ 217 pull3) \ 218 { \ 219 .bank_num = id, \ 220 .nr_pins = pins, \ 221 .name = label, \ 222 .iomux = { \ 223 { .type = iom0, .offset = -1 }, \ 224 { .type = iom1, .offset = -1 }, \ 225 { .type = iom2, .offset = -1 }, \ 226 { .type = iom3, .offset = -1 }, \ 227 }, \ 228 .drv = { \ 229 { .drv_type = drv0, .offset = -1 }, \ 230 { .drv_type = drv1, .offset = -1 }, \ 231 { .drv_type = drv2, .offset = -1 }, \ 232 { .drv_type = drv3, .offset = -1 }, \ 233 }, \ 234 .pull_type[0] = pull0, \ 235 .pull_type[1] = pull1, \ 236 .pull_type[2] = pull2, \ 237 .pull_type[3] = pull3, \ 238 } 239 240 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 241 label, iom0, iom1, iom2, \ 242 iom3, drv0, drv1, drv2, \ 243 drv3, offset0, offset1, \ 244 offset2, offset3, pull0, \ 245 pull1, pull2, pull3) \ 246 { \ 247 .bank_num = id, \ 248 .nr_pins = pins, \ 249 .name = label, \ 250 .iomux = { \ 251 { .type = iom0, .offset = -1 }, \ 252 { .type = iom1, .offset = -1 }, \ 253 { .type = iom2, .offset = -1 }, \ 254 { .type = iom3, .offset = -1 }, \ 255 }, \ 256 .drv = { \ 257 { .drv_type = drv0, .offset = offset0 }, \ 258 { .drv_type = drv1, .offset = offset1 }, \ 259 { .drv_type = drv2, .offset = offset2 }, \ 260 { .drv_type = drv3, .offset = offset3 }, \ 261 }, \ 262 .pull_type[0] = pull0, \ 263 .pull_type[1] = pull1, \ 264 .pull_type[2] = pull2, \ 265 .pull_type[3] = pull3, \ 266 } 267 268 /** 269 * struct rockchip_mux_recalced_data: represent a pin iomux data. 270 * @num: bank number. 271 * @pin: pin number. 272 * @bit: index at register. 273 * @reg: register offset. 274 * @mask: mask bit 275 */ 276 struct rockchip_mux_recalced_data { 277 u8 num; 278 u8 pin; 279 u32 reg; 280 u8 bit; 281 u8 mask; 282 }; 283 284 /** 285 * struct rockchip_mux_recalced_data: represent a pin iomux data. 286 * @bank_num: bank number. 287 * @pin: index at register or used to calc index. 288 * @func: the min pin. 289 * @route_offset: the max pin. 290 * @route_val: the register offset. 291 */ 292 struct rockchip_mux_route_data { 293 u8 bank_num; 294 u8 pin; 295 u8 func; 296 u32 route_offset; 297 u32 route_val; 298 }; 299 300 /** 301 */ 302 struct rockchip_pin_ctrl { 303 struct rockchip_pin_bank *pin_banks; 304 u32 nr_banks; 305 u32 nr_pins; 306 char *label; 307 enum rockchip_pinctrl_type type; 308 int grf_mux_offset; 309 int pmu_mux_offset; 310 int grf_drv_offset; 311 int pmu_drv_offset; 312 struct rockchip_mux_recalced_data *iomux_recalced; 313 u32 niomux_recalced; 314 struct rockchip_mux_route_data *iomux_routes; 315 u32 niomux_routes; 316 317 int (*ctrl_data_re_init)(struct rockchip_pin_ctrl *ctrl); 318 319 int (*soc_data_init)(struct rockchip_pinctrl_priv *info); 320 321 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 322 int pin_num, struct regmap **regmap, 323 int *reg, u8 *bit); 324 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 325 int pin_num, struct regmap **regmap, 326 int *reg, u8 *bit); 327 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 328 int pin_num, struct regmap **regmap, 329 int *reg, u8 *bit); 330 int (*slew_rate_calc_reg)(struct rockchip_pin_bank *bank, 331 int pin_num, struct regmap **regmap, 332 int *reg, u8 *bit); 333 }; 334 335 /** 336 */ 337 struct rockchip_pinctrl_priv { 338 struct rockchip_pin_ctrl *ctrl; 339 struct regmap *regmap_base; 340 struct regmap *regmap_pmu; 341 342 }; 343 344 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 345 { 346 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 347 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 348 349 if (bank >= ctrl->nr_banks) { 350 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 351 return -EINVAL; 352 } 353 354 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 355 debug("pin conf pin %d >= %d\n", pin, 356 MAX_ROCKCHIP_GPIO_PER_BANK); 357 return -EINVAL; 358 } 359 360 return 0; 361 } 362 363 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 364 { 365 .num = 1, 366 .pin = 0, 367 .reg = 0x418, 368 .bit = 0, 369 .mask = 0x3 370 }, { 371 .num = 1, 372 .pin = 1, 373 .reg = 0x418, 374 .bit = 2, 375 .mask = 0x3 376 }, { 377 .num = 1, 378 .pin = 2, 379 .reg = 0x418, 380 .bit = 4, 381 .mask = 0x3 382 }, { 383 .num = 1, 384 .pin = 3, 385 .reg = 0x418, 386 .bit = 6, 387 .mask = 0x3 388 }, { 389 .num = 1, 390 .pin = 4, 391 .reg = 0x418, 392 .bit = 8, 393 .mask = 0x3 394 }, { 395 .num = 1, 396 .pin = 5, 397 .reg = 0x418, 398 .bit = 10, 399 .mask = 0x3 400 }, { 401 .num = 1, 402 .pin = 6, 403 .reg = 0x418, 404 .bit = 12, 405 .mask = 0x3 406 }, { 407 .num = 1, 408 .pin = 7, 409 .reg = 0x418, 410 .bit = 14, 411 .mask = 0x3 412 }, { 413 .num = 1, 414 .pin = 8, 415 .reg = 0x41c, 416 .bit = 0, 417 .mask = 0x3 418 }, { 419 .num = 1, 420 .pin = 9, 421 .reg = 0x41c, 422 .bit = 2, 423 .mask = 0x3 424 }, 425 }; 426 427 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 428 { 429 .num = 0, 430 .pin = 20, 431 .reg = 0x10000, 432 .bit = 0, 433 .mask = 0xf 434 }, 435 { 436 .num = 0, 437 .pin = 21, 438 .reg = 0x10000, 439 .bit = 4, 440 .mask = 0xf 441 }, 442 { 443 .num = 0, 444 .pin = 22, 445 .reg = 0x10000, 446 .bit = 8, 447 .mask = 0xf 448 }, 449 { 450 .num = 0, 451 .pin = 23, 452 .reg = 0x10000, 453 .bit = 12, 454 .mask = 0xf 455 }, 456 }; 457 458 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 459 { 460 .num = 2, 461 .pin = 20, 462 .reg = 0xe8, 463 .bit = 0, 464 .mask = 0x7 465 }, { 466 .num = 2, 467 .pin = 21, 468 .reg = 0xe8, 469 .bit = 4, 470 .mask = 0x7 471 }, { 472 .num = 2, 473 .pin = 22, 474 .reg = 0xe8, 475 .bit = 8, 476 .mask = 0x7 477 }, { 478 .num = 2, 479 .pin = 23, 480 .reg = 0xe8, 481 .bit = 12, 482 .mask = 0x7 483 }, { 484 .num = 2, 485 .pin = 24, 486 .reg = 0xd4, 487 .bit = 12, 488 .mask = 0x7 489 }, 490 }; 491 492 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 493 { 494 .num = 1, 495 .pin = 14, 496 .reg = 0x28, 497 .bit = 12, 498 .mask = 0x7 499 }, { 500 .num = 1, 501 .pin = 15, 502 .reg = 0x2c, 503 .bit = 0, 504 .mask = 0x3 505 }, { 506 .num = 1, 507 .pin = 18, 508 .reg = 0x30, 509 .bit = 4, 510 .mask = 0x7 511 }, { 512 .num = 1, 513 .pin = 19, 514 .reg = 0x30, 515 .bit = 8, 516 .mask = 0x7 517 }, { 518 .num = 1, 519 .pin = 20, 520 .reg = 0x30, 521 .bit = 12, 522 .mask = 0x7 523 }, { 524 .num = 1, 525 .pin = 21, 526 .reg = 0x34, 527 .bit = 0, 528 .mask = 0x7 529 }, { 530 .num = 1, 531 .pin = 22, 532 .reg = 0x34, 533 .bit = 4, 534 .mask = 0x7 535 }, { 536 .num = 1, 537 .pin = 23, 538 .reg = 0x34, 539 .bit = 8, 540 .mask = 0x7 541 }, { 542 .num = 3, 543 .pin = 12, 544 .reg = 0x68, 545 .bit = 8, 546 .mask = 0x7 547 }, { 548 .num = 3, 549 .pin = 13, 550 .reg = 0x68, 551 .bit = 12, 552 .mask = 0x7 553 }, 554 }; 555 556 static struct rockchip_mux_recalced_data rk3308b_mux_recalced_data[] = { 557 { 558 .num = 1, 559 .pin = 14, 560 .reg = 0x28, 561 .bit = 12, 562 .mask = 0xf 563 }, { 564 .num = 1, 565 .pin = 15, 566 .reg = 0x2c, 567 .bit = 0, 568 .mask = 0x3 569 }, { 570 .num = 1, 571 .pin = 18, 572 .reg = 0x30, 573 .bit = 4, 574 .mask = 0xf 575 }, { 576 .num = 1, 577 .pin = 19, 578 .reg = 0x30, 579 .bit = 8, 580 .mask = 0xf 581 }, { 582 .num = 1, 583 .pin = 20, 584 .reg = 0x30, 585 .bit = 12, 586 .mask = 0xf 587 }, { 588 .num = 1, 589 .pin = 21, 590 .reg = 0x34, 591 .bit = 0, 592 .mask = 0xf 593 }, { 594 .num = 1, 595 .pin = 22, 596 .reg = 0x34, 597 .bit = 4, 598 .mask = 0xf 599 }, { 600 .num = 1, 601 .pin = 23, 602 .reg = 0x34, 603 .bit = 8, 604 .mask = 0xf 605 }, { 606 .num = 3, 607 .pin = 12, 608 .reg = 0x68, 609 .bit = 8, 610 .mask = 0xf 611 }, { 612 .num = 3, 613 .pin = 13, 614 .reg = 0x68, 615 .bit = 12, 616 .mask = 0xf 617 }, { 618 .num = 2, 619 .pin = 2, 620 .reg = 0x608, 621 .bit = 0, 622 .mask = 0x7 623 }, { 624 .num = 2, 625 .pin = 3, 626 .reg = 0x608, 627 .bit = 4, 628 .mask = 0x7 629 }, { 630 .num = 2, 631 .pin = 16, 632 .reg = 0x610, 633 .bit = 8, 634 .mask = 0x7 635 }, { 636 .num = 3, 637 .pin = 10, 638 .reg = 0x610, 639 .bit = 0, 640 .mask = 0x7 641 }, { 642 .num = 3, 643 .pin = 11, 644 .reg = 0x610, 645 .bit = 4, 646 .mask = 0x7 647 }, 648 }; 649 650 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 651 { 652 .num = 2, 653 .pin = 12, 654 .reg = 0x24, 655 .bit = 8, 656 .mask = 0x3 657 }, { 658 .num = 2, 659 .pin = 15, 660 .reg = 0x28, 661 .bit = 0, 662 .mask = 0x7 663 }, { 664 .num = 2, 665 .pin = 23, 666 .reg = 0x30, 667 .bit = 14, 668 .mask = 0x3 669 }, 670 }; 671 672 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 673 int *reg, u8 *bit, int *mask) 674 { 675 struct rockchip_pinctrl_priv *priv = bank->priv; 676 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 677 struct rockchip_mux_recalced_data *data; 678 int i; 679 680 for (i = 0; i < ctrl->niomux_recalced; i++) { 681 data = &ctrl->iomux_recalced[i]; 682 if (data->num == bank->bank_num && 683 data->pin == pin) 684 break; 685 } 686 687 if (i >= ctrl->niomux_recalced) 688 return; 689 690 *reg = data->reg; 691 *mask = data->mask; 692 *bit = data->bit; 693 } 694 695 static struct rockchip_mux_route_data px30_mux_route_data[] = { 696 { 697 /* cif-d2m0 */ 698 .bank_num = 2, 699 .pin = 0, 700 .func = 1, 701 .route_offset = 0x184, 702 .route_val = BIT(16 + 7), 703 }, { 704 /* cif-d2m1 */ 705 .bank_num = 3, 706 .pin = 3, 707 .func = 3, 708 .route_offset = 0x184, 709 .route_val = BIT(16 + 7) | BIT(7), 710 }, { 711 /* pdm-m0 */ 712 .bank_num = 3, 713 .pin = 22, 714 .func = 2, 715 .route_offset = 0x184, 716 .route_val = BIT(16 + 8), 717 }, { 718 /* pdm-m1 */ 719 .bank_num = 2, 720 .pin = 22, 721 .func = 1, 722 .route_offset = 0x184, 723 .route_val = BIT(16 + 8) | BIT(8), 724 }, { 725 /* uart2-rxm0 */ 726 .bank_num = 1, 727 .pin = 27, 728 .func = 2, 729 .route_offset = 0x184, 730 .route_val = BIT(16 + 10), 731 }, { 732 /* uart2-rxm1 */ 733 .bank_num = 2, 734 .pin = 14, 735 .func = 2, 736 .route_offset = 0x184, 737 .route_val = BIT(16 + 10) | BIT(10), 738 }, { 739 /* uart3-rxm0 */ 740 .bank_num = 0, 741 .pin = 17, 742 .func = 2, 743 .route_offset = 0x184, 744 .route_val = BIT(16 + 9), 745 }, { 746 /* uart3-rxm1 */ 747 .bank_num = 1, 748 .pin = 15, 749 .func = 2, 750 .route_offset = 0x184, 751 .route_val = BIT(16 + 9) | BIT(9), 752 }, 753 }; 754 755 static struct rockchip_mux_route_data rk1808_mux_route_data[] = { 756 { 757 /* i2c2m0_sda */ 758 .bank_num = 3, 759 .pin = 12, 760 .func = 2, 761 .route_offset = 0x190, 762 .route_val = BIT(16 + 3), 763 }, { 764 /* i2c2m1_sda */ 765 .bank_num = 1, 766 .pin = 13, 767 .func = 2, 768 .route_offset = 0x190, 769 .route_val = BIT(16 + 3) | BIT(3), 770 }, { 771 /* uart2_rxm0 */ 772 .bank_num = 4, 773 .pin = 3, 774 .func = 2, 775 .route_offset = 0x190, 776 .route_val = BIT(16 + 14) | BIT(16 + 15), 777 }, { 778 /* uart2_rxm1 */ 779 .bank_num = 2, 780 .pin = 25, 781 .func = 2, 782 .route_offset = 0x190, 783 .route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15), 784 }, { 785 /* uart2_rxm2 */ 786 .bank_num = 3, 787 .pin = 4, 788 .func = 2, 789 .route_offset = 0x190, 790 .route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15), 791 }, 792 }; 793 794 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 795 { 796 /* spi-0 */ 797 .bank_num = 1, 798 .pin = 10, 799 .func = 1, 800 .route_offset = 0x144, 801 .route_val = BIT(16 + 3) | BIT(16 + 4), 802 }, { 803 /* spi-1 */ 804 .bank_num = 1, 805 .pin = 27, 806 .func = 3, 807 .route_offset = 0x144, 808 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 809 }, { 810 /* spi-2 */ 811 .bank_num = 0, 812 .pin = 13, 813 .func = 2, 814 .route_offset = 0x144, 815 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 816 }, { 817 /* i2s-0 */ 818 .bank_num = 1, 819 .pin = 5, 820 .func = 1, 821 .route_offset = 0x144, 822 .route_val = BIT(16 + 5), 823 }, { 824 /* i2s-1 */ 825 .bank_num = 0, 826 .pin = 14, 827 .func = 1, 828 .route_offset = 0x144, 829 .route_val = BIT(16 + 5) | BIT(5), 830 }, { 831 /* emmc-0 */ 832 .bank_num = 1, 833 .pin = 22, 834 .func = 2, 835 .route_offset = 0x144, 836 .route_val = BIT(16 + 6), 837 }, { 838 /* emmc-1 */ 839 .bank_num = 2, 840 .pin = 4, 841 .func = 2, 842 .route_offset = 0x144, 843 .route_val = BIT(16 + 6) | BIT(6), 844 }, 845 }; 846 847 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 848 { 849 /* pwm0-0 */ 850 .bank_num = 0, 851 .pin = 26, 852 .func = 1, 853 .route_offset = 0x50, 854 .route_val = BIT(16), 855 }, { 856 /* pwm0-1 */ 857 .bank_num = 3, 858 .pin = 21, 859 .func = 1, 860 .route_offset = 0x50, 861 .route_val = BIT(16) | BIT(0), 862 }, { 863 /* pwm1-0 */ 864 .bank_num = 0, 865 .pin = 27, 866 .func = 1, 867 .route_offset = 0x50, 868 .route_val = BIT(16 + 1), 869 }, { 870 /* pwm1-1 */ 871 .bank_num = 0, 872 .pin = 30, 873 .func = 2, 874 .route_offset = 0x50, 875 .route_val = BIT(16 + 1) | BIT(1), 876 }, { 877 /* pwm2-0 */ 878 .bank_num = 0, 879 .pin = 28, 880 .func = 1, 881 .route_offset = 0x50, 882 .route_val = BIT(16 + 2), 883 }, { 884 /* pwm2-1 */ 885 .bank_num = 1, 886 .pin = 12, 887 .func = 2, 888 .route_offset = 0x50, 889 .route_val = BIT(16 + 2) | BIT(2), 890 }, { 891 /* pwm3-0 */ 892 .bank_num = 3, 893 .pin = 26, 894 .func = 1, 895 .route_offset = 0x50, 896 .route_val = BIT(16 + 3), 897 }, { 898 /* pwm3-1 */ 899 .bank_num = 1, 900 .pin = 11, 901 .func = 2, 902 .route_offset = 0x50, 903 .route_val = BIT(16 + 3) | BIT(3), 904 }, { 905 /* sdio-0_d0 */ 906 .bank_num = 1, 907 .pin = 1, 908 .func = 1, 909 .route_offset = 0x50, 910 .route_val = BIT(16 + 4), 911 }, { 912 /* sdio-1_d0 */ 913 .bank_num = 3, 914 .pin = 2, 915 .func = 1, 916 .route_offset = 0x50, 917 .route_val = BIT(16 + 4) | BIT(4), 918 }, { 919 /* spi-0_rx */ 920 .bank_num = 0, 921 .pin = 13, 922 .func = 2, 923 .route_offset = 0x50, 924 .route_val = BIT(16 + 5), 925 }, { 926 /* spi-1_rx */ 927 .bank_num = 2, 928 .pin = 0, 929 .func = 2, 930 .route_offset = 0x50, 931 .route_val = BIT(16 + 5) | BIT(5), 932 }, { 933 /* emmc-0_cmd */ 934 .bank_num = 1, 935 .pin = 22, 936 .func = 2, 937 .route_offset = 0x50, 938 .route_val = BIT(16 + 7), 939 }, { 940 /* emmc-1_cmd */ 941 .bank_num = 2, 942 .pin = 4, 943 .func = 2, 944 .route_offset = 0x50, 945 .route_val = BIT(16 + 7) | BIT(7), 946 }, { 947 /* uart2-0_rx */ 948 .bank_num = 1, 949 .pin = 19, 950 .func = 2, 951 .route_offset = 0x50, 952 .route_val = BIT(16 + 8), 953 }, { 954 /* uart2-1_rx */ 955 .bank_num = 1, 956 .pin = 10, 957 .func = 2, 958 .route_offset = 0x50, 959 .route_val = BIT(16 + 8) | BIT(8), 960 }, { 961 /* uart1-0_rx */ 962 .bank_num = 1, 963 .pin = 10, 964 .func = 1, 965 .route_offset = 0x50, 966 .route_val = BIT(16 + 11), 967 }, { 968 /* uart1-1_rx */ 969 .bank_num = 3, 970 .pin = 13, 971 .func = 1, 972 .route_offset = 0x50, 973 .route_val = BIT(16 + 11) | BIT(11), 974 }, 975 }; 976 977 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 978 { 979 /* edphdmi_cecinoutt1 */ 980 .bank_num = 7, 981 .pin = 16, 982 .func = 2, 983 .route_offset = 0x264, 984 .route_val = BIT(16 + 12) | BIT(12), 985 }, { 986 /* edphdmi_cecinout */ 987 .bank_num = 7, 988 .pin = 23, 989 .func = 4, 990 .route_offset = 0x264, 991 .route_val = BIT(16 + 12), 992 }, 993 }; 994 995 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 996 { 997 /* rtc_clk */ 998 .bank_num = 0, 999 .pin = 19, 1000 .func = 1, 1001 .route_offset = 0x314, 1002 .route_val = BIT(16 + 0) | BIT(0), 1003 }, { 1004 /* uart2_rxm0 */ 1005 .bank_num = 1, 1006 .pin = 22, 1007 .func = 2, 1008 .route_offset = 0x314, 1009 .route_val = BIT(16 + 2) | BIT(16 + 3), 1010 }, { 1011 /* uart2_rxm1 */ 1012 .bank_num = 4, 1013 .pin = 26, 1014 .func = 2, 1015 .route_offset = 0x314, 1016 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1017 }, { 1018 /* i2c3_sdam0 */ 1019 .bank_num = 0, 1020 .pin = 23, 1021 .func = 2, 1022 .route_offset = 0x314, 1023 .route_val = BIT(16 + 4), 1024 }, { 1025 /* i2c3_sdam1 */ 1026 .bank_num = 3, 1027 .pin = 12, 1028 .func = 2, 1029 .route_offset = 0x314, 1030 .route_val = BIT(16 + 4) | BIT(4), 1031 }, { 1032 /* i2s-8ch-1-sclktxm0 */ 1033 .bank_num = 1, 1034 .pin = 3, 1035 .func = 2, 1036 .route_offset = 0x308, 1037 .route_val = BIT(16 + 3), 1038 }, { 1039 /* i2s-8ch-1-sclkrxm0 */ 1040 .bank_num = 1, 1041 .pin = 4, 1042 .func = 2, 1043 .route_offset = 0x308, 1044 .route_val = BIT(16 + 3), 1045 }, { 1046 /* i2s-8ch-1-sclktxm1 */ 1047 .bank_num = 1, 1048 .pin = 13, 1049 .func = 2, 1050 .route_offset = 0x308, 1051 .route_val = BIT(16 + 3) | BIT(3), 1052 }, { 1053 /* i2s-8ch-1-sclkrxm1 */ 1054 .bank_num = 1, 1055 .pin = 14, 1056 .func = 2, 1057 .route_offset = 0x308, 1058 .route_val = BIT(16 + 3) | BIT(3), 1059 }, { 1060 /* pdm-clkm0 */ 1061 .bank_num = 1, 1062 .pin = 4, 1063 .func = 3, 1064 .route_offset = 0x308, 1065 .route_val = BIT(16 + 12) | BIT(16 + 13), 1066 }, { 1067 /* pdm-clkm1 */ 1068 .bank_num = 1, 1069 .pin = 14, 1070 .func = 4, 1071 .route_offset = 0x308, 1072 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1073 }, { 1074 /* pdm-clkm2 */ 1075 .bank_num = 2, 1076 .pin = 6, 1077 .func = 2, 1078 .route_offset = 0x308, 1079 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1080 }, { 1081 /* pdm-clkm-m2 */ 1082 .bank_num = 2, 1083 .pin = 4, 1084 .func = 3, 1085 .route_offset = 0x600, 1086 .route_val = BIT(16 + 2) | BIT(2), 1087 }, 1088 }; 1089 1090 static struct rockchip_mux_route_data rk3308b_mux_route_data[] = { 1091 { 1092 /* rtc_clk */ 1093 .bank_num = 0, 1094 .pin = 19, 1095 .func = 1, 1096 .route_offset = 0x314, 1097 .route_val = BIT(16 + 0) | BIT(0), 1098 }, { 1099 /* uart2_rxm0 */ 1100 .bank_num = 1, 1101 .pin = 22, 1102 .func = 2, 1103 .route_offset = 0x314, 1104 .route_val = BIT(16 + 2) | BIT(16 + 3), 1105 }, { 1106 /* uart2_rxm1 */ 1107 .bank_num = 4, 1108 .pin = 26, 1109 .func = 2, 1110 .route_offset = 0x314, 1111 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1112 }, { 1113 /* i2c3_sdam0 */ 1114 .bank_num = 0, 1115 .pin = 15, 1116 .func = 2, 1117 .route_offset = 0x608, 1118 .route_val = BIT(16 + 8) | BIT(16 + 9), 1119 }, { 1120 /* i2c3_sdam1 */ 1121 .bank_num = 3, 1122 .pin = 12, 1123 .func = 2, 1124 .route_offset = 0x608, 1125 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 1126 }, { 1127 /* i2c3_sdam2 */ 1128 .bank_num = 2, 1129 .pin = 0, 1130 .func = 3, 1131 .route_offset = 0x608, 1132 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 1133 }, { 1134 /* i2s-8ch-1-sclktxm0 */ 1135 .bank_num = 1, 1136 .pin = 3, 1137 .func = 2, 1138 .route_offset = 0x308, 1139 .route_val = BIT(16 + 3), 1140 }, { 1141 /* i2s-8ch-1-sclkrxm0 */ 1142 .bank_num = 1, 1143 .pin = 4, 1144 .func = 2, 1145 .route_offset = 0x308, 1146 .route_val = BIT(16 + 3), 1147 }, { 1148 /* i2s-8ch-1-sclktxm1 */ 1149 .bank_num = 1, 1150 .pin = 13, 1151 .func = 2, 1152 .route_offset = 0x308, 1153 .route_val = BIT(16 + 3) | BIT(3), 1154 }, { 1155 /* i2s-8ch-1-sclkrxm1 */ 1156 .bank_num = 1, 1157 .pin = 14, 1158 .func = 2, 1159 .route_offset = 0x308, 1160 .route_val = BIT(16 + 3) | BIT(3), 1161 }, { 1162 /* pdm-clkm0 */ 1163 .bank_num = 1, 1164 .pin = 4, 1165 .func = 3, 1166 .route_offset = 0x308, 1167 .route_val = BIT(16 + 12) | BIT(16 + 13), 1168 }, { 1169 /* pdm-clkm1 */ 1170 .bank_num = 1, 1171 .pin = 14, 1172 .func = 4, 1173 .route_offset = 0x308, 1174 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1175 }, { 1176 /* pdm-clkm2 */ 1177 .bank_num = 2, 1178 .pin = 6, 1179 .func = 2, 1180 .route_offset = 0x308, 1181 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1182 }, { 1183 /* pdm-clkm-m2 */ 1184 .bank_num = 2, 1185 .pin = 4, 1186 .func = 3, 1187 .route_offset = 0x600, 1188 .route_val = BIT(16 + 2) | BIT(2), 1189 }, { 1190 /* spi1_miso */ 1191 .bank_num = 3, 1192 .pin = 10, 1193 .func = 3, 1194 .route_offset = 0x314, 1195 .route_val = BIT(16 + 9), 1196 }, { 1197 /* spi1_miso_m1 */ 1198 .bank_num = 2, 1199 .pin = 4, 1200 .func = 2, 1201 .route_offset = 0x314, 1202 .route_val = BIT(16 + 9) | BIT(9), 1203 }, { 1204 /* owire_m0 */ 1205 .bank_num = 0, 1206 .pin = 11, 1207 .func = 3, 1208 .route_offset = 0x314, 1209 .route_val = BIT(16 + 10) | BIT(16 + 11), 1210 }, { 1211 /* owire_m1 */ 1212 .bank_num = 1, 1213 .pin = 22, 1214 .func = 7, 1215 .route_offset = 0x314, 1216 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1217 }, { 1218 /* owire_m2 */ 1219 .bank_num = 2, 1220 .pin = 2, 1221 .func = 5, 1222 .route_offset = 0x314, 1223 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1224 }, { 1225 /* can_rxd_m0 */ 1226 .bank_num = 0, 1227 .pin = 11, 1228 .func = 2, 1229 .route_offset = 0x314, 1230 .route_val = BIT(16 + 12) | BIT(16 + 13), 1231 }, { 1232 /* can_rxd_m1 */ 1233 .bank_num = 1, 1234 .pin = 22, 1235 .func = 5, 1236 .route_offset = 0x314, 1237 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1238 }, { 1239 /* can_rxd_m2 */ 1240 .bank_num = 2, 1241 .pin = 2, 1242 .func = 4, 1243 .route_offset = 0x314, 1244 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1245 }, { 1246 /* mac_rxd0_m0 */ 1247 .bank_num = 1, 1248 .pin = 20, 1249 .func = 3, 1250 .route_offset = 0x314, 1251 .route_val = BIT(16 + 14), 1252 }, { 1253 /* mac_rxd0_m1 */ 1254 .bank_num = 4, 1255 .pin = 2, 1256 .func = 2, 1257 .route_offset = 0x314, 1258 .route_val = BIT(16 + 14) | BIT(14), 1259 }, { 1260 /* uart3_rx */ 1261 .bank_num = 3, 1262 .pin = 12, 1263 .func = 4, 1264 .route_offset = 0x314, 1265 .route_val = BIT(16 + 15), 1266 }, { 1267 /* uart3_rx_m1 */ 1268 .bank_num = 0, 1269 .pin = 17, 1270 .func = 3, 1271 .route_offset = 0x314, 1272 .route_val = BIT(16 + 15) | BIT(15), 1273 }, 1274 }; 1275 1276 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1277 { 1278 /* uart2dbg_rxm0 */ 1279 .bank_num = 1, 1280 .pin = 1, 1281 .func = 2, 1282 .route_offset = 0x50, 1283 .route_val = BIT(16) | BIT(16 + 1), 1284 }, { 1285 /* uart2dbg_rxm1 */ 1286 .bank_num = 2, 1287 .pin = 1, 1288 .func = 1, 1289 .route_offset = 0x50, 1290 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1291 }, { 1292 /* gmac-m1_rxd0 */ 1293 .bank_num = 1, 1294 .pin = 11, 1295 .func = 2, 1296 .route_offset = 0x50, 1297 .route_val = BIT(16 + 2) | BIT(2), 1298 }, { 1299 /* gmac-m1-optimized_rxd3 */ 1300 .bank_num = 1, 1301 .pin = 14, 1302 .func = 2, 1303 .route_offset = 0x50, 1304 .route_val = BIT(16 + 10) | BIT(10), 1305 }, { 1306 /* pdm_sdi0m0 */ 1307 .bank_num = 2, 1308 .pin = 19, 1309 .func = 2, 1310 .route_offset = 0x50, 1311 .route_val = BIT(16 + 3), 1312 }, { 1313 /* pdm_sdi0m1 */ 1314 .bank_num = 1, 1315 .pin = 23, 1316 .func = 3, 1317 .route_offset = 0x50, 1318 .route_val = BIT(16 + 3) | BIT(3), 1319 }, { 1320 /* spi_rxdm2 */ 1321 .bank_num = 3, 1322 .pin = 2, 1323 .func = 4, 1324 .route_offset = 0x50, 1325 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1326 }, { 1327 /* i2s2_sdim0 */ 1328 .bank_num = 1, 1329 .pin = 24, 1330 .func = 1, 1331 .route_offset = 0x50, 1332 .route_val = BIT(16 + 6), 1333 }, { 1334 /* i2s2_sdim1 */ 1335 .bank_num = 3, 1336 .pin = 2, 1337 .func = 6, 1338 .route_offset = 0x50, 1339 .route_val = BIT(16 + 6) | BIT(6), 1340 }, { 1341 /* card_iom1 */ 1342 .bank_num = 2, 1343 .pin = 22, 1344 .func = 3, 1345 .route_offset = 0x50, 1346 .route_val = BIT(16 + 7) | BIT(7), 1347 }, { 1348 /* tsp_d5m1 */ 1349 .bank_num = 2, 1350 .pin = 16, 1351 .func = 3, 1352 .route_offset = 0x50, 1353 .route_val = BIT(16 + 8) | BIT(8), 1354 }, { 1355 /* cif_data5m1 */ 1356 .bank_num = 2, 1357 .pin = 16, 1358 .func = 4, 1359 .route_offset = 0x50, 1360 .route_val = BIT(16 + 9) | BIT(9), 1361 }, 1362 }; 1363 1364 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1365 { 1366 /* uart2dbga_rx */ 1367 .bank_num = 4, 1368 .pin = 8, 1369 .func = 2, 1370 .route_offset = 0xe21c, 1371 .route_val = BIT(16 + 10) | BIT(16 + 11), 1372 }, { 1373 /* uart2dbgb_rx */ 1374 .bank_num = 4, 1375 .pin = 16, 1376 .func = 2, 1377 .route_offset = 0xe21c, 1378 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1379 }, { 1380 /* uart2dbgc_rx */ 1381 .bank_num = 4, 1382 .pin = 19, 1383 .func = 1, 1384 .route_offset = 0xe21c, 1385 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1386 }, { 1387 /* pcie_clkreqn */ 1388 .bank_num = 2, 1389 .pin = 26, 1390 .func = 2, 1391 .route_offset = 0xe21c, 1392 .route_val = BIT(16 + 14), 1393 }, { 1394 /* pcie_clkreqnb */ 1395 .bank_num = 4, 1396 .pin = 24, 1397 .func = 1, 1398 .route_offset = 0xe21c, 1399 .route_val = BIT(16 + 14) | BIT(14), 1400 }, 1401 }; 1402 1403 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1404 int mux, u32 *reg, u32 *value) 1405 { 1406 struct rockchip_pinctrl_priv *priv = bank->priv; 1407 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1408 struct rockchip_mux_route_data *data; 1409 int i; 1410 1411 for (i = 0; i < ctrl->niomux_routes; i++) { 1412 data = &ctrl->iomux_routes[i]; 1413 if ((data->bank_num == bank->bank_num) && 1414 (data->pin == pin) && (data->func == mux)) 1415 break; 1416 } 1417 1418 if (i >= ctrl->niomux_routes) 1419 return false; 1420 1421 *reg = data->route_offset; 1422 *value = data->route_val; 1423 1424 return true; 1425 } 1426 1427 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1428 { 1429 struct rockchip_pinctrl_priv *priv = bank->priv; 1430 int iomux_num = (pin / 8); 1431 struct regmap *regmap; 1432 unsigned int val; 1433 int reg, ret, mask, mux_type; 1434 u8 bit; 1435 1436 if (iomux_num > 3) 1437 return -EINVAL; 1438 1439 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1440 debug("pin %d is unrouted\n", pin); 1441 return -EINVAL; 1442 } 1443 1444 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1445 return RK_FUNC_GPIO; 1446 1447 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1448 regmap = priv->regmap_pmu; 1449 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1450 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 1451 else 1452 regmap = priv->regmap_base; 1453 1454 /* get basic quadrupel of mux registers and the correct reg inside */ 1455 mux_type = bank->iomux[iomux_num].type; 1456 reg = bank->iomux[iomux_num].offset; 1457 if (mux_type & IOMUX_WIDTH_4BIT) { 1458 if ((pin % 8) >= 4) 1459 reg += 0x4; 1460 bit = (pin % 4) * 4; 1461 mask = 0xf; 1462 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1463 if ((pin % 8) >= 5) 1464 reg += 0x4; 1465 bit = (pin % 8 % 5) * 3; 1466 mask = 0x7; 1467 } else { 1468 bit = (pin % 8) * 2; 1469 mask = 0x3; 1470 } 1471 1472 if (bank->recalced_mask & BIT(pin)) 1473 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1474 1475 ret = regmap_read(regmap, reg, &val); 1476 if (ret) 1477 return ret; 1478 1479 return ((val >> bit) & mask); 1480 } 1481 1482 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1483 int index) 1484 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1485 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1486 1487 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1488 } 1489 1490 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1491 int pin, int mux) 1492 { 1493 int iomux_num = (pin / 8); 1494 1495 if (iomux_num > 3) 1496 return -EINVAL; 1497 1498 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1499 debug("pin %d is unrouted\n", pin); 1500 return -EINVAL; 1501 } 1502 1503 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1504 if (mux != IOMUX_GPIO_ONLY) { 1505 debug("pin %d only supports a gpio mux\n", pin); 1506 return -ENOTSUPP; 1507 } 1508 } 1509 1510 return 0; 1511 } 1512 1513 /* 1514 * Set a new mux function for a pin. 1515 * 1516 * The register is divided into the upper and lower 16 bit. When changing 1517 * a value, the previous register value is not read and changed. Instead 1518 * it seems the changed bits are marked in the upper 16 bit, while the 1519 * changed value gets set in the same offset in the lower 16 bit. 1520 * All pin settings seem to be 2 bit wide in both the upper and lower 1521 * parts. 1522 * @bank: pin bank to change 1523 * @pin: pin to change 1524 * @mux: new mux function to set 1525 */ 1526 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1527 { 1528 struct rockchip_pinctrl_priv *priv = bank->priv; 1529 int iomux_num = (pin / 8); 1530 struct regmap *regmap; 1531 int reg, ret, mask, mux_type; 1532 u8 bit; 1533 u32 data, route_reg, route_val; 1534 1535 ret = rockchip_verify_mux(bank, pin, mux); 1536 if (ret < 0) 1537 return ret; 1538 1539 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1540 return 0; 1541 1542 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1543 1544 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1545 regmap = priv->regmap_pmu; 1546 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1547 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; 1548 else 1549 regmap = priv->regmap_base; 1550 1551 /* get basic quadrupel of mux registers and the correct reg inside */ 1552 mux_type = bank->iomux[iomux_num].type; 1553 reg = bank->iomux[iomux_num].offset; 1554 if (mux_type & IOMUX_WIDTH_4BIT) { 1555 if ((pin % 8) >= 4) 1556 reg += 0x4; 1557 bit = (pin % 4) * 4; 1558 mask = 0xf; 1559 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1560 if ((pin % 8) >= 5) 1561 reg += 0x4; 1562 bit = (pin % 8 % 5) * 3; 1563 mask = 0x7; 1564 } else { 1565 bit = (pin % 8) * 2; 1566 mask = 0x3; 1567 } 1568 1569 if (bank->recalced_mask & BIT(pin)) 1570 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1571 1572 if (bank->route_mask & BIT(pin)) { 1573 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1574 &route_val)) { 1575 ret = regmap_write(regmap, route_reg, route_val); 1576 if (ret) 1577 return ret; 1578 } 1579 } 1580 1581 if (mux_type & IOMUX_WRITABLE_32BIT) { 1582 regmap_read(regmap, reg, &data); 1583 data &= ~(mask << bit); 1584 } else { 1585 data = (mask << (bit + 16)); 1586 } 1587 1588 data |= (mux & mask) << bit; 1589 ret = regmap_write(regmap, reg, data); 1590 1591 return ret; 1592 } 1593 1594 #define PX30_PULL_PMU_OFFSET 0x10 1595 #define PX30_PULL_GRF_OFFSET 0x60 1596 #define PX30_PULL_BITS_PER_PIN 2 1597 #define PX30_PULL_PINS_PER_REG 8 1598 #define PX30_PULL_BANK_STRIDE 16 1599 1600 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1601 int pin_num, struct regmap **regmap, 1602 int *reg, u8 *bit) 1603 { 1604 struct rockchip_pinctrl_priv *priv = bank->priv; 1605 1606 /* The first 32 pins of the first bank are located in PMU */ 1607 if (bank->bank_num == 0) { 1608 *regmap = priv->regmap_pmu; 1609 *reg = PX30_PULL_PMU_OFFSET; 1610 } else { 1611 *regmap = priv->regmap_base; 1612 *reg = PX30_PULL_GRF_OFFSET; 1613 1614 /* correct the offset, as we're starting with the 2nd bank */ 1615 *reg -= 0x10; 1616 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1617 } 1618 1619 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1620 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1621 *bit *= PX30_PULL_BITS_PER_PIN; 1622 } 1623 1624 #define PX30_DRV_PMU_OFFSET 0x20 1625 #define PX30_DRV_GRF_OFFSET 0xf0 1626 #define PX30_DRV_BITS_PER_PIN 2 1627 #define PX30_DRV_PINS_PER_REG 8 1628 #define PX30_DRV_BANK_STRIDE 16 1629 1630 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1631 int pin_num, struct regmap **regmap, 1632 int *reg, u8 *bit) 1633 { 1634 struct rockchip_pinctrl_priv *priv = bank->priv; 1635 1636 /* The first 32 pins of the first bank are located in PMU */ 1637 if (bank->bank_num == 0) { 1638 *regmap = priv->regmap_pmu; 1639 *reg = PX30_DRV_PMU_OFFSET; 1640 } else { 1641 *regmap = priv->regmap_base; 1642 *reg = PX30_DRV_GRF_OFFSET; 1643 1644 /* correct the offset, as we're starting with the 2nd bank */ 1645 *reg -= 0x10; 1646 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1647 } 1648 1649 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1650 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1651 *bit *= PX30_DRV_BITS_PER_PIN; 1652 } 1653 1654 #define PX30_SCHMITT_PMU_OFFSET 0x38 1655 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1656 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1657 #define PX30_SCHMITT_BANK_STRIDE 16 1658 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1659 1660 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1661 int pin_num, 1662 struct regmap **regmap, 1663 int *reg, u8 *bit) 1664 { 1665 struct rockchip_pinctrl_priv *priv = bank->priv; 1666 int pins_per_reg; 1667 1668 if (bank->bank_num == 0) { 1669 *regmap = priv->regmap_pmu; 1670 *reg = PX30_SCHMITT_PMU_OFFSET; 1671 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1672 } else { 1673 *regmap = priv->regmap_base; 1674 *reg = PX30_SCHMITT_GRF_OFFSET; 1675 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1676 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1677 } 1678 *reg += ((pin_num / pins_per_reg) * 4); 1679 *bit = pin_num % pins_per_reg; 1680 1681 return 0; 1682 } 1683 1684 #define RV1108_PULL_PMU_OFFSET 0x10 1685 #define RV1108_PULL_OFFSET 0x110 1686 #define RV1108_PULL_PINS_PER_REG 8 1687 #define RV1108_PULL_BITS_PER_PIN 2 1688 #define RV1108_PULL_BANK_STRIDE 16 1689 1690 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1691 int pin_num, struct regmap **regmap, 1692 int *reg, u8 *bit) 1693 { 1694 struct rockchip_pinctrl_priv *priv = bank->priv; 1695 1696 /* The first 24 pins of the first bank are located in PMU */ 1697 if (bank->bank_num == 0) { 1698 *regmap = priv->regmap_pmu; 1699 *reg = RV1108_PULL_PMU_OFFSET; 1700 } else { 1701 *reg = RV1108_PULL_OFFSET; 1702 *regmap = priv->regmap_base; 1703 /* correct the offset, as we're starting with the 2nd bank */ 1704 *reg -= 0x10; 1705 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1706 } 1707 1708 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1709 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1710 *bit *= RV1108_PULL_BITS_PER_PIN; 1711 } 1712 1713 #define RV1108_DRV_PMU_OFFSET 0x20 1714 #define RV1108_DRV_GRF_OFFSET 0x210 1715 #define RV1108_DRV_BITS_PER_PIN 2 1716 #define RV1108_DRV_PINS_PER_REG 8 1717 #define RV1108_DRV_BANK_STRIDE 16 1718 1719 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1720 int pin_num, struct regmap **regmap, 1721 int *reg, u8 *bit) 1722 { 1723 struct rockchip_pinctrl_priv *priv = bank->priv; 1724 1725 /* The first 24 pins of the first bank are located in PMU */ 1726 if (bank->bank_num == 0) { 1727 *regmap = priv->regmap_pmu; 1728 *reg = RV1108_DRV_PMU_OFFSET; 1729 } else { 1730 *regmap = priv->regmap_base; 1731 *reg = RV1108_DRV_GRF_OFFSET; 1732 1733 /* correct the offset, as we're starting with the 2nd bank */ 1734 *reg -= 0x10; 1735 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1736 } 1737 1738 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1739 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1740 *bit *= RV1108_DRV_BITS_PER_PIN; 1741 } 1742 1743 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1744 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1745 #define RV1108_SCHMITT_BANK_STRIDE 8 1746 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1747 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1748 1749 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1750 int pin_num, 1751 struct regmap **regmap, 1752 int *reg, u8 *bit) 1753 { 1754 struct rockchip_pinctrl_priv *priv = bank->priv; 1755 int pins_per_reg; 1756 1757 if (bank->bank_num == 0) { 1758 *regmap = priv->regmap_pmu; 1759 *reg = RV1108_SCHMITT_PMU_OFFSET; 1760 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1761 } else { 1762 *regmap = priv->regmap_base; 1763 *reg = RV1108_SCHMITT_GRF_OFFSET; 1764 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1765 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1766 } 1767 *reg += ((pin_num / pins_per_reg) * 4); 1768 *bit = pin_num % pins_per_reg; 1769 1770 return 0; 1771 } 1772 1773 #define RV1126_PULL_PMU_OFFSET 0x40 1774 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 1775 #define RV1126_PULL_PINS_PER_REG 8 1776 #define RV1126_PULL_BITS_PER_PIN 2 1777 #define RV1126_PULL_BANK_STRIDE 16 1778 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 1779 1780 static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1781 int pin_num, struct regmap **regmap, 1782 int *reg, u8 *bit) 1783 { 1784 struct rockchip_pinctrl_priv *priv = bank->priv; 1785 1786 /* The first 24 pins of the first bank are located in PMU */ 1787 if (bank->bank_num == 0) { 1788 if (RV1126_GPIO_C4_D7(pin_num)) { 1789 *regmap = priv->regmap_base; 1790 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1791 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 1792 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 1793 *bit *= RV1126_PULL_BITS_PER_PIN; 1794 return; 1795 } 1796 *regmap = priv->regmap_pmu; 1797 *reg = RV1126_PULL_PMU_OFFSET; 1798 } else { 1799 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1800 *regmap = priv->regmap_base; 1801 *reg += bank->bank_num * RV1126_PULL_BANK_STRIDE; 1802 } 1803 1804 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 1805 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 1806 *bit *= RV1126_PULL_BITS_PER_PIN; 1807 } 1808 1809 #define RV1126_DRV_PMU_OFFSET 0x20 1810 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 1811 #define RV1126_DRV_BITS_PER_PIN 4 1812 #define RV1126_DRV_PINS_PER_REG 4 1813 #define RV1126_DRV_BANK_STRIDE 32 1814 1815 static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1816 int pin_num, struct regmap **regmap, 1817 int *reg, u8 *bit) 1818 { 1819 struct rockchip_pinctrl_priv *priv = bank->priv; 1820 1821 /* The first 24 pins of the first bank are located in PMU */ 1822 if (bank->bank_num == 0) { 1823 if (RV1126_GPIO_C4_D7(pin_num)) { 1824 *regmap = priv->regmap_base; 1825 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1826 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 1827 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1828 *bit *= RV1126_DRV_BITS_PER_PIN; 1829 return; 1830 } 1831 *regmap = priv->regmap_pmu; 1832 *reg = RV1126_DRV_PMU_OFFSET; 1833 } else { 1834 *regmap = priv->regmap_base; 1835 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1836 *reg += bank->bank_num * RV1126_DRV_BANK_STRIDE; 1837 } 1838 1839 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 1840 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1841 *bit *= RV1126_DRV_BITS_PER_PIN; 1842 } 1843 1844 #define RV1126_SCHMITT_PMU_OFFSET 0x60 1845 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 1846 #define RV1126_SCHMITT_BANK_STRIDE 16 1847 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8 1848 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8 1849 1850 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1851 int pin_num, 1852 struct regmap **regmap, 1853 int *reg, u8 *bit) 1854 { 1855 struct rockchip_pinctrl_priv *priv = bank->priv; 1856 int pins_per_reg; 1857 1858 if (bank->bank_num == 0) { 1859 if (RV1126_GPIO_C4_D7(pin_num)) { 1860 *regmap = priv->regmap_base; 1861 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1862 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 1863 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 1864 return 0; 1865 } 1866 *regmap = priv->regmap_pmu; 1867 *reg = RV1126_SCHMITT_PMU_OFFSET; 1868 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 1869 } else { 1870 *regmap = priv->regmap_base; 1871 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1872 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 1873 *reg += bank->bank_num * RV1126_SCHMITT_BANK_STRIDE; 1874 } 1875 *reg += ((pin_num / pins_per_reg) * 4); 1876 *bit = pin_num % pins_per_reg; 1877 1878 return 0; 1879 } 1880 1881 #define RK1808_PULL_PMU_OFFSET 0x10 1882 #define RK1808_PULL_GRF_OFFSET 0x80 1883 #define RK1808_PULL_PINS_PER_REG 8 1884 #define RK1808_PULL_BITS_PER_PIN 2 1885 #define RK1808_PULL_BANK_STRIDE 16 1886 1887 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1888 int pin_num, 1889 struct regmap **regmap, 1890 int *reg, u8 *bit) 1891 { 1892 struct rockchip_pinctrl_priv *priv = bank->priv; 1893 1894 if (bank->bank_num == 0) { 1895 *regmap = priv->regmap_pmu; 1896 *reg = RK1808_PULL_PMU_OFFSET; 1897 } else { 1898 *reg = RK1808_PULL_GRF_OFFSET; 1899 *regmap = priv->regmap_base; 1900 } 1901 1902 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4); 1903 *bit = (pin_num % RK1808_PULL_PINS_PER_REG); 1904 *bit *= RK1808_PULL_BITS_PER_PIN; 1905 } 1906 1907 #define RK1808_DRV_PMU_OFFSET 0x20 1908 #define RK1808_DRV_GRF_OFFSET 0x140 1909 #define RK1808_DRV_BITS_PER_PIN 2 1910 #define RK1808_DRV_PINS_PER_REG 8 1911 #define RK1808_DRV_BANK_STRIDE 16 1912 1913 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1914 int pin_num, 1915 struct regmap **regmap, 1916 int *reg, u8 *bit) 1917 { 1918 struct rockchip_pinctrl_priv *priv = bank->priv; 1919 1920 if (bank->bank_num == 0) { 1921 *regmap = priv->regmap_pmu; 1922 *reg = RK1808_DRV_PMU_OFFSET; 1923 } else { 1924 *regmap = priv->regmap_base; 1925 *reg = RK1808_DRV_GRF_OFFSET; 1926 } 1927 1928 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4); 1929 *bit = pin_num % RK1808_DRV_PINS_PER_REG; 1930 *bit *= RK1808_DRV_BITS_PER_PIN; 1931 } 1932 1933 #define RK1808_SCHMITT_PMU_OFFSET 0x0040 1934 #define RK1808_SCHMITT_GRF_OFFSET 0x0100 1935 #define RK1808_SCHMITT_BANK_STRIDE 16 1936 #define RK1808_SCHMITT_PINS_PER_REG 8 1937 1938 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1939 int pin_num, 1940 struct regmap **regmap, 1941 int *reg, u8 *bit) 1942 { 1943 struct rockchip_pinctrl_priv *priv = bank->priv; 1944 1945 if (bank->bank_num == 0) { 1946 *regmap = priv->regmap_pmu; 1947 *reg = RK1808_SCHMITT_PMU_OFFSET; 1948 } else { 1949 *regmap = priv->regmap_base; 1950 *reg = RK1808_SCHMITT_GRF_OFFSET; 1951 *reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE; 1952 } 1953 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4); 1954 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG; 1955 1956 return 0; 1957 } 1958 1959 #define RK2928_PULL_OFFSET 0x118 1960 #define RK2928_PULL_PINS_PER_REG 16 1961 #define RK2928_PULL_BANK_STRIDE 8 1962 1963 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1964 int pin_num, struct regmap **regmap, 1965 int *reg, u8 *bit) 1966 { 1967 struct rockchip_pinctrl_priv *priv = bank->priv; 1968 1969 *regmap = priv->regmap_base; 1970 *reg = RK2928_PULL_OFFSET; 1971 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1972 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1973 1974 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1975 }; 1976 1977 #define RK3128_PULL_OFFSET 0x118 1978 1979 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1980 int pin_num, struct regmap **regmap, 1981 int *reg, u8 *bit) 1982 { 1983 struct rockchip_pinctrl_priv *priv = bank->priv; 1984 1985 *regmap = priv->regmap_base; 1986 *reg = RK3128_PULL_OFFSET; 1987 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1988 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1989 1990 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1991 } 1992 1993 #define RK3188_PULL_OFFSET 0x164 1994 #define RK3188_PULL_BITS_PER_PIN 2 1995 #define RK3188_PULL_PINS_PER_REG 8 1996 #define RK3188_PULL_BANK_STRIDE 16 1997 #define RK3188_PULL_PMU_OFFSET 0x64 1998 1999 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2000 int pin_num, struct regmap **regmap, 2001 int *reg, u8 *bit) 2002 { 2003 struct rockchip_pinctrl_priv *priv = bank->priv; 2004 2005 /* The first 12 pins of the first bank are located elsewhere */ 2006 if (bank->bank_num == 0 && pin_num < 12) { 2007 *regmap = priv->regmap_pmu; 2008 *reg = RK3188_PULL_PMU_OFFSET; 2009 2010 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2011 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2012 *bit *= RK3188_PULL_BITS_PER_PIN; 2013 } else { 2014 *regmap = priv->regmap_base; 2015 *reg = RK3188_PULL_OFFSET; 2016 2017 /* correct the offset, as it is the 2nd pull register */ 2018 *reg -= 4; 2019 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2020 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2021 2022 /* 2023 * The bits in these registers have an inverse ordering 2024 * with the lowest pin being in bits 15:14 and the highest 2025 * pin in bits 1:0 2026 */ 2027 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 2028 *bit *= RK3188_PULL_BITS_PER_PIN; 2029 } 2030 } 2031 2032 #define RK3288_PULL_OFFSET 0x140 2033 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2034 int pin_num, struct regmap **regmap, 2035 int *reg, u8 *bit) 2036 { 2037 struct rockchip_pinctrl_priv *priv = bank->priv; 2038 2039 /* The first 24 pins of the first bank are located in PMU */ 2040 if (bank->bank_num == 0) { 2041 *regmap = priv->regmap_pmu; 2042 *reg = RK3188_PULL_PMU_OFFSET; 2043 2044 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2045 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2046 *bit *= RK3188_PULL_BITS_PER_PIN; 2047 } else { 2048 *regmap = priv->regmap_base; 2049 *reg = RK3288_PULL_OFFSET; 2050 2051 /* correct the offset, as we're starting with the 2nd bank */ 2052 *reg -= 0x10; 2053 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2054 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2055 2056 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2057 *bit *= RK3188_PULL_BITS_PER_PIN; 2058 } 2059 } 2060 2061 #define RK3288_DRV_PMU_OFFSET 0x70 2062 #define RK3288_DRV_GRF_OFFSET 0x1c0 2063 #define RK3288_DRV_BITS_PER_PIN 2 2064 #define RK3288_DRV_PINS_PER_REG 8 2065 #define RK3288_DRV_BANK_STRIDE 16 2066 2067 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2068 int pin_num, struct regmap **regmap, 2069 int *reg, u8 *bit) 2070 { 2071 struct rockchip_pinctrl_priv *priv = bank->priv; 2072 2073 /* The first 24 pins of the first bank are located in PMU */ 2074 if (bank->bank_num == 0) { 2075 *regmap = priv->regmap_pmu; 2076 *reg = RK3288_DRV_PMU_OFFSET; 2077 2078 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2079 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2080 *bit *= RK3288_DRV_BITS_PER_PIN; 2081 } else { 2082 *regmap = priv->regmap_base; 2083 *reg = RK3288_DRV_GRF_OFFSET; 2084 2085 /* correct the offset, as we're starting with the 2nd bank */ 2086 *reg -= 0x10; 2087 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2088 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2089 2090 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2091 *bit *= RK3288_DRV_BITS_PER_PIN; 2092 } 2093 } 2094 2095 #define RK3228_PULL_OFFSET 0x100 2096 2097 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2098 int pin_num, struct regmap **regmap, 2099 int *reg, u8 *bit) 2100 { 2101 struct rockchip_pinctrl_priv *priv = bank->priv; 2102 2103 *regmap = priv->regmap_base; 2104 *reg = RK3228_PULL_OFFSET; 2105 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2106 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2107 2108 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2109 *bit *= RK3188_PULL_BITS_PER_PIN; 2110 } 2111 2112 #define RK3228_DRV_GRF_OFFSET 0x200 2113 2114 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2115 int pin_num, struct regmap **regmap, 2116 int *reg, u8 *bit) 2117 { 2118 struct rockchip_pinctrl_priv *priv = bank->priv; 2119 2120 *regmap = priv->regmap_base; 2121 *reg = RK3228_DRV_GRF_OFFSET; 2122 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2123 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2124 2125 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2126 *bit *= RK3288_DRV_BITS_PER_PIN; 2127 } 2128 2129 #define RK3308_PULL_OFFSET 0xa0 2130 2131 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2132 int pin_num, struct regmap **regmap, 2133 int *reg, u8 *bit) 2134 { 2135 struct rockchip_pinctrl_priv *priv = bank->priv; 2136 2137 *regmap = priv->regmap_base; 2138 *reg = RK3308_PULL_OFFSET; 2139 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2140 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2141 2142 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2143 *bit *= RK3188_PULL_BITS_PER_PIN; 2144 } 2145 2146 #define RK3308_DRV_GRF_OFFSET 0x100 2147 2148 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2149 int pin_num, struct regmap **regmap, 2150 int *reg, u8 *bit) 2151 { 2152 struct rockchip_pinctrl_priv *priv = bank->priv; 2153 2154 *regmap = priv->regmap_base; 2155 *reg = RK3308_DRV_GRF_OFFSET; 2156 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2157 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2158 2159 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2160 *bit *= RK3288_DRV_BITS_PER_PIN; 2161 } 2162 2163 #define RK3308_SCHMITT_PINS_PER_REG 8 2164 #define RK3308_SCHMITT_BANK_STRIDE 16 2165 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 2166 2167 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2168 int pin_num, 2169 struct regmap **regmap, 2170 int *reg, u8 *bit) 2171 { 2172 struct rockchip_pinctrl_priv *priv = bank->priv; 2173 2174 *regmap = priv->regmap_base; 2175 *reg = RK3308_SCHMITT_GRF_OFFSET; 2176 2177 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 2178 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 2179 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 2180 2181 return 0; 2182 } 2183 2184 #define RK3368_PULL_GRF_OFFSET 0x100 2185 #define RK3368_PULL_PMU_OFFSET 0x10 2186 2187 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2188 int pin_num, struct regmap **regmap, 2189 int *reg, u8 *bit) 2190 { 2191 struct rockchip_pinctrl_priv *priv = bank->priv; 2192 2193 /* The first 32 pins of the first bank are located in PMU */ 2194 if (bank->bank_num == 0) { 2195 *regmap = priv->regmap_pmu; 2196 *reg = RK3368_PULL_PMU_OFFSET; 2197 2198 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2199 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2200 *bit *= RK3188_PULL_BITS_PER_PIN; 2201 } else { 2202 *regmap = priv->regmap_base; 2203 *reg = RK3368_PULL_GRF_OFFSET; 2204 2205 /* correct the offset, as we're starting with the 2nd bank */ 2206 *reg -= 0x10; 2207 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2208 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2209 2210 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2211 *bit *= RK3188_PULL_BITS_PER_PIN; 2212 } 2213 } 2214 2215 #define RK3368_DRV_PMU_OFFSET 0x20 2216 #define RK3368_DRV_GRF_OFFSET 0x200 2217 2218 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2219 int pin_num, struct regmap **regmap, 2220 int *reg, u8 *bit) 2221 { 2222 struct rockchip_pinctrl_priv *priv = bank->priv; 2223 2224 /* The first 32 pins of the first bank are located in PMU */ 2225 if (bank->bank_num == 0) { 2226 *regmap = priv->regmap_pmu; 2227 *reg = RK3368_DRV_PMU_OFFSET; 2228 2229 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2230 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2231 *bit *= RK3288_DRV_BITS_PER_PIN; 2232 } else { 2233 *regmap = priv->regmap_base; 2234 *reg = RK3368_DRV_GRF_OFFSET; 2235 2236 /* correct the offset, as we're starting with the 2nd bank */ 2237 *reg -= 0x10; 2238 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2239 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2240 2241 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2242 *bit *= RK3288_DRV_BITS_PER_PIN; 2243 } 2244 } 2245 2246 #define RK3399_PULL_GRF_OFFSET 0xe040 2247 #define RK3399_PULL_PMU_OFFSET 0x40 2248 #define RK3399_DRV_3BITS_PER_PIN 3 2249 2250 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2251 int pin_num, struct regmap **regmap, 2252 int *reg, u8 *bit) 2253 { 2254 struct rockchip_pinctrl_priv *priv = bank->priv; 2255 2256 /* The bank0:16 and bank1:32 pins are located in PMU */ 2257 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2258 *regmap = priv->regmap_pmu; 2259 *reg = RK3399_PULL_PMU_OFFSET; 2260 2261 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2262 2263 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2264 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2265 *bit *= RK3188_PULL_BITS_PER_PIN; 2266 } else { 2267 *regmap = priv->regmap_base; 2268 *reg = RK3399_PULL_GRF_OFFSET; 2269 2270 /* correct the offset, as we're starting with the 3rd bank */ 2271 *reg -= 0x20; 2272 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2273 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2274 2275 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2276 *bit *= RK3188_PULL_BITS_PER_PIN; 2277 } 2278 } 2279 2280 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2281 int pin_num, struct regmap **regmap, 2282 int *reg, u8 *bit) 2283 { 2284 struct rockchip_pinctrl_priv *priv = bank->priv; 2285 int drv_num = (pin_num / 8); 2286 2287 /* The bank0:16 and bank1:32 pins are located in PMU */ 2288 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2289 *regmap = priv->regmap_pmu; 2290 else 2291 *regmap = priv->regmap_base; 2292 2293 *reg = bank->drv[drv_num].offset; 2294 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2295 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2296 *bit = (pin_num % 8) * 3; 2297 else 2298 *bit = (pin_num % 8) * 2; 2299 } 2300 2301 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2302 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2303 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2304 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2305 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2306 { 4, 7, 10, 13, 16, 19, 22, 26 } 2307 }; 2308 2309 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2310 int pin_num, int strength) 2311 { 2312 struct rockchip_pinctrl_priv *priv = bank->priv; 2313 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2314 struct regmap *regmap; 2315 int reg, ret, i; 2316 u32 data, rmask_bits, temp; 2317 u8 bit; 2318 /* Where need to clean the special mask for rockchip_perpin_drv_list */ 2319 int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); 2320 2321 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 2322 pin_num, strength); 2323 2324 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2325 2326 ret = -EINVAL; 2327 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2328 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2329 ret = i; 2330 break; 2331 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2332 ret = rockchip_perpin_drv_list[drv_type][i]; 2333 break; 2334 } 2335 } 2336 2337 if (ret < 0) { 2338 debug("unsupported driver strength %d\n", strength); 2339 return ret; 2340 } 2341 2342 switch (drv_type) { 2343 case DRV_TYPE_IO_1V8_3V0_AUTO: 2344 case DRV_TYPE_IO_3V3_ONLY: 2345 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2346 switch (bit) { 2347 case 0 ... 12: 2348 /* regular case, nothing to do */ 2349 break; 2350 case 15: 2351 /* 2352 * drive-strength offset is special, as it is spread 2353 * over 2 registers, the bit data[15] contains bit 0 2354 * of the value while temp[1:0] contains bits 2 and 1 2355 */ 2356 data = (ret & 0x1) << 15; 2357 temp = (ret >> 0x1) & 0x3; 2358 2359 data |= BIT(31); 2360 ret = regmap_write(regmap, reg, data); 2361 if (ret) 2362 return ret; 2363 2364 temp |= (0x3 << 16); 2365 reg += 0x4; 2366 ret = regmap_write(regmap, reg, temp); 2367 2368 return ret; 2369 case 18 ... 21: 2370 /* setting fully enclosed in the second register */ 2371 reg += 4; 2372 bit -= 16; 2373 break; 2374 default: 2375 debug("unsupported bit: %d for pinctrl drive type: %d\n", 2376 bit, drv_type); 2377 return -EINVAL; 2378 } 2379 break; 2380 case DRV_TYPE_IO_DEFAULT: 2381 case DRV_TYPE_IO_1V8_OR_3V0: 2382 case DRV_TYPE_IO_1V8_ONLY: 2383 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2384 break; 2385 default: 2386 debug("unsupported pinctrl drive type: %d\n", 2387 drv_type); 2388 return -EINVAL; 2389 } 2390 2391 if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { 2392 regmap_read(regmap, reg, &data); 2393 data &= ~(((1 << rmask_bits) - 1) << bit); 2394 } else { 2395 /* enable the write to the equivalent lower bits */ 2396 data = ((1 << rmask_bits) - 1) << (bit + 16); 2397 } 2398 2399 data |= (ret << bit); 2400 ret = regmap_write(regmap, reg, data); 2401 return ret; 2402 } 2403 2404 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2405 { 2406 PIN_CONFIG_BIAS_DISABLE, 2407 PIN_CONFIG_BIAS_PULL_UP, 2408 PIN_CONFIG_BIAS_PULL_DOWN, 2409 PIN_CONFIG_BIAS_BUS_HOLD 2410 }, 2411 { 2412 PIN_CONFIG_BIAS_DISABLE, 2413 PIN_CONFIG_BIAS_PULL_DOWN, 2414 PIN_CONFIG_BIAS_DISABLE, 2415 PIN_CONFIG_BIAS_PULL_UP 2416 }, 2417 }; 2418 2419 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2420 int pin_num, int pull) 2421 { 2422 struct rockchip_pinctrl_priv *priv = bank->priv; 2423 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2424 struct regmap *regmap; 2425 int reg, ret, i, pull_type; 2426 u8 bit; 2427 u32 data; 2428 2429 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 2430 pin_num, pull); 2431 2432 /* rk3066b does support any pulls */ 2433 if (ctrl->type == RK3066B) 2434 return pull ? -EINVAL : 0; 2435 2436 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2437 2438 switch (ctrl->type) { 2439 case RK2928: 2440 case RK3128: 2441 data = BIT(bit + 16); 2442 if (pull == PIN_CONFIG_BIAS_DISABLE) 2443 data |= BIT(bit); 2444 ret = regmap_write(regmap, reg, data); 2445 break; 2446 case PX30: 2447 case RV1108: 2448 case RV1126: 2449 case RK1808: 2450 case RK3188: 2451 case RK3288: 2452 case RK3308: 2453 case RK3368: 2454 case RK3399: 2455 /* 2456 * Where need to clean the special mask for 2457 * rockchip_pull_list. 2458 */ 2459 pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); 2460 ret = -EINVAL; 2461 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2462 i++) { 2463 if (rockchip_pull_list[pull_type][i] == pull) { 2464 ret = i; 2465 break; 2466 } 2467 } 2468 2469 if (ret < 0) { 2470 debug("unsupported pull setting %d\n", pull); 2471 return ret; 2472 } 2473 2474 if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { 2475 regmap_read(regmap, reg, &data); 2476 data &= ~(((1 << RK3188_PULL_BITS_PER_PIN) - 1) << bit); 2477 } else { 2478 /* enable the write to the equivalent lower bits */ 2479 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2480 } 2481 2482 data |= (ret << bit); 2483 ret = regmap_write(regmap, reg, data); 2484 break; 2485 default: 2486 debug("unsupported pinctrl type\n"); 2487 return -EINVAL; 2488 } 2489 2490 return ret; 2491 } 2492 2493 #define RK3328_SCHMITT_BITS_PER_PIN 1 2494 #define RK3328_SCHMITT_PINS_PER_REG 16 2495 #define RK3328_SCHMITT_BANK_STRIDE 8 2496 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2497 2498 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2499 int pin_num, 2500 struct regmap **regmap, 2501 int *reg, u8 *bit) 2502 { 2503 struct rockchip_pinctrl_priv *priv = bank->priv; 2504 2505 *regmap = priv->regmap_base; 2506 *reg = RK3328_SCHMITT_GRF_OFFSET; 2507 2508 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2509 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2510 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2511 2512 return 0; 2513 } 2514 2515 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2516 int pin_num, int enable) 2517 { 2518 struct rockchip_pinctrl_priv *priv = bank->priv; 2519 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2520 struct regmap *regmap; 2521 int reg, ret; 2522 u8 bit; 2523 u32 data; 2524 2525 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 2526 pin_num, enable); 2527 2528 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2529 if (ret) 2530 return ret; 2531 2532 /* enable the write to the equivalent lower bits */ 2533 data = BIT(bit + 16) | (enable << bit); 2534 2535 return regmap_write(regmap, reg, data); 2536 } 2537 2538 #define PX30_SLEW_RATE_PMU_OFFSET 0x30 2539 #define PX30_SLEW_RATE_GRF_OFFSET 0x90 2540 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16 2541 #define PX30_SLEW_RATE_BANK_STRIDE 16 2542 #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8 2543 2544 static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, 2545 int pin_num, 2546 struct regmap **regmap, 2547 int *reg, u8 *bit) 2548 { 2549 struct rockchip_pinctrl_priv *priv = bank->priv; 2550 int pins_per_reg; 2551 2552 if (bank->bank_num == 0) { 2553 *regmap = priv->regmap_pmu; 2554 *reg = PX30_SLEW_RATE_PMU_OFFSET; 2555 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 2556 } else { 2557 *regmap = priv->regmap_base; 2558 *reg = PX30_SCHMITT_GRF_OFFSET; 2559 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 2560 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 2561 } 2562 *reg += ((pin_num / pins_per_reg) * 4); 2563 *bit = pin_num % pins_per_reg; 2564 2565 return 0; 2566 } 2567 2568 static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank, 2569 int pin_num, int speed) 2570 { 2571 struct rockchip_pinctrl_priv *priv = bank->priv; 2572 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2573 struct regmap *regmap; 2574 int reg, ret; 2575 u8 bit; 2576 u32 data; 2577 2578 debug("setting slew rate of GPIO%d-%d to %d\n", bank->bank_num, 2579 pin_num, speed); 2580 2581 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit); 2582 if (ret) 2583 return ret; 2584 2585 /* enable the write to the equivalent lower bits */ 2586 data = BIT(bit + 16) | (speed << bit); 2587 2588 return regmap_write(regmap, reg, data); 2589 } 2590 2591 /* 2592 * Pinconf_ops handling 2593 */ 2594 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2595 unsigned int pull) 2596 { 2597 switch (ctrl->type) { 2598 case RK2928: 2599 case RK3128: 2600 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2601 pull == PIN_CONFIG_BIAS_DISABLE); 2602 case RK3066B: 2603 return pull ? false : true; 2604 case PX30: 2605 case RV1108: 2606 case RV1126: 2607 case RK1808: 2608 case RK3188: 2609 case RK3288: 2610 case RK3308: 2611 case RK3368: 2612 case RK3399: 2613 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2614 } 2615 2616 return false; 2617 } 2618 2619 /* set the pin config settings for a specified pin */ 2620 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 2621 u32 pin, u32 param, u32 arg) 2622 { 2623 struct rockchip_pinctrl_priv *priv = bank->priv; 2624 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2625 int rc; 2626 2627 switch (param) { 2628 case PIN_CONFIG_BIAS_DISABLE: 2629 rc = rockchip_set_pull(bank, pin, param); 2630 if (rc) 2631 return rc; 2632 break; 2633 2634 case PIN_CONFIG_BIAS_PULL_UP: 2635 case PIN_CONFIG_BIAS_PULL_DOWN: 2636 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2637 case PIN_CONFIG_BIAS_BUS_HOLD: 2638 if (!rockchip_pinconf_pull_valid(ctrl, param)) 2639 return -ENOTSUPP; 2640 2641 if (!arg) 2642 return -EINVAL; 2643 2644 rc = rockchip_set_pull(bank, pin, param); 2645 if (rc) 2646 return rc; 2647 break; 2648 2649 case PIN_CONFIG_DRIVE_STRENGTH: 2650 if (!ctrl->drv_calc_reg) 2651 return -ENOTSUPP; 2652 2653 rc = rockchip_set_drive_perpin(bank, pin, arg); 2654 if (rc < 0) 2655 return rc; 2656 break; 2657 2658 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2659 if (!ctrl->schmitt_calc_reg) 2660 return -ENOTSUPP; 2661 2662 rc = rockchip_set_schmitt(bank, pin, arg); 2663 if (rc < 0) 2664 return rc; 2665 break; 2666 2667 case PIN_CONFIG_SLEW_RATE: 2668 if (!ctrl->slew_rate_calc_reg) 2669 return -ENOTSUPP; 2670 2671 rc = rockchip_set_slew_rate(bank, 2672 pin - bank->pin_base, arg); 2673 if (rc < 0) 2674 return rc; 2675 break; 2676 2677 default: 2678 break; 2679 } 2680 2681 return 0; 2682 } 2683 2684 static const struct pinconf_param rockchip_conf_params[] = { 2685 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 2686 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 2687 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 2688 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 2689 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 2690 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 2691 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 2692 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 2693 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 2694 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, 2695 }; 2696 2697 static int rockchip_pinconf_prop_name_to_param(const char *property, 2698 u32 *default_value) 2699 { 2700 const struct pinconf_param *p, *end; 2701 2702 p = rockchip_conf_params; 2703 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 2704 2705 /* See if this pctldev supports this parameter */ 2706 for (; p < end; p++) { 2707 if (!strcmp(property, p->property)) { 2708 *default_value = p->default_value; 2709 return p->param; 2710 } 2711 } 2712 2713 *default_value = 0; 2714 return -EPERM; 2715 } 2716 2717 static int rockchip_pinctrl_set_state(struct udevice *dev, 2718 struct udevice *config) 2719 { 2720 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2721 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 2722 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 2723 u32 bank, pin, mux, conf, arg, default_val; 2724 int ret, count, i; 2725 const char *prop_name; 2726 const void *value; 2727 int prop_len, param; 2728 const u32 *data; 2729 ofnode node; 2730 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 2731 const struct device_node *np; 2732 struct property *pp; 2733 #else 2734 int property_offset, pcfg_node; 2735 const void *blob = gd->fdt_blob; 2736 #endif 2737 data = dev_read_prop(config, "rockchip,pins", &count); 2738 if (count < 0) { 2739 debug("%s: bad array size %d\n", __func__, count); 2740 return -EINVAL; 2741 } 2742 2743 count /= sizeof(u32); 2744 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2745 debug("%s: unsupported pins array count %d\n", 2746 __func__, count); 2747 return -EINVAL; 2748 } 2749 2750 for (i = 0; i < count; i++) 2751 cells[i] = fdt32_to_cpu(data[i]); 2752 2753 for (i = 0; i < (count >> 2); i++) { 2754 bank = cells[4 * i + 0]; 2755 pin = cells[4 * i + 1]; 2756 mux = cells[4 * i + 2]; 2757 conf = cells[4 * i + 3]; 2758 2759 ret = rockchip_verify_config(dev, bank, pin); 2760 if (ret) 2761 return ret; 2762 2763 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2764 if (ret) 2765 return ret; 2766 2767 node = ofnode_get_by_phandle(conf); 2768 if (!ofnode_valid(node)) 2769 return -ENODEV; 2770 #if defined(CONFIG_OF_LIVE) && !defined(CONFIG_SPL_BUILD) 2771 np = ofnode_to_np(node); 2772 for (pp = np->properties; pp; pp = pp->next) { 2773 prop_name = pp->name; 2774 prop_len = pp->length; 2775 value = pp->value; 2776 #else 2777 pcfg_node = ofnode_to_offset(node); 2778 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2779 value = fdt_getprop_by_offset(blob, property_offset, 2780 &prop_name, &prop_len); 2781 if (!value) 2782 return -ENOENT; 2783 #endif 2784 param = rockchip_pinconf_prop_name_to_param(prop_name, 2785 &default_val); 2786 if (param < 0) 2787 break; 2788 2789 if (prop_len >= sizeof(fdt32_t)) 2790 arg = fdt32_to_cpu(*(fdt32_t *)value); 2791 else 2792 arg = default_val; 2793 2794 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2795 param, arg); 2796 if (ret) { 2797 debug("%s: rockchip_pinconf_set fail: %d\n", 2798 __func__, ret); 2799 return ret; 2800 } 2801 } 2802 } 2803 2804 return 0; 2805 } 2806 2807 static struct pinctrl_ops rockchip_pinctrl_ops = { 2808 .set_state = rockchip_pinctrl_set_state, 2809 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2810 }; 2811 2812 /* Ctrl data specially handle */ 2813 static int rk3308b_ctrl_data_re_init(struct rockchip_pin_ctrl *ctrl) 2814 { 2815 /* 2816 * Special for rk3308b, where we need to replace the recalced 2817 * and routed arrays. 2818 */ 2819 if (soc_is_rk3308b()) { 2820 ctrl->iomux_recalced = rk3308b_mux_recalced_data; 2821 ctrl->niomux_recalced = ARRAY_SIZE(rk3308b_mux_recalced_data); 2822 ctrl->iomux_routes = rk3308b_mux_route_data; 2823 ctrl->niomux_routes = ARRAY_SIZE(rk3308b_mux_route_data); 2824 } 2825 2826 return 0; 2827 } 2828 2829 /* retrieve the soc specific data */ 2830 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 2831 { 2832 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2833 struct rockchip_pin_ctrl *ctrl = 2834 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 2835 struct rockchip_pin_bank *bank; 2836 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2837 2838 grf_offs = ctrl->grf_mux_offset; 2839 pmu_offs = ctrl->pmu_mux_offset; 2840 drv_pmu_offs = ctrl->pmu_drv_offset; 2841 drv_grf_offs = ctrl->grf_drv_offset; 2842 bank = ctrl->pin_banks; 2843 2844 /* Ctrl data re-initialize for some Socs */ 2845 if (ctrl->ctrl_data_re_init) { 2846 if (ctrl->ctrl_data_re_init(ctrl)) 2847 return NULL; 2848 } 2849 2850 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2851 int bank_pins = 0; 2852 2853 bank->priv = priv; 2854 bank->pin_base = ctrl->nr_pins; 2855 ctrl->nr_pins += bank->nr_pins; 2856 2857 /* calculate iomux and drv offsets */ 2858 for (j = 0; j < 4; j++) { 2859 struct rockchip_iomux *iom = &bank->iomux[j]; 2860 struct rockchip_drv *drv = &bank->drv[j]; 2861 int inc; 2862 2863 if (bank_pins >= bank->nr_pins) 2864 break; 2865 2866 /* preset iomux offset value, set new start value */ 2867 if (iom->offset >= 0) { 2868 if (iom->type & IOMUX_SOURCE_PMU) 2869 pmu_offs = iom->offset; 2870 else 2871 grf_offs = iom->offset; 2872 } else { /* set current iomux offset */ 2873 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2874 pmu_offs : grf_offs; 2875 } 2876 2877 /* preset drv offset value, set new start value */ 2878 if (drv->offset >= 0) { 2879 if (iom->type & IOMUX_SOURCE_PMU) 2880 drv_pmu_offs = drv->offset; 2881 else 2882 drv_grf_offs = drv->offset; 2883 } else { /* set current drv offset */ 2884 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2885 drv_pmu_offs : drv_grf_offs; 2886 } 2887 2888 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2889 i, j, iom->offset, drv->offset); 2890 2891 /* 2892 * Increase offset according to iomux width. 2893 * 4bit iomux'es are spread over two registers. 2894 */ 2895 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2896 IOMUX_WIDTH_3BIT | 2897 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 2898 if (iom->type & IOMUX_SOURCE_PMU) 2899 pmu_offs += inc; 2900 else 2901 grf_offs += inc; 2902 2903 /* 2904 * Increase offset according to drv width. 2905 * 3bit drive-strenth'es are spread over two registers. 2906 */ 2907 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2908 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2909 inc = 8; 2910 else 2911 inc = 4; 2912 2913 if (iom->type & IOMUX_SOURCE_PMU) 2914 drv_pmu_offs += inc; 2915 else 2916 drv_grf_offs += inc; 2917 2918 bank_pins += 8; 2919 } 2920 2921 /* calculate the per-bank recalced_mask */ 2922 for (j = 0; j < ctrl->niomux_recalced; j++) { 2923 int pin = 0; 2924 2925 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2926 pin = ctrl->iomux_recalced[j].pin; 2927 bank->recalced_mask |= BIT(pin); 2928 } 2929 } 2930 2931 /* calculate the per-bank route_mask */ 2932 for (j = 0; j < ctrl->niomux_routes; j++) { 2933 int pin = 0; 2934 2935 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2936 pin = ctrl->iomux_routes[j].pin; 2937 bank->route_mask |= BIT(pin); 2938 } 2939 } 2940 } 2941 2942 return ctrl; 2943 } 2944 2945 /* SoC data specially handle */ 2946 2947 /* rk3308b SoC data initialize */ 2948 #define RK3308B_GRF_SOC_CON13 0x608 2949 #define RK3308B_GRF_SOC_CON15 0x610 2950 2951 /* RK3308B_GRF_SOC_CON13 */ 2952 #define RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) 2953 #define RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 2954 #define RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 2955 2956 /* RK3308B_GRF_SOC_CON15 */ 2957 #define RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) 2958 #define RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) 2959 #define RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) 2960 2961 static int rk3308b_soc_data_init(struct rockchip_pinctrl_priv *priv) 2962 { 2963 int ret; 2964 2965 /* 2966 * Enable the special ctrl of selected sources. 2967 */ 2968 if (soc_is_rk3308b()) { 2969 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON13, 2970 RK3308B_GRF_I2C3_IOFUNC_SRC_CTRL | 2971 RK3308B_GRF_GPIO2A3_SEL_SRC_CTRL | 2972 RK3308B_GRF_GPIO2A2_SEL_SRC_CTRL); 2973 if (ret) 2974 return ret; 2975 2976 ret = regmap_write(priv->regmap_base, RK3308B_GRF_SOC_CON15, 2977 RK3308B_GRF_GPIO2C0_SEL_SRC_CTRL | 2978 RK3308B_GRF_GPIO3B3_SEL_SRC_CTRL | 2979 RK3308B_GRF_GPIO3B2_SEL_SRC_CTRL); 2980 if (ret) 2981 return ret; 2982 } 2983 2984 return 0; 2985 } 2986 2987 static int rockchip_pinctrl_probe(struct udevice *dev) 2988 { 2989 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2990 struct rockchip_pin_ctrl *ctrl; 2991 struct udevice *syscon; 2992 struct regmap *regmap; 2993 int ret = 0; 2994 2995 /* get rockchip grf syscon phandle */ 2996 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2997 &syscon); 2998 if (ret) { 2999 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 3000 return ret; 3001 } 3002 3003 /* get grf-reg base address */ 3004 regmap = syscon_get_regmap(syscon); 3005 if (!regmap) { 3006 debug("unable to find rockchip grf regmap\n"); 3007 return -ENODEV; 3008 } 3009 priv->regmap_base = regmap; 3010 3011 /* option: get pmu-reg base address */ 3012 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 3013 &syscon); 3014 if (!ret) { 3015 /* get pmugrf-reg base address */ 3016 regmap = syscon_get_regmap(syscon); 3017 if (!regmap) { 3018 debug("unable to find rockchip pmu regmap\n"); 3019 return -ENODEV; 3020 } 3021 priv->regmap_pmu = regmap; 3022 } 3023 3024 ctrl = rockchip_pinctrl_get_soc_data(dev); 3025 if (!ctrl) { 3026 debug("driver data not available\n"); 3027 return -EINVAL; 3028 } 3029 3030 /* Special handle for some Socs */ 3031 if (ctrl->soc_data_init) { 3032 ret = ctrl->soc_data_init(priv); 3033 if (ret) 3034 return ret; 3035 } 3036 3037 priv->ctrl = ctrl; 3038 return 0; 3039 } 3040 3041 static struct rockchip_pin_bank px30_pin_banks[] = { 3042 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3043 IOMUX_SOURCE_PMU, 3044 IOMUX_SOURCE_PMU, 3045 IOMUX_SOURCE_PMU 3046 ), 3047 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3048 IOMUX_WIDTH_4BIT, 3049 IOMUX_WIDTH_4BIT, 3050 IOMUX_WIDTH_4BIT 3051 ), 3052 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3053 IOMUX_WIDTH_4BIT, 3054 IOMUX_WIDTH_4BIT, 3055 IOMUX_WIDTH_4BIT 3056 ), 3057 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3058 IOMUX_WIDTH_4BIT, 3059 IOMUX_WIDTH_4BIT, 3060 IOMUX_WIDTH_4BIT 3061 ), 3062 }; 3063 3064 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3065 .pin_banks = px30_pin_banks, 3066 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3067 .label = "PX30-GPIO", 3068 .type = PX30, 3069 .grf_mux_offset = 0x0, 3070 .pmu_mux_offset = 0x0, 3071 .iomux_routes = px30_mux_route_data, 3072 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3073 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3074 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3075 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3076 .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit, 3077 }; 3078 3079 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3080 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3081 IOMUX_SOURCE_PMU, 3082 IOMUX_SOURCE_PMU, 3083 IOMUX_SOURCE_PMU), 3084 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3085 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3086 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3087 }; 3088 3089 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3090 .pin_banks = rv1108_pin_banks, 3091 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3092 .label = "RV1108-GPIO", 3093 .type = RV1108, 3094 .grf_mux_offset = 0x10, 3095 .pmu_mux_offset = 0x0, 3096 .iomux_recalced = rv1108_mux_recalced_data, 3097 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3098 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3099 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3100 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3101 }; 3102 3103 static struct rockchip_pin_bank rv1126_pin_banks[] = { 3104 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3105 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3106 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 3107 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 3108 IOMUX_WIDTH_4BIT), 3109 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 3110 IOMUX_WIDTH_4BIT, 3111 IOMUX_WIDTH_4BIT, 3112 IOMUX_WIDTH_4BIT, 3113 IOMUX_WIDTH_4BIT), 3114 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3115 IOMUX_WIDTH_4BIT, 3116 IOMUX_WIDTH_4BIT, 3117 IOMUX_WIDTH_4BIT, 3118 IOMUX_WIDTH_4BIT), 3119 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3120 IOMUX_WIDTH_4BIT, 3121 IOMUX_WIDTH_4BIT, 3122 IOMUX_WIDTH_4BIT, 3123 IOMUX_WIDTH_4BIT), 3124 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 3125 IOMUX_WIDTH_4BIT, 0, 0, 0), 3126 }; 3127 3128 static struct rockchip_pin_ctrl rv1126_pin_ctrl = { 3129 .pin_banks = rv1126_pin_banks, 3130 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 3131 .label = "RV1126-GPIO", 3132 .type = RV1126, 3133 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 3134 .pmu_mux_offset = 0x0, 3135 .iomux_recalced = rv1126_mux_recalced_data, 3136 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 3137 .pull_calc_reg = rv1126_calc_pull_reg_and_bit, 3138 .drv_calc_reg = rv1126_calc_drv_reg_and_bit, 3139 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit, 3140 }; 3141 3142 static struct rockchip_pin_bank rk1808_pin_banks[] = { 3143 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 3144 IOMUX_SOURCE_PMU, 3145 IOMUX_SOURCE_PMU, 3146 IOMUX_SOURCE_PMU, 3147 IOMUX_SOURCE_PMU), 3148 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 3149 IOMUX_WIDTH_4BIT, 3150 IOMUX_WIDTH_4BIT, 3151 IOMUX_WIDTH_4BIT, 3152 IOMUX_WIDTH_4BIT), 3153 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 3154 IOMUX_WIDTH_4BIT, 3155 IOMUX_WIDTH_4BIT, 3156 IOMUX_WIDTH_4BIT, 3157 IOMUX_WIDTH_4BIT), 3158 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3159 IOMUX_WIDTH_4BIT, 3160 IOMUX_WIDTH_4BIT, 3161 IOMUX_WIDTH_4BIT, 3162 IOMUX_WIDTH_4BIT), 3163 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", 3164 IOMUX_WIDTH_4BIT, 3165 IOMUX_WIDTH_4BIT, 3166 IOMUX_WIDTH_4BIT, 3167 IOMUX_WIDTH_4BIT), 3168 }; 3169 3170 static struct rockchip_pin_ctrl rk1808_pin_ctrl = { 3171 .pin_banks = rk1808_pin_banks, 3172 .nr_banks = ARRAY_SIZE(rk1808_pin_banks), 3173 .label = "RK1808-GPIO", 3174 .type = RK1808, 3175 .iomux_routes = rk1808_mux_route_data, 3176 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data), 3177 .grf_mux_offset = 0x0, 3178 .pmu_mux_offset = 0x0, 3179 .pull_calc_reg = rk1808_calc_pull_reg_and_bit, 3180 .drv_calc_reg = rk1808_calc_drv_reg_and_bit, 3181 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit, 3182 }; 3183 3184 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3185 PIN_BANK(0, 32, "gpio0"), 3186 PIN_BANK(1, 32, "gpio1"), 3187 PIN_BANK(2, 32, "gpio2"), 3188 PIN_BANK(3, 32, "gpio3"), 3189 }; 3190 3191 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3192 .pin_banks = rk2928_pin_banks, 3193 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3194 .label = "RK2928-GPIO", 3195 .type = RK2928, 3196 .grf_mux_offset = 0xa8, 3197 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3198 }; 3199 3200 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3201 PIN_BANK(0, 32, "gpio0"), 3202 PIN_BANK(1, 32, "gpio1"), 3203 PIN_BANK(2, 32, "gpio2"), 3204 }; 3205 3206 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3207 .pin_banks = rk3036_pin_banks, 3208 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3209 .label = "RK3036-GPIO", 3210 .type = RK2928, 3211 .grf_mux_offset = 0xa8, 3212 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3213 }; 3214 3215 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3216 PIN_BANK(0, 32, "gpio0"), 3217 PIN_BANK(1, 32, "gpio1"), 3218 PIN_BANK(2, 32, "gpio2"), 3219 PIN_BANK(3, 32, "gpio3"), 3220 PIN_BANK(4, 32, "gpio4"), 3221 PIN_BANK(6, 16, "gpio6"), 3222 }; 3223 3224 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3225 .pin_banks = rk3066a_pin_banks, 3226 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3227 .label = "RK3066a-GPIO", 3228 .type = RK2928, 3229 .grf_mux_offset = 0xa8, 3230 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3231 }; 3232 3233 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3234 PIN_BANK(0, 32, "gpio0"), 3235 PIN_BANK(1, 32, "gpio1"), 3236 PIN_BANK(2, 32, "gpio2"), 3237 PIN_BANK(3, 32, "gpio3"), 3238 }; 3239 3240 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3241 .pin_banks = rk3066b_pin_banks, 3242 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3243 .label = "RK3066b-GPIO", 3244 .type = RK3066B, 3245 .grf_mux_offset = 0x60, 3246 }; 3247 3248 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3249 PIN_BANK(0, 32, "gpio0"), 3250 PIN_BANK(1, 32, "gpio1"), 3251 PIN_BANK(2, 32, "gpio2"), 3252 PIN_BANK(3, 32, "gpio3"), 3253 }; 3254 3255 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3256 .pin_banks = rk3128_pin_banks, 3257 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3258 .label = "RK3128-GPIO", 3259 .type = RK3128, 3260 .grf_mux_offset = 0xa8, 3261 .iomux_recalced = rk3128_mux_recalced_data, 3262 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3263 .iomux_routes = rk3128_mux_route_data, 3264 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3265 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3266 }; 3267 3268 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3269 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3270 PIN_BANK(1, 32, "gpio1"), 3271 PIN_BANK(2, 32, "gpio2"), 3272 PIN_BANK(3, 32, "gpio3"), 3273 }; 3274 3275 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3276 .pin_banks = rk3188_pin_banks, 3277 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3278 .label = "RK3188-GPIO", 3279 .type = RK3188, 3280 .grf_mux_offset = 0x60, 3281 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3282 }; 3283 3284 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3285 PIN_BANK(0, 32, "gpio0"), 3286 PIN_BANK(1, 32, "gpio1"), 3287 PIN_BANK(2, 32, "gpio2"), 3288 PIN_BANK(3, 32, "gpio3"), 3289 }; 3290 3291 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3292 .pin_banks = rk3228_pin_banks, 3293 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 3294 .label = "RK3228-GPIO", 3295 .type = RK3288, 3296 .grf_mux_offset = 0x0, 3297 .iomux_routes = rk3228_mux_route_data, 3298 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 3299 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3300 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3301 }; 3302 3303 static struct rockchip_pin_bank rk3288_pin_banks[] = { 3304 PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", 3305 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3306 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3307 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, 3308 IOMUX_UNROUTED, 3309 DRV_TYPE_WRITABLE_32BIT, 3310 DRV_TYPE_WRITABLE_32BIT, 3311 DRV_TYPE_WRITABLE_32BIT, 3312 0, 3313 PULL_TYPE_WRITABLE_32BIT, 3314 PULL_TYPE_WRITABLE_32BIT, 3315 PULL_TYPE_WRITABLE_32BIT, 3316 0 3317 ), 3318 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 3319 IOMUX_UNROUTED, 3320 IOMUX_UNROUTED, 3321 0 3322 ), 3323 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 3324 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 3325 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 3326 IOMUX_WIDTH_4BIT, 3327 0, 3328 0 3329 ), 3330 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 3331 0, 3332 0, 3333 IOMUX_UNROUTED 3334 ), 3335 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 3336 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 3337 0, 3338 IOMUX_WIDTH_4BIT, 3339 IOMUX_UNROUTED 3340 ), 3341 PIN_BANK(8, 16, "gpio8"), 3342 }; 3343 3344 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 3345 .pin_banks = rk3288_pin_banks, 3346 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 3347 .label = "RK3288-GPIO", 3348 .type = RK3288, 3349 .grf_mux_offset = 0x0, 3350 .pmu_mux_offset = 0x84, 3351 .iomux_routes = rk3288_mux_route_data, 3352 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 3353 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3354 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3355 }; 3356 3357 static struct rockchip_pin_bank rk3308_pin_banks[] = { 3358 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 3359 IOMUX_8WIDTH_2BIT, 3360 IOMUX_8WIDTH_2BIT, 3361 IOMUX_8WIDTH_2BIT), 3362 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 3363 IOMUX_8WIDTH_2BIT, 3364 IOMUX_8WIDTH_2BIT, 3365 IOMUX_8WIDTH_2BIT), 3366 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 3367 IOMUX_8WIDTH_2BIT, 3368 IOMUX_8WIDTH_2BIT, 3369 IOMUX_8WIDTH_2BIT), 3370 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 3371 IOMUX_8WIDTH_2BIT, 3372 IOMUX_8WIDTH_2BIT, 3373 IOMUX_8WIDTH_2BIT), 3374 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 3375 IOMUX_8WIDTH_2BIT, 3376 IOMUX_8WIDTH_2BIT, 3377 IOMUX_8WIDTH_2BIT), 3378 }; 3379 3380 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 3381 .pin_banks = rk3308_pin_banks, 3382 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 3383 .label = "RK3308-GPIO", 3384 .type = RK3308, 3385 .grf_mux_offset = 0x0, 3386 .iomux_recalced = rk3308_mux_recalced_data, 3387 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 3388 .iomux_routes = rk3308_mux_route_data, 3389 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 3390 .ctrl_data_re_init = rk3308b_ctrl_data_re_init, 3391 .soc_data_init = rk3308b_soc_data_init, 3392 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 3393 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 3394 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 3395 }; 3396 3397 static struct rockchip_pin_bank rk3328_pin_banks[] = { 3398 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 3399 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3400 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 3401 IOMUX_WIDTH_3BIT, 3402 IOMUX_WIDTH_3BIT, 3403 0), 3404 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 3405 IOMUX_WIDTH_3BIT, 3406 IOMUX_WIDTH_3BIT, 3407 0, 3408 0), 3409 }; 3410 3411 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 3412 .pin_banks = rk3328_pin_banks, 3413 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 3414 .label = "RK3328-GPIO", 3415 .type = RK3288, 3416 .grf_mux_offset = 0x0, 3417 .iomux_recalced = rk3328_mux_recalced_data, 3418 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 3419 .iomux_routes = rk3328_mux_route_data, 3420 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 3421 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 3422 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 3423 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 3424 }; 3425 3426 static struct rockchip_pin_bank rk3368_pin_banks[] = { 3427 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3428 IOMUX_SOURCE_PMU, 3429 IOMUX_SOURCE_PMU, 3430 IOMUX_SOURCE_PMU 3431 ), 3432 PIN_BANK(1, 32, "gpio1"), 3433 PIN_BANK(2, 32, "gpio2"), 3434 PIN_BANK(3, 32, "gpio3"), 3435 }; 3436 3437 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 3438 .pin_banks = rk3368_pin_banks, 3439 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 3440 .label = "RK3368-GPIO", 3441 .type = RK3368, 3442 .grf_mux_offset = 0x0, 3443 .pmu_mux_offset = 0x0, 3444 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 3445 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 3446 }; 3447 3448 static struct rockchip_pin_bank rk3399_pin_banks[] = { 3449 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 3450 IOMUX_SOURCE_PMU, 3451 IOMUX_SOURCE_PMU, 3452 IOMUX_SOURCE_PMU, 3453 IOMUX_SOURCE_PMU, 3454 DRV_TYPE_IO_1V8_ONLY, 3455 DRV_TYPE_IO_1V8_ONLY, 3456 DRV_TYPE_IO_DEFAULT, 3457 DRV_TYPE_IO_DEFAULT, 3458 0x80, 3459 0x88, 3460 -1, 3461 -1, 3462 PULL_TYPE_IO_1V8_ONLY, 3463 PULL_TYPE_IO_1V8_ONLY, 3464 PULL_TYPE_IO_DEFAULT, 3465 PULL_TYPE_IO_DEFAULT 3466 ), 3467 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 3468 IOMUX_SOURCE_PMU, 3469 IOMUX_SOURCE_PMU, 3470 IOMUX_SOURCE_PMU, 3471 DRV_TYPE_IO_1V8_OR_3V0, 3472 DRV_TYPE_IO_1V8_OR_3V0, 3473 DRV_TYPE_IO_1V8_OR_3V0, 3474 DRV_TYPE_IO_1V8_OR_3V0, 3475 0xa0, 3476 0xa8, 3477 0xb0, 3478 0xb8 3479 ), 3480 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3481 DRV_TYPE_IO_1V8_OR_3V0, 3482 DRV_TYPE_IO_1V8_ONLY, 3483 DRV_TYPE_IO_1V8_ONLY, 3484 PULL_TYPE_IO_DEFAULT, 3485 PULL_TYPE_IO_DEFAULT, 3486 PULL_TYPE_IO_1V8_ONLY, 3487 PULL_TYPE_IO_1V8_ONLY 3488 ), 3489 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 3490 DRV_TYPE_IO_3V3_ONLY, 3491 DRV_TYPE_IO_3V3_ONLY, 3492 DRV_TYPE_IO_1V8_OR_3V0 3493 ), 3494 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 3495 DRV_TYPE_IO_1V8_3V0_AUTO, 3496 DRV_TYPE_IO_1V8_OR_3V0, 3497 DRV_TYPE_IO_1V8_OR_3V0 3498 ), 3499 }; 3500 3501 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 3502 .pin_banks = rk3399_pin_banks, 3503 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 3504 .label = "RK3399-GPIO", 3505 .type = RK3399, 3506 .grf_mux_offset = 0xe000, 3507 .pmu_mux_offset = 0x0, 3508 .grf_drv_offset = 0xe100, 3509 .pmu_drv_offset = 0x80, 3510 .iomux_routes = rk3399_mux_route_data, 3511 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 3512 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 3513 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 3514 }; 3515 3516 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 3517 { .compatible = "rockchip,px30-pinctrl", 3518 .data = (ulong)&px30_pin_ctrl }, 3519 { .compatible = "rockchip,rv1108-pinctrl", 3520 .data = (ulong)&rv1108_pin_ctrl }, 3521 { .compatible = "rockchip,rv1126-pinctrl", 3522 .data = (ulong)&rv1126_pin_ctrl }, 3523 { .compatible = "rockchip,rk1808-pinctrl", 3524 .data = (ulong)&rk1808_pin_ctrl }, 3525 { .compatible = "rockchip,rk2928-pinctrl", 3526 .data = (ulong)&rk2928_pin_ctrl }, 3527 { .compatible = "rockchip,rk3036-pinctrl", 3528 .data = (ulong)&rk3036_pin_ctrl }, 3529 { .compatible = "rockchip,rk3066a-pinctrl", 3530 .data = (ulong)&rk3066a_pin_ctrl }, 3531 { .compatible = "rockchip,rk3066b-pinctrl", 3532 .data = (ulong)&rk3066b_pin_ctrl }, 3533 { .compatible = "rockchip,rk3128-pinctrl", 3534 .data = (ulong)&rk3128_pin_ctrl }, 3535 { .compatible = "rockchip,rk3188-pinctrl", 3536 .data = (ulong)&rk3188_pin_ctrl }, 3537 { .compatible = "rockchip,rk3228-pinctrl", 3538 .data = (ulong)&rk3228_pin_ctrl }, 3539 { .compatible = "rockchip,rk3288-pinctrl", 3540 .data = (ulong)&rk3288_pin_ctrl }, 3541 { .compatible = "rockchip,rk3308-pinctrl", 3542 .data = (ulong)&rk3308_pin_ctrl }, 3543 { .compatible = "rockchip,rk3328-pinctrl", 3544 .data = (ulong)&rk3328_pin_ctrl }, 3545 { .compatible = "rockchip,rk3368-pinctrl", 3546 .data = (ulong)&rk3368_pin_ctrl }, 3547 { .compatible = "rockchip,rk3399-pinctrl", 3548 .data = (ulong)&rk3399_pin_ctrl }, 3549 {}, 3550 }; 3551 3552 U_BOOT_DRIVER(pinctrl_rockchip) = { 3553 .name = "rockchip_pinctrl", 3554 .id = UCLASS_PINCTRL, 3555 .of_match = rockchip_pinctrl_dt_match, 3556 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 3557 .ops = &rockchip_pinctrl_ops, 3558 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 3559 .bind = dm_scan_fdt_dev, 3560 #endif 3561 .probe = rockchip_pinctrl_probe, 3562 }; 3563