1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &spi_nand, &spi_nor, &nandc, &emmc; 16 }; 17}; 18 19&uart2 { 20 clock-frequency = <24000000>; 21 u-boot,dm-spl; 22}; 23 24&sdmmc { 25 u-boot,dm-spl; 26}; 27 28&emmc { 29 mmc-ecsd = <0x0020f000>; 30 u-boot,dm-spl; 31}; 32 33&pmu { 34 u-boot,dm-spl; 35}; 36 37&pmugrf { 38 u-boot,dm-spl; 39}; 40 41&pmucru { 42 u-boot,dm-spl; 43}; 44 45&cru { 46 u-boot,dm-spl; 47}; 48 49&crypto { 50 u-boot,dm-spl; 51 status = "okay"; 52}; 53 54&grf { 55 u-boot,dm-spl; 56}; 57 58&saradc { 59 u-boot,dm-spl; 60 status = "okay"; 61}; 62 63&sfc { 64 u-boot,dm-spl; 65 status = "okay"; 66 67 #address-cells = <1>; 68 #size-cells = <0>; 69 spi_nand: flash@0 { 70 u-boot,dm-spl; 71 compatible = "spi-nand"; 72 reg = <0>; 73 spi-tx-bus-width = <1>; 74 spi-rx-bus-width = <4>; 75 spi-max-frequency = <96000000>; 76 }; 77 78 spi_nor: flash@1 { 79 u-boot,dm-spl; 80 compatible = "jedec,spi-nor"; 81 reg = <0>; 82 spi-tx-bus-width = <1>; 83 spi-rx-bus-width = <4>; 84 spi-max-frequency = <96000000>; 85 }; 86}; 87 88&nandc { 89 u-boot,dm-spl; 90 status = "okay"; 91 #address-cells = <1>; 92 #size-cells = <0>; 93 94 nand@0 { 95 u-boot,dm-spl; 96 reg = <0>; 97 nand-ecc-mode = "hw_syndrome"; 98 nand-ecc-strength = <16>; 99 nand-ecc-step-size = <1024>; 100 }; 101}; 102 103&hw_decompress { 104 u-boot,dm-spl; 105 status = "okay"; 106}; 107 108&secure_otp { 109 u-boot,dm-spl; 110 status = "okay"; 111}; 112 113&u2phy0 { 114 u-boot,dm-pre-reloc; 115 status = "okay"; 116}; 117 118&u2phy_otg { 119 u-boot,dm-pre-reloc; 120 status = "okay"; 121}; 122 123&usbdrd { 124 u-boot,dm-pre-reloc; 125 status = "okay"; 126}; 127 128&usbdrd_dwc3 { 129 u-boot,dm-pre-reloc; 130 status = "okay"; 131}; 132