1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd. 4 * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 */ 6 7 #ifndef _ASM_ARCH_CRU_RV1126_H 8 #define _ASM_ARCH_CRU_RV1126_H 9 10 #include <common.h> 11 12 #define MHz 1000000 13 #define KHz 1000 14 #define OSC_HZ (24 * MHz) 15 16 #define APLL_HZ (600 * MHz) 17 #define GPLL_HZ (1188 * MHz) 18 #define CPLL_HZ (1000 * MHz) 19 #define HPLL_HZ (1600 * MHz) 20 #define PCLK_PDPMU_HZ (100 * MHz) 21 #define ACLK_PDBUS_HZ (500 * MHz) 22 #define HCLK_PDBUS_HZ (200 * MHz) 23 #define PCLK_PDBUS_HZ (100 * MHz) 24 #define ACLK_PDPHP_HZ (300 * MHz) 25 #define HCLK_PDPHP_HZ (200 * MHz) 26 #define HCLK_PDCORE_HZ (200 * MHz) 27 #define HCLK_PDAUDIO_HZ (150 * MHz) 28 #define CLK_OSC0_DIV_HZ (32768) 29 30 /* RV1126 pll id */ 31 enum rv1126_pll_id { 32 APLL, 33 DPLL, 34 CPLL, 35 HPLL, 36 GPLL, 37 PLL_COUNT, 38 }; 39 40 struct rv1126_clk_info { 41 unsigned long id; 42 char *name; 43 bool is_cru; 44 }; 45 46 /* Private data for the clock driver - used by rockchip_get_cru() */ 47 struct rv1126_pmuclk_priv { 48 struct rv1126_pmucru *pmucru; 49 ulong gpll_hz; 50 }; 51 52 struct rv1126_clk_priv { 53 struct rv1126_cru *cru; 54 struct rv1126_grf *grf; 55 ulong gpll_hz; 56 ulong cpll_hz; 57 ulong hpll_hz; 58 ulong armclk_hz; 59 ulong armclk_enter_hz; 60 ulong armclk_init_hz; 61 bool sync_kernel; 62 bool set_armclk_rate; 63 }; 64 65 struct rv1126_pll { 66 unsigned int con0; 67 unsigned int con1; 68 unsigned int con2; 69 unsigned int con3; 70 unsigned int con4; 71 unsigned int con5; 72 unsigned int con6; 73 unsigned int reserved0[1]; 74 }; 75 76 struct rv1126_pmucru { 77 unsigned int pmu_mode; 78 unsigned int reserved1[3]; 79 struct rv1126_pll pll; 80 unsigned int offsetcal_status; 81 unsigned int reserved2[51]; 82 unsigned int pmu_clksel_con[14]; 83 unsigned int reserved3[18]; 84 unsigned int pmu_clkgate_con[3]; 85 unsigned int reserved4[29]; 86 unsigned int pmu_softrst_con[2]; 87 unsigned int reserved5[14]; 88 unsigned int pmu_autocs_con[2]; 89 }; 90 91 check_member(rv1126_pmucru, pmu_autocs_con[1], 0x244); 92 93 struct rv1126_cru { 94 struct rv1126_pll pll[4]; 95 unsigned int offsetcal_status[4]; 96 unsigned int mode; 97 unsigned int reserved1[27]; 98 unsigned int clksel_con[78]; 99 unsigned int reserved2[18]; 100 unsigned int clkgate_con[25]; 101 unsigned int reserved3[7]; 102 unsigned int softrst_con[15]; 103 unsigned int reserved4[17]; 104 unsigned int ssgtbl[32]; 105 unsigned int glb_cnt_th; 106 unsigned int glb_rst_st; 107 unsigned int glb_srst_fst; 108 unsigned int glb_srst_snd; 109 unsigned int glb_rst_con; 110 unsigned int reserved5[11]; 111 unsigned int sdmmc_con[2]; 112 unsigned int sdio_con[2]; 113 unsigned int emmc_con[2]; 114 unsigned int reserved6[2]; 115 unsigned int gmac_con; 116 unsigned int misc[2]; 117 unsigned int reserved7[45]; 118 unsigned int autocs_con[26]; 119 }; 120 121 check_member(rv1126_cru, autocs_con[25], 0x584); 122 123 struct pll_rate_table { 124 unsigned long rate; 125 unsigned int fbdiv; 126 unsigned int postdiv1; 127 unsigned int refdiv; 128 unsigned int postdiv2; 129 unsigned int dsmpd; 130 unsigned int frac; 131 }; 132 133 struct cpu_rate_table { 134 unsigned long rate; 135 unsigned int aclk_div; 136 unsigned int pclk_div; 137 }; 138 139 #define RV1126_PMU_MODE 0x0 140 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10) 141 #define RV1126_PLL_CON(x) ((x) * 0x4) 142 #define RV1126_MODE_CON 0x90 143 144 enum { 145 /* CRU_PMU_CLK_SEL0_CON */ 146 RTC32K_SEL_SHIFT = 7, 147 RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT, 148 RTC32K_SEL_PMUPVTM = 0, 149 RTC32K_SEL_OSC1_32K, 150 RTC32K_SEL_OSC0_DIV32K, 151 152 /* CRU_PMU_CLK_SEL1_CON */ 153 PCLK_PDPMU_DIV_SHIFT = 0, 154 PCLK_PDPMU_DIV_MASK = 0x1f, 155 156 /* CRU_PMU_CLK_SEL2_CON */ 157 CLK_I2C0_DIV_SHIFT = 0, 158 CLK_I2C0_DIV_MASK = 0x7f, 159 160 /* CRU_PMU_CLK_SEL3_CON */ 161 CLK_I2C2_DIV_SHIFT = 0, 162 CLK_I2C2_DIV_MASK = 0x7f, 163 164 /* CRU_PMU_CLK_SEL6_CON */ 165 CLK_PWM1_SEL_SHIFT = 15, 166 CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT, 167 CLK_PWM1_SEL_XIN24M = 0, 168 CLK_PWM1_SEL_GPLL, 169 CLK_PWM1_DIV_SHIFT = 8, 170 CLK_PWM1_DIV_MASK = 0x7f << CLK_PWM1_DIV_SHIFT, 171 CLK_PWM0_SEL_SHIFT = 7, 172 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, 173 CLK_PWM0_SEL_XIN24M = 0, 174 CLK_PWM0_SEL_GPLL, 175 CLK_PWM0_DIV_SHIFT = 0, 176 CLK_PWM0_DIV_MASK = 0x7f, 177 178 /* CRU_PMU_CLK_SEL9_CON */ 179 CLK_SPI0_SEL_SHIFT = 7, 180 CLK_SPI0_SEL_MASK = 1 << CLK_SPI0_SEL_SHIFT, 181 CLK_SPI0_SEL_GPLL = 0, 182 CLK_SPI0_SEL_XIN24M, 183 CLK_SPI0_DIV_SHIFT = 0, 184 CLK_SPI0_DIV_MASK = 0x7f, 185 186 /* CRU_PMU_CLK_SEL13_CON */ 187 CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16, 188 CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, 189 CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0, 190 CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, 191 192 /* CRU_CLK_SEL0_CON */ 193 CORE_HCLK_DIV_SHIFT = 8, 194 CORE_HCLK_DIV_MASK = 0x1f << CORE_HCLK_DIV_SHIFT, 195 196 /* CRU_CLK_SEL1_CON */ 197 CORE_ACLK_DIV_SHIFT = 4, 198 CORE_ACLK_DIV_MASK = 0xf << CORE_ACLK_DIV_SHIFT, 199 CORE_DBG_DIV_SHIFT = 0, 200 CORE_DBG_DIV_MASK = 0x7, 201 202 /* CRU_CLK_SEL2_CON */ 203 HCLK_PDBUS_SEL_SHIFT = 15, 204 HCLK_PDBUS_SEL_MASK = 1 << HCLK_PDBUS_SEL_SHIFT, 205 HCLK_PDBUS_SEL_GPLL = 0, 206 HCLK_PDBUS_SEL_CPLL, 207 HCLK_PDBUS_DIV_SHIFT = 8, 208 HCLK_PDBUS_DIV_MASK = 0x1f << HCLK_PDBUS_DIV_SHIFT, 209 ACLK_PDBUS_SEL_SHIFT = 6, 210 ACLK_PDBUS_SEL_MASK = 0x3 << ACLK_PDBUS_SEL_SHIFT, 211 ACLK_PDBUS_SEL_GPLL = 0, 212 ACLK_PDBUS_SEL_CPLL, 213 ACLK_PDBUS_SEL_DPLL, 214 ACLK_PDBUS_DIV_SHIFT = 0, 215 ACLK_PDBUS_DIV_MASK = 0x1f, 216 217 /* CRU_CLK_SEL3_CON */ 218 CLK_SCR1_SEL_SHIFT = 15, 219 CLK_SCR1_SEL_MASK = 1 << CLK_SCR1_SEL_SHIFT, 220 CLK_SCR1_SEL_GPLL = 0, 221 CLK_SCR1_SEL_CPLL, 222 CLK_SCR1_DIV_SHIFT = 8, 223 CLK_SCR1_DIV_MASK = 0x1f << CLK_SCR1_DIV_SHIFT, 224 PCLK_PDBUS_SEL_SHIFT = 7, 225 PCLK_PDBUS_SEL_MASK = 1 << PCLK_PDBUS_SEL_SHIFT, 226 PCLK_PDBUS_SEL_GPLL = 0, 227 PCLK_PDBUS_SEL_CPLL, 228 PCLK_PDBUS_DIV_SHIFT = 0, 229 PCLK_PDBUS_DIV_MASK = 0x1f, 230 231 /* CRU_CLK_SEL4_CON */ 232 ACLK_CRYPTO_SEL_SHIFT = 7, 233 ACLK_CRYPTO_SEL_MASK = 1 << ACLK_CRYPTO_SEL_SHIFT, 234 ACLK_CRYPTO_SEL_GPLL = 0, 235 ACLK_CRYPTO_SEL_CPLL, 236 ACLK_CRYPTO_DIV_SHIFT = 0, 237 ACLK_CRYPTO_DIV_MASK = 0x1f, 238 239 /* CRU_CLK_SEL5_CON */ 240 CLK_I2C3_DIV_SHIFT = 8, 241 CLK_I2C3_DIV_MASK = 0x7f << CLK_I2C3_DIV_SHIFT, 242 CLK_I2C1_DIV_SHIFT = 0, 243 CLK_I2C1_DIV_MASK = 0x7f, 244 245 /* CRU_CLK_SEL6_CON */ 246 CLK_I2C5_DIV_SHIFT = 8, 247 CLK_I2C5_DIV_MASK = 0x7f << CLK_I2C5_DIV_SHIFT, 248 CLK_I2C4_DIV_SHIFT = 0, 249 CLK_I2C4_DIV_MASK = 0x7f, 250 251 /* CRU_CLK_SEL7_CON */ 252 CLK_CRYPTO_PKA_SEL_SHIFT = 15, 253 CLK_CRYPTO_PKA_SEL_MASK = 1 << CLK_CRYPTO_PKA_SEL_SHIFT, 254 CLK_CRYPTO_PKA_SEL_GPLL = 0, 255 CLK_CRYPTO_PKA_SEL_CPLL, 256 CLK_CRYPTO_PKA_DIV_SHIFT = 8, 257 CLK_CRYPTO_PKA_DIV_MASK = 0x1f << CLK_CRYPTO_PKA_DIV_SHIFT, 258 CLK_CRYPTO_CORE_SEL_SHIFT = 7, 259 CLK_CRYPTO_CORE_SEL_MASK = 1 << CLK_CRYPTO_CORE_SEL_SHIFT, 260 CLK_CRYPTO_CORE_SEL_GPLL = 0, 261 CLK_CRYPTO_CORE_SEL_CPLL, 262 CLK_CRYPTO_CORE_DIV_SHIFT = 0, 263 CLK_CRYPTO_CORE_DIV_MASK = 0x1f, 264 265 /* CRU_CLK_SEL8_CON */ 266 CLK_SPI1_SEL_SHIFT = 8, 267 CLK_SPI1_SEL_MASK = 1 << CLK_SPI1_SEL_SHIFT, 268 CLK_SPI1_SEL_GPLL = 0, 269 CLK_SPI1_SEL_XIN24M, 270 CLK_SPI1_DIV_SHIFT = 0, 271 CLK_SPI1_DIV_MASK = 0x7f, 272 273 /* CRU_CLK_SEL9_CON */ 274 CLK_PWM2_SEL_SHIFT = 15, 275 CLK_PWM2_SEL_MASK = 1 << CLK_PWM2_SEL_SHIFT, 276 CLK_PWM2_SEL_XIN24M = 0, 277 CLK_PWM2_SEL_GPLL, 278 CLK_PWM2_DIV_SHIFT = 8, 279 CLK_PWM2_DIV_MASK = 0x7f << CLK_PWM2_DIV_SHIFT, 280 281 /* CRU_CLK_SEL20_CON */ 282 CLK_SARADC_DIV_SHIFT = 0, 283 CLK_SARADC_DIV_MASK = 0x7ff, 284 285 /* CRU_CLK_SEL26_CON */ 286 HCLK_PDAUDIO_DIV_SHIFT = 0, 287 HCLK_PDAUDIO_DIV_MASK = 0x1f, 288 289 /* CRU_CLK_SEL45_CON */ 290 ACLK_PDVO_SEL_SHIFT = 7, 291 ACLK_PDVO_SEL_MASK = 1 << ACLK_PDVO_SEL_SHIFT, 292 ACLK_PDVO_SEL_GPLL = 0, 293 ACLK_PDVO_SEL_CPLL, 294 ACLK_PDVO_DIV_SHIFT = 0, 295 ACLK_PDVO_DIV_MASK = 0x1f, 296 297 /* CRU_CLK_SEL47_CON */ 298 DCLK_VOP_SEL_SHIFT = 8, 299 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 300 DCLK_VOP_SEL_GPLL = 0, 301 DCLK_VOP_SEL_CPLL, 302 DCLK_VOP_DIV_SHIFT = 0, 303 DCLK_VOP_DIV_MASK = 0xff, 304 305 /* CRU_CLK_SEL53_CON */ 306 HCLK_PDPHP_DIV_SHIFT = 8, 307 HCLK_PDPHP_DIV_MASK = 0x1f << HCLK_PDPHP_DIV_SHIFT, 308 ACLK_PDPHP_SEL_SHIFT = 7, 309 ACLK_PDPHP_SEL_MASK = 1 << ACLK_PDPHP_SEL_SHIFT, 310 ACLK_PDPHP_SEL_GPLL = 0, 311 ACLK_PDPHP_SEL_CPLL, 312 ACLK_PDPHP_DIV_SHIFT = 0, 313 ACLK_PDPHP_DIV_MASK = 0x1f, 314 315 /* CRU_CLK_SEL57_CON */ 316 EMMC_SEL_SHIFT = 14, 317 EMMC_SEL_MASK = 0x3 << EMMC_SEL_SHIFT, 318 EMMC_SEL_GPLL = 0, 319 EMMC_SEL_CPLL, 320 EMMC_SEL_XIN24M, 321 EMMC_DIV_SHIFT = 0, 322 EMMC_DIV_MASK = 0xff, 323 324 /* CRU_CLK_SEL58_CON */ 325 SCLK_SFC_SEL_SHIFT = 15, 326 SCLK_SFC_SEL_MASK = 0x1 << SCLK_SFC_SEL_SHIFT, 327 SCLK_SFC_SEL_CPLL = 0, 328 SCLK_SFC_SEL_GPLL, 329 SCLK_SFC_DIV_SHIFT = 0, 330 SCLK_SFC_DIV_MASK = 0xff, 331 332 /* CRU_CLK_SEL59_CON */ 333 CLK_NANDC_SEL_SHIFT = 15, 334 CLK_NANDC_SEL_MASK = 0x1 << CLK_NANDC_SEL_SHIFT, 335 CLK_NANDC_SEL_GPLL = 0, 336 CLK_NANDC_SEL_CPLL, 337 CLK_NANDC_DIV_SHIFT = 0, 338 CLK_NANDC_DIV_MASK = 0xff, 339 340 /* CRU_GMAC_CON */ 341 GMAC_SRC_M1_SEL_SHIFT = 5, 342 GMAC_SRC_M1_SEL_MASK = 0x1 << GMAC_SRC_M1_SEL_SHIFT, 343 GMAC_SRC_M1_SEL_INT = 0, 344 GMAC_SRC_M1_SEL_EXT, 345 GMAC_SRC_M0_SEL_SHIFT = 0, 346 GMAC_SRC_M0_SEL_MASK = 0x1, 347 GMAC_SRC_M0_SEL_INT = 0, 348 GMAC_SRC_M0_SEL_EXT, 349 350 /* GRF_IOFUNC_CON1 */ 351 GMAC_SRC_SEL_SHIFT = 12, 352 GMAC_SRC_SEL_MASK = 1 < GMAC_SRC_SEL_SHIFT, 353 GMAC_SRC_SEL_M0 = 0, 354 GMAC_SRC_SEL_M1, 355 }; 356 #endif 357