feat(fdts): add STM32MP1 fw-config DT files

Create all boards fw-config DT files. They all include a generic
stm32mp15-fw-config.dtsi.

Change-Id: Ib9ac8a59e93e01365001b0d11fee41f7c507c08e
Signed-of

feat(fdts): add STM32MP1 fw-config DT files

Create all boards fw-config DT files. They all include a generic
stm32mp15-fw-config.dtsi.

Change-Id: Ib9ac8a59e93e01365001b0d11fee41f7c507c08e
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge "feat(gic600ae): introduce support for Fault Management Unit" into integration

docs(ff-a): fix specification naming

Rename the FF-A specification to:
Arm Firmware Framework for Arm A-profile

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4f9d29409d048e7a49

docs(ff-a): fix specification naming

Rename the FF-A specification to:
Arm Firmware Framework for Arm A-profile

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4f9d29409d048e7a49832b95d39d2583c1fb5792

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Merge "feat(fvp): enable external SP images in BL2 config" into integration

refactor(plat/st): updates for OP-TEE

Protect BL32 (SP_min) with MMU if OP-TEE is not used.
Validate OP-TEE header with optee_header_is_valid().
Use default values in bl2_mem_params_descs[]. They wi

refactor(plat/st): updates for OP-TEE

Protect BL32 (SP_min) with MMU if OP-TEE is not used.
Validate OP-TEE header with optee_header_is_valid().
Use default values in bl2_mem_params_descs[]. They will be overwritten
in bl2_plat_handle_post_image_load() if OP-TEE is used.

Change-Id: I8614f3a17caa827561614d0f25f30ee90c4ec3fe
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(lib/optee): introduce optee_header_is_valid()

This new function optee_header_is_valid() allows platform to know
whether OP-TEE OS is loaded from multi-image (using OP-TEE header
image as BL32_I

feat(lib/optee): introduce optee_header_is_valid()

This new function optee_header_is_valid() allows platform to know
whether OP-TEE OS is loaded from multi-image (using OP-TEE header
image as BL32_IMAGE_ID) or from a single OP-TEE binary image.
The function tee_validate_header() is reworked to return a boolean,
and is now silent.

Change-Id: Idc7dde091f2ada8898f40d02e68c3834ca39d8e8
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge "feat(board/rdn2): add tzc master source ids for soc dma" into integration

Merge changes from topic "erratas" into integration

* changes:
errata: workaround for Neoverse N2 erratum 2138956
errata: workaround for Neoverse N2 erratum 2189731
errata: workaround for Cort

Merge changes from topic "erratas" into integration

* changes:
errata: workaround for Neoverse N2 erratum 2138956
errata: workaround for Neoverse N2 erratum 2189731
errata: workaround for Cortex-A710 erratum 2017096
errata: workaround for Cortex-A710 erratum 2055002

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errata: workaround for Neoverse N2 erratum 2138956

Neoverse N2 erratum 2138956 is a Cat B erratum that applies to
revision r0p0 and is still open. This erratum can be avoided by
inserting a sequence

errata: workaround for Neoverse N2 erratum 2138956

Neoverse N2 erratum 2138956 is a Cat B erratum that applies to
revision r0p0 and is still open. This erratum can be avoided by
inserting a sequence of 16 DMB ST instructions prior to WFI or WFE.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I1aac87b3075992f875451e4767b21857f596d0b2

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errata: workaround for Neoverse N2 erratum 2189731

Neoverse N2 erratum 2189731 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR5_EL1[44] to 1 whi

errata: workaround for Neoverse N2 erratum 2189731

Neoverse N2 erratum 2189731 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR5_EL1[44] to 1 which will cause the CPP instruction to
invalidate the hardware prefetcher state trained from any EL.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Iddc6a59adf9fa3cab560c46f2133e1f5a8b3ad03

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errata: workaround for Cortex-A710 erratum 2017096

Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1

errata: workaround for Cortex-A710 erratum 2017096

Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3

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errata: workaround for Cortex-A710 erratum 2055002

Cortex-A710 erratum 2055002 is a Cat B erratum that applies to
revisions r1p0 & r2p0 and is still open. The workaround is to
set CPUACTLR_EL1[46] t

errata: workaround for Cortex-A710 erratum 2055002

Cortex-A710 erratum 2055002 is a Cat B erratum that applies to
revisions r1p0 & r2p0 and is still open. The workaround is to
set CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r1p0 & r2p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I67be1dce53c4651167d8cee33c116e73b9dafe81

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Merge changes from topic "erratas" into integration

* changes:
errata: workaround for Neoverse N2 erratum 2025414
errata: workaround for Neoverse N2 erratum 2067956

fix(arm_fpga): reserve BL31 memory

Embarrassingly we never told the non-secure world that secure firmware
lives in the first few hundred KBs of DRAM, so any non-secure payload
could happily overwrit

fix(arm_fpga): reserve BL31 memory

Embarrassingly we never told the non-secure world that secure firmware
lives in the first few hundred KBs of DRAM, so any non-secure payload
could happily overwrite TF-A, and we couldn't even blame it.

Advertise the BL31 region in the reserved-memory DT node, so non-secure
world stays out of it.

This fixes Linux booting on FPGAs with less memory than usual.

Change-Id: I7fbe7d42c0b251c0ccc43d7c50ca902013d152ec
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes I3c20611a,Ib1671011,I5eab3f33,Ib149b3ea into integration

* changes:
refactor(plat/nxp): refine api to read SVR register
refactor(plat/nxp): each errata use a seperate source file

Merge changes I3c20611a,Ib1671011,I5eab3f33,Ib149b3ea into integration

* changes:
refactor(plat/nxp): refine api to read SVR register
refactor(plat/nxp): each errata use a seperate source file
refactor(plat/nxp): use a unified errata api
refactor(plat/soc-lx2160): move errata to common directory

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fix(arm_fpga): limit BL31 memory usage

At the moment we specified the BL31 memory limits to 1MB; since we
typically have gigabytes of DRAM, we can be quite generous.

However the default parameters

fix(arm_fpga): limit BL31 memory usage

At the moment we specified the BL31 memory limits to 1MB; since we
typically have gigabytes of DRAM, we can be quite generous.

However the default parameters expect the devicetree binary at
0x80070000, so we should actually make sure we have no code or data
beyond that point.

Limit the ARM FPGA BL31 memory footprint to this available 7*64K region.
We stay within the limit at the moment, with more than half of it
reserved for stacks, so this could be downsized later should we run
into problems.

The PIE addresses stay as they are, since the default addresses do not
apply there anywhere, and the build is broken anyway.

Change-Id: I7768af1a93ff67096f4359fc5f5feb66464bafaa
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(fvp): enable external SP images in BL2 config

Currently the list of SP UUIDs loaded by BL2 is hardcoded in the DT.
This is a problem when building a system with other SPs (e.g. from
Trusted Ser

feat(fvp): enable external SP images in BL2 config

Currently the list of SP UUIDs loaded by BL2 is hardcoded in the DT.
This is a problem when building a system with other SPs (e.g. from
Trusted Services). This commit implements a workaround to enable adding
SP UUIDs to the list at build time.

Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: Iff85d3778596d23d777dec458f131bd7a8647031

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docs: nxp soc-lx2160a based platforms

Addition of documents for platforms based on
NXP SoC LX2160A.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I39ac5a9eb0b668d26301a0a24a1e6bf87f

docs: nxp soc-lx2160a based platforms

Addition of documents for platforms based on
NXP SoC LX2160A.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I39ac5a9eb0b668d26301a0a24a1e6bf87f245f02

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Merge "errata: workaround for Cortex-A78 errata 1952683" into integration

errata: workaround for Neoverse N2 erratum 2025414

Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which

errata: workaround for Neoverse N2 erratum 2025414

Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a

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errata: workaround for Neoverse N2 erratum 2067956

Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force

errata: workaround for Neoverse N2 erratum 2067956

Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r0p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie92d18a379c66675b5c1c50fd0b8dde130848b21

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feat(gic600ae): introduce support for Fault Management Unit

The FMU is part of the GIC Distributor (GICD) component. It implements
the following functionality in GIC-600AE:

* Provides software the

feat(gic600ae): introduce support for Fault Management Unit

The FMU is part of the GIC Distributor (GICD) component. It implements
the following functionality in GIC-600AE:

* Provides software the means to enable or disable a Safety Mechanism
within a GIC block.
* Receives error signaling from all Safety Mechanisms within other GIC
blocks.
* Maintains error records for each GIC block, for software inspection
and provides information on the source of the error.
* Retains error records across functional reset.
* Enables software error recovery testing by providing error injection
capabilities in a Safety Mechanism.

This patch introduces support to enable error detection for all safety
mechanisms provided by the FMU. Platforms are expected to invoke the
initialization function during cold boot.

The support for the FMU is guarded by the GICV3_SUPPORT_GIC600AE_FMU
makefile variable. The default value of this variable is '0'.

Change-Id: I421c3d059624ddefd174cb1140a2d2a2296be0c6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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feat(arm_fpga): support GICv4 images

Up until now we relied on the GICs used in our FPGA images to be GICv3
compliant, without the "direct virtual injection" feature (aka GICv4)
enabled.
To support

feat(arm_fpga): support GICv4 images

Up until now we relied on the GICs used in our FPGA images to be GICv3
compliant, without the "direct virtual injection" feature (aka GICv4)
enabled.
To support newer images which have GICv4 compliant GICs, enable the
newly introduced GICv4 detection code, and use that also when we adjust
the redistributor region size in the devicetree.

This allows the same BL31 image to be used with GICv3 or GICv4 FPGA
images.

Change-Id: I9f6435a6d5150983625efe3650a8b7d1ef11b1d1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(gicv3): detect GICv4 feature at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec

feat(gicv3): detect GICv4 feature at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec or not. This just changes the number of 64K MMIO pages
we expect per redistributor.

To support firmware builds which run on variable systems (emulators,
fast model or FPGAs), let's make this decision at runtime.
The GIC specification provides several architected flags to learn the
size of the MMIO frame per redistributor, we use GICR_TYPER[VLPI] here.

Provide a (static inline) function to return the size of each
redistributor.
We keep the GIC_ENABLE_V4_EXTN build time variable around, but change
its meaning to enable this autodetection code. Systems not defining this
rely on a "pure" GICv3 (as before), but platforms setting it to "1" can
now deal with both configurations.

Change-Id: I9ede4acf058846157a0a9e2ef6103bf07c7655d9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(gicv3): multichip: detect GIC-700 at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the

feat(gicv3): multichip: detect GIC-700 at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the GIC spec or not.
In case of the GIC-600 multichip support we were somewhat abusing that
flag to differentiate between a GIC-700 and GIC-600 implementation
being used in the system.

To avoid a build time dependency on this flag, look at the GICD_IIDR
register and check if the hardware is a GIC-600 or not, to make this
decision at runtime. We then use the values for either GIC-700 or the
GIC-600, respectively.

Change-Id: I8c09ec1cd6fd60d28da879ed55ffef5506f9869d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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