1/* 2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11 12/* Hardware handled coherency */ 13#if HW_ASSISTED_COHERENCY == 0 14#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 15#endif 16 17/* 64-bit only core */ 18#if CTX_INCLUDE_AARCH32_REGS == 1 19#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 20#endif 21 22/* -------------------------------------------------- 23 * Errata Workaround for Neoverse N2 Erratum 2002655. 24 * This applies to revision r0p0 of Neoverse N2. it is still open. 25 * Inputs: 26 * x0: variant[4:7] and revision[0:3] of current cpu. 27 * Shall clobber: x0-x17 28 * -------------------------------------------------- 29 */ 30func errata_n2_2002655_wa 31 /* Check revision. */ 32 mov x17, x30 33 bl check_errata_2002655 34 cbz x0, 1f 35 36 /* Apply instruction patching sequence */ 37 ldr x0,=0x6 38 msr S3_6_c15_c8_0,x0 39 ldr x0,=0xF3A08002 40 msr S3_6_c15_c8_2,x0 41 ldr x0,=0xFFF0F7FE 42 msr S3_6_c15_c8_3,x0 43 ldr x0,=0x40000001003ff 44 msr S3_6_c15_c8_1,x0 45 ldr x0,=0x7 46 msr S3_6_c15_c8_0,x0 47 ldr x0,=0xBF200000 48 msr S3_6_c15_c8_2,x0 49 ldr x0,=0xFFEF0000 50 msr S3_6_c15_c8_3,x0 51 ldr x0,=0x40000001003f3 52 msr S3_6_c15_c8_1,x0 53 isb 541: 55 ret x17 56endfunc errata_n2_2002655_wa 57 58func check_errata_2002655 59 /* Applies to r0p0 */ 60 mov x1, #0x00 61 b cpu_rev_var_ls 62endfunc check_errata_2002655 63 64/* --------------------------------------------------------------- 65 * Errata Workaround for Neoverse N2 Erratum 2067956. 66 * This applies to revision r0p0 of Neoverse N2 and is still open. 67 * Inputs: 68 * x0: variant[4:7] and revision[0:3] of current cpu. 69 * Shall clobber: x0-x17 70 * --------------------------------------------------------------- 71 */ 72func errata_n2_2067956_wa 73 /* Compare x0 against revision r0p0 */ 74 mov x17, x30 75 bl check_errata_2067956 76 cbz x0, 1f 77 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 78 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 79 msr NEOVERSE_N2_CPUACTLR_EL1, x1 801: 81 ret x17 82endfunc errata_n2_2067956_wa 83 84func check_errata_2067956 85 /* Applies to r0p0 */ 86 mov x1, #0x00 87 b cpu_rev_var_ls 88endfunc check_errata_2067956 89 90/* --------------------------------------------------------------- 91 * Errata Workaround for Neoverse N2 Erratum 2025414. 92 * This applies to revision r0p0 of Neoverse N2 and is still open. 93 * Inputs: 94 * x0: variant[4:7] and revision[0:3] of current cpu. 95 * Shall clobber: x0-x17 96 * --------------------------------------------------------------- 97 */ 98func errata_n2_2025414_wa 99 /* Compare x0 against revision r0p0 */ 100 mov x17, x30 101 bl check_errata_2025414 102 cbz x0, 1f 103 mrs x1, NEOVERSE_N2_CPUECTLR_EL1 104 orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 105 msr NEOVERSE_N2_CPUECTLR_EL1, x1 106 1071: 108 ret x17 109endfunc errata_n2_2025414_wa 110 111func check_errata_2025414 112 /* Applies to r0p0 */ 113 mov x1, #0x00 114 b cpu_rev_var_ls 115endfunc check_errata_2025414 116 117/* --------------------------------------------------------------- 118 * Errata Workaround for Neoverse N2 Erratum 2189731. 119 * This applies to revision r0p0 of Neoverse N2 and is still open. 120 * Inputs: 121 * x0: variant[4:7] and revision[0:3] of current cpu. 122 * Shall clobber: x0-x17 123 * --------------------------------------------------------------- 124 */ 125func errata_n2_2189731_wa 126 /* Compare x0 against revision r0p0 */ 127 mov x17, x30 128 bl check_errata_2189731 129 cbz x0, 1f 130 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 131 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 132 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 133 1341: 135 ret x17 136endfunc errata_n2_2189731_wa 137 138func check_errata_2189731 139 /* Applies to r0p0 */ 140 mov x1, #0x00 141 b cpu_rev_var_ls 142endfunc check_errata_2189731 143 144 /* ------------------------------------------- 145 * The CPU Ops reset function for Neoverse N2. 146 * ------------------------------------------- 147 */ 148func neoverse_n2_reset_func 149 mov x19, x30 150 151 /* Check if the PE implements SSBS */ 152 mrs x0, id_aa64pfr1_el1 153 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 154 b.eq 1f 155 156 /* Disable speculative loads */ 157 msr SSBS, xzr 1581: 159 /* Force all cacheable atomic instructions to be near */ 160 mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 161 orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 162 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 163 164#if ERRATA_N2_2067956 165 mov x0, x18 166 bl errata_n2_2067956_wa 167#endif 168 169#if ERRATA_N2_2025414 170 mov x0, x18 171 bl errata_n2_2025414_wa 172#endif 173 174#if ERRATA_N2_2189731 175 mov x0, x18 176 bl errata_n2_2189731_wa 177#endif 178 179#if ENABLE_AMU 180 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 181 mrs x0, cptr_el3 182 orr x0, x0, #TAM_BIT 183 msr cptr_el3, x0 184 185 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 186 mrs x0, cptr_el2 187 orr x0, x0, #TAM_BIT 188 msr cptr_el2, x0 189 190 /* No need to enable the counters as this would be done at el3 exit */ 191#endif 192 193#if NEOVERSE_Nx_EXTERNAL_LLC 194 /* Some systems may have External LLC, core needs to be made aware */ 195 mrs x0, NEOVERSE_N2_CPUECTLR_EL1 196 orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 197 msr NEOVERSE_N2_CPUECTLR_EL1, x0 198#endif 199 200 bl cpu_get_rev_var 201 mov x18, x0 202 203#if ERRATA_N2_2002655 204 mov x0, x18 205 bl errata_n2_2002655_wa 206#endif 207 208 isb 209 ret x19 210endfunc neoverse_n2_reset_func 211 212func neoverse_n2_core_pwr_dwn 213 /* --------------------------------------------------- 214 * Enable CPU power down bit in power control register 215 * No need to do cache maintenance here. 216 * --------------------------------------------------- 217 */ 218 mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 219 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT 220 msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 221 isb 222 ret 223endfunc neoverse_n2_core_pwr_dwn 224 225#if REPORT_ERRATA 226/* 227 * Errata printing function for Neoverse N2 cores. Must follow AAPCS. 228 */ 229func neoverse_n2_errata_report 230 stp x8, x30, [sp, #-16]! 231 232 bl cpu_get_rev_var 233 mov x8, x0 234 235 /* 236 * Report all errata. The revision-variant information is passed to 237 * checking functions of each errata. 238 */ 239 report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 240 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 241 report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 242 report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 243 244 ldp x8, x30, [sp], #16 245 ret 246endfunc neoverse_n2_errata_report 247#endif 248 249 /* --------------------------------------------- 250 * This function provides Neoverse N2 specific 251 * register information for crash reporting. 252 * It needs to return with x6 pointing to 253 * a list of register names in ASCII and 254 * x8 - x15 having values of registers to be 255 * reported. 256 * --------------------------------------------- 257 */ 258.section .rodata.neoverse_n2_regs, "aS" 259neoverse_n2_regs: /* The ASCII list of register names to be reported */ 260 .asciz "cpupwrctlr_el1", "" 261 262func neoverse_n2_cpu_reg_dump 263 adr x6, neoverse_n2_regs 264 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 265 ret 266endfunc neoverse_n2_cpu_reg_dump 267 268declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 269 neoverse_n2_reset_func, \ 270 neoverse_n2_core_pwr_dwn 271