1/* 2 * Copyright (c) 2020, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11 12/* Hardware handled coherency */ 13#if HW_ASSISTED_COHERENCY == 0 14#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 15#endif 16 17/* 64-bit only core */ 18#if CTX_INCLUDE_AARCH32_REGS == 1 19#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 20#endif 21 22/* -------------------------------------------------- 23 * Errata Workaround for Neoverse N2 Erratum 2002655. 24 * This applies to revision r0p0 of Neoverse N2. it is still open. 25 * Inputs: 26 * x0: variant[4:7] and revision[0:3] of current cpu. 27 * Shall clobber: x0-x17 28 * -------------------------------------------------- 29 */ 30func errata_n2_2002655_wa 31 /* Check revision. */ 32 mov x17, x30 33 bl check_errata_2002655 34 cbz x0, 1f 35 36 /* Apply instruction patching sequence */ 37 ldr x0,=0x6 38 msr S3_6_c15_c8_0,x0 39 ldr x0,=0xF3A08002 40 msr S3_6_c15_c8_2,x0 41 ldr x0,=0xFFF0F7FE 42 msr S3_6_c15_c8_3,x0 43 ldr x0,=0x40000001003ff 44 msr S3_6_c15_c8_1,x0 45 ldr x0,=0x7 46 msr S3_6_c15_c8_0,x0 47 ldr x0,=0xBF200000 48 msr S3_6_c15_c8_2,x0 49 ldr x0,=0xFFEF0000 50 msr S3_6_c15_c8_3,x0 51 ldr x0,=0x40000001003f3 52 msr S3_6_c15_c8_1,x0 53 isb 541: 55 ret x17 56endfunc errata_n2_2002655_wa 57 58func check_errata_2002655 59 /* Applies to r0p0 */ 60 mov x1, #0x00 61 b cpu_rev_var_ls 62endfunc check_errata_2002655 63 64/* --------------------------------------------------------------- 65 * Errata Workaround for Neoverse N2 Erratum 2067956. 66 * This applies to revision r0p0 of Neoverse N2 and is still open. 67 * Inputs: 68 * x0: variant[4:7] and revision[0:3] of current cpu. 69 * Shall clobber: x0-x17 70 * --------------------------------------------------------------- 71 */ 72func errata_n2_2067956_wa 73 /* Compare x0 against revision r0p0 */ 74 mov x17, x30 75 bl check_errata_2067956 76 cbz x0, 1f 77 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 78 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 79 msr NEOVERSE_N2_CPUACTLR_EL1, x1 801: 81 ret x17 82endfunc errata_n2_2067956_wa 83 84func check_errata_2067956 85 /* Applies to r0p0 */ 86 mov x1, #0x00 87 b cpu_rev_var_ls 88endfunc check_errata_2067956 89 90 /* ------------------------------------------------- 91 * The CPU Ops reset function for Neoverse N2. 92 * ------------------------------------------------- 93 */ 94func neoverse_n2_reset_func 95 mov x19, x30 96 97 /* Check if the PE implements SSBS */ 98 mrs x0, id_aa64pfr1_el1 99 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 100 b.eq 1f 101 102 /* Disable speculative loads */ 103 msr SSBS, xzr 1041: 105 /* Force all cacheable atomic instructions to be near */ 106 mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 107 orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 108 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 109 110#if ERRATA_N2_2067956 111 mov x0, x18 112 bl errata_n2_2067956_wa 113#endif 114 115#if ENABLE_AMU 116 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 117 mrs x0, cptr_el3 118 orr x0, x0, #TAM_BIT 119 msr cptr_el3, x0 120 121 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 122 mrs x0, cptr_el2 123 orr x0, x0, #TAM_BIT 124 msr cptr_el2, x0 125 126 /* No need to enable the counters as this would be done at el3 exit */ 127#endif 128 129#if NEOVERSE_Nx_EXTERNAL_LLC 130 /* Some systems may have External LLC, core needs to be made aware */ 131 mrs x0, NEOVERSE_N2_CPUECTLR_EL1 132 orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 133 msr NEOVERSE_N2_CPUECTLR_EL1, x0 134#endif 135 136 bl cpu_get_rev_var 137 mov x18, x0 138 139#if ERRATA_N2_2002655 140 mov x0, x18 141 bl errata_n2_2002655_wa 142#endif 143 144 isb 145 ret x19 146endfunc neoverse_n2_reset_func 147 148func neoverse_n2_core_pwr_dwn 149 /* --------------------------------------------- 150 * Enable CPU power down bit in power control register 151 * No need to do cache maintenance here. 152 * --------------------------------------------- 153 */ 154 mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 155 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT 156 msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 157 isb 158 ret 159endfunc neoverse_n2_core_pwr_dwn 160 161#if REPORT_ERRATA 162/* 163 * Errata printing function for Neoverse N2 cores. Must follow AAPCS. 164 */ 165func neoverse_n2_errata_report 166 stp x8, x30, [sp, #-16]! 167 168 bl cpu_get_rev_var 169 mov x8, x0 170 171 /* 172 * Report all errata. The revision-variant information is passed to 173 * checking functions of each errata. 174 */ 175 report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 176 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 177 178 ldp x8, x30, [sp], #16 179 ret 180endfunc neoverse_n2_errata_report 181#endif 182 183 /* --------------------------------------------- 184 * This function provides Neoverse N2 specific 185 * register information for crash reporting. 186 * It needs to return with x6 pointing to 187 * a list of register names in ASCII and 188 * x8 - x15 having values of registers to be 189 * reported. 190 * --------------------------------------------- 191 */ 192.section .rodata.neoverse_n2_regs, "aS" 193neoverse_n2_regs: /* The ASCII list of register names to be reported */ 194 .asciz "cpupwrctlr_el1", "" 195 196func neoverse_n2_cpu_reg_dump 197 adr x6, neoverse_n2_regs 198 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 199 ret 200endfunc neoverse_n2_cpu_reg_dump 201 202declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 203 neoverse_n2_reset_func, \ 204 neoverse_n2_core_pwr_dwn 205