1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32.. _arm_cpu_macros_errata_workarounds: 33 34CPU Errata Workarounds 35---------------------- 36 37TF-A exports a series of build flags which control the errata workarounds that 38are applied to each CPU by the reset handler. The errata details can be found 39in the CPU specific errata documents published by Arm: 40 41- `Cortex-A53 MPCore Software Developers Errata Notice`_ 42- `Cortex-A57 MPCore Software Developers Errata Notice`_ 43- `Cortex-A72 MPCore Software Developers Errata Notice`_ 44 45The errata workarounds are implemented for a particular revision or a set of 46processor revisions. This is checked by the reset handler at runtime. Each 47errata workaround is identified by its ``ID`` as specified in the processor's 48errata notice document. The format of the define used to enable/disable the 49errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 50is for example ``A57`` for the ``Cortex_A57`` CPU. 51 52Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to 53write errata workaround functions. 54 55All workarounds are disabled by default. The platform is responsible for 56enabling these workarounds according to its requirement by defining the 57errata workaround build flags in the platform specific makefile. In case 58these workarounds are enabled for the wrong CPU revision then the errata 59workaround is not applied. In the DEBUG build, this is indicated by 60printing a warning to the crash console. 61 62In the current implementation, a platform which has more than 1 variant 63with different revisions of a processor has no runtime mechanism available 64for it to specify which errata workarounds should be enabled or not. 65 66The value of the build flags is 0 by default, that is, disabled. A value of 1 67will enable it. 68 69For Cortex-A9, the following errata build flags are defined : 70 71- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 72 CPU. This needs to be enabled for all revisions of the CPU. 73 74For Cortex-A15, the following errata build flags are defined : 75 76- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 77 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 78 79- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 80 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 81 82For Cortex-A17, the following errata build flags are defined : 83 84- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 85 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 86 87- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 88 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 89 90For Cortex-A35, the following errata build flags are defined : 91 92- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 93 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 94 95For Cortex-A53, the following errata build flags are defined : 96 97- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 98 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 99 100- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 101 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 102 103- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 104 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 105 106- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 107 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 108 109- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 110 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 111 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 112 sections. 113 114- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 115 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 116 r0p4 and onwards, this errata is enabled by default in hardware. 117 118- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 119 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 120 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 121 which are 4kB aligned. 122 123- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 124 CPUs. Though the erratum is present in every revision of the CPU, 125 this workaround is only applied to CPUs from r0p3 onwards, which feature 126 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 127 Earlier revisions of the CPU have other errata which require the same 128 workaround in software, so they should be covered anyway. 129 130- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 131 revisions of Cortex-A53 CPU. 132 133For Cortex-A55, the following errata build flags are defined : 134 135- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 136 CPU. This needs to be enabled only for revision r0p0 of the CPU. 137 138- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 139 CPU. This needs to be enabled only for revision r0p0 of the CPU. 140 141- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 142 CPU. This needs to be enabled only for revision r0p0 of the CPU. 143 144- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 145 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 146 147- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 148 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 149 150- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 151 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 152 153- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 154 revisions of Cortex-A55 CPU. 155 156For Cortex-A57, the following errata build flags are defined : 157 158- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 159 CPU. This needs to be enabled only for revision r0p0 of the CPU. 160 161- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 162 CPU. This needs to be enabled only for revision r0p0 of the CPU. 163 164- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 165 CPU. This needs to be enabled only for revision r0p0 of the CPU. 166 167- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 168 CPU. This needs to be enabled only for revision r0p0 of the CPU. 169 170- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 171 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 172 173- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 174 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 175 176- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 177 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 178 179- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 180 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 181 182- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 183 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 184 185- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 186 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 187 188- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 189 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 190 191- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 192 revisions of Cortex-A57 CPU. 193 194For Cortex-A72, the following errata build flags are defined : 195 196- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 197 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 198 199- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 200 revisions of Cortex-A72 CPU. 201 202For Cortex-A73, the following errata build flags are defined : 203 204- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 205 CPU. This needs to be enabled only for revision r0p0 of the CPU. 206 207- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 208 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 209 210For Cortex-A75, the following errata build flags are defined : 211 212- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 213 CPU. This needs to be enabled only for revision r0p0 of the CPU. 214 215- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 216 CPU. This needs to be enabled only for revision r0p0 of the CPU. 217 218For Cortex-A76, the following errata build flags are defined : 219 220- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 221 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 222 223- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 224 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 225 226- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 227 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 228 229- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 230 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 231 232- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 233 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 234 235- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 236 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 237 238- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 239 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 240 241- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 242 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 243 244- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 245 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 246 limitation of errata framework this errata is applied to all revisions 247 of Cortex-A76 CPU. 248 249- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 250 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 251 252- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 253 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 254 255For Cortex-A77, the following errata build flags are defined : 256 257- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 258 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 259 260- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 261 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 262 263- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 264 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 265 266- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 267 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 268 269For Cortex-A78, the following errata build flags are defined : 270 271- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 272 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 273 274- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 275 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 276 277- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 278 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 279 issue but there is no workaround for that revision. 280 281- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 282 CPU. This needs to be enabled for revisions r0p0 and r1p0. 283 284For Cortex-A78 AE, the following errata build flags are defined : 285 286- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78 287 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is 288 still open. 289 290- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to Cortex-A78 291 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is 292 still open. 293 294For Neoverse N1, the following errata build flags are defined : 295 296- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 297 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 298 299- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 300 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 301 302- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 303 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 304 305- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 306 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 307 308- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 309 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 310 311- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 312 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 313 314- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 315 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 316 317- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 318 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 319 320- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 321 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 322 323- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 324 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 325 326- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 327 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 328 329- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 330 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 331 332- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 333 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 334 revisions r0p0, r1p0, and r2p0 there is no workaround. 335 336For Neoverse N2, the following errata build flags are defined : 337 338- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 339 CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open. 340 341For Neoverse V1, the following errata build flags are defined : 342 343- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 344 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 345 in r1p1. 346 347- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 348 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 349 in r1p1. 350 351- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 352 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 353 in r1p1. 354 355- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 356 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 357 358- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 359 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 360 CPU. 361 362- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 363 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 364 issue is present in r0p0 as well but there is no workaround for that 365 revision. It is still open. 366 367- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 368 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 369 CPU. It is still open. 370 371For Cortex-A710, the following errata build flags are defined : 372 373- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 374 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 375 r2p0 of the CPU. It is still open. 376 377- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 378 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 379 r2p0 of the CPU. It is still open. 380 381- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 382 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 383 and is still open. 384 385- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 386 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 387 of the CPU and is still open. 388 389 390For Neoverse N2, the following errata build flags are defined : 391 392- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 393 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 394 395- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 396 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 397 398DSU Errata Workarounds 399---------------------- 400 401Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 402Shared Unit) errata. The DSU errata details can be found in the respective Arm 403documentation: 404 405- `Arm DSU Software Developers Errata Notice`_. 406 407Each erratum is identified by an ``ID``, as defined in the DSU errata notice 408document. Thus, the build flags which enable/disable the errata workarounds 409have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 410of DSU errata workarounds are similar to `CPU errata workarounds`_. 411 412For DSU errata, the following build flags are defined: 413 414- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 415 affected DSU configurations. This errata applies only for those DSUs that 416 revision is r0p0 (on r0p1 it is fixed). However, please note that this 417 workaround results in increased DSU power consumption on idle. 418 419- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 420 affected DSU configurations. This errata applies only for those DSUs that 421 contain the ACP interface **and** the DSU revision is older than r2p0 (on 422 r2p0 it is fixed). However, please note that this workaround results in 423 increased DSU power consumption on idle. 424 425CPU Specific optimizations 426-------------------------- 427 428This section describes some of the optimizations allowed by the CPU micro 429architecture that can be enabled by the platform as desired. 430 431- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 432 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 433 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 434 of the L2 by set/way flushes any dirty lines from the L1 as well. This 435 is a known safe deviation from the Cortex-A57 TRM defined power down 436 sequence. Each Cortex-A57 based platform must make its own decision on 437 whether to use the optimization. 438 439- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 440 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 441 in a way most programmers expect, and will most probably result in a 442 significant speed degradation to any code that employs them. The Armv8-A 443 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 444 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 445 flag enforces this behaviour. This needs to be enabled only for revisions 446 <= r0p3 of the CPU and is enabled by default. 447 448- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 449 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 450 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 451 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 452 `Cortex-A57 Software Optimization Guide`_. 453 454- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 455 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 456 this bit only if their memory system meets the requirement that cache 457 line fill requests from the Cortex-A57 processor are atomic. Each 458 Cortex-A57 based platform must make its own decision on whether to use 459 the optimization. This flag is disabled by default. 460 461- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 462 level cache(LLC) is present in the system, and that the DataSource field 463 on the master CHI interface indicates when data is returned from the LLC. 464 This is used to control how the LL_CACHE* PMU events count. 465 Default value is 0 (Disabled). 466 467-------------- 468 469*Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.* 470 471.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 472.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 473.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html 474.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html 475.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html 476.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf 477.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html 478