Merge changes from topic "st_fip_fconf" into integration

* changes:
refactor(plat/st): use TZC400 bindings
feat(dt-bindings): add STM32MP1 TZC400 bindings

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): manage io_policies with FCONF
feat(fdts): add IO policies for STM32MP1

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): use FCONF to configure platform
feat(fdts): add STM32MP1 fw-config DT files

Merge "feat(plat/st): improve FIP image loading from MMC" into integration

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): use FIP to load images
refactor(plat/st): updates for OP-TEE
feat(lib/optee): introduce optee_header_is_valid

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): use FIP to load images
refactor(plat/st): updates for OP-TEE
feat(lib/optee): introduce optee_header_is_valid()

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refactor(spmd): boot interface and pass core id

This change refactors the SPMD to setup SPMC CPU contexts once and early
from spmd_spmc_init (single call to cm_setup_context rather than on each
and

refactor(spmd): boot interface and pass core id

This change refactors the SPMD to setup SPMC CPU contexts once and early
from spmd_spmc_init (single call to cm_setup_context rather than on each
and every warm boot).
Pass the core linear ID through a GP register as an implementation
defined behavior helping FF-A adoption to legacy TOSes (essentially
when secure virtualization is not used).

A first version of this change was originally submitted by Lukas [1].
Pasting below the original justification:

Our TEE, Kinibi, is used to receive the core linear ID in the x3
register of booting secondary cores.
This patch is necessary to bring up secondary cores with Kinibi as an
SPMC in SEL1.

In Kinibi, the TEE is mostly platform-independent and all platform-
specifics like topology is concentrated in TF-A of our customers.
That is why we don't have the MPIDR - linear ID mapping in Kinibi.
We need the correct linear ID to program the GICv2 target register,
for example in power management case.
It is not needed on GICv3/v4, because of using a fixed mapping from
MPIDR to ICDIPTR/GICD_ITARGETSRn register.

For debug and power management purpose, we also want a unified view to
linear id between Linux and the TEE.
E.g. to disable a core, to see what cores are printing a trace /
an event.

In the past, Kinibi had several other designs, but the complexity was
getting out of control:
* Platform-specific assembler macros in the kernel.
* A per-core SMC from Linux to tell the linear ID after the boot.
* With DynamiQ, it seems SIPs were playing with MPIDR register values,
reusing them between cores and changing them during boot.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/10235

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Lukas Hanel <lukas.hanel@trustonic.com>
Change-Id: Ifa8fa208e9b8eb1642c80b5f7b54152dadafa75e

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fix(docs-contributing.rst): fix formatting for code snippet

This patch will fix the formatting errors concerning code snippet,
lines 245 and 256 respectively.
The code snippet is updated to 'shell'

fix(docs-contributing.rst): fix formatting for code snippet

This patch will fix the formatting errors concerning code snippet,
lines 245 and 256 respectively.
The code snippet is updated to 'shell' to lex it appropriately.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I53aefd81da350b6511e7a97b5fee7b0d6f9dde2d

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Merge "fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode" into integration

fix(plat/marvell/a3k): enable workaround for erratum 1530924

Erratum 1530924 affects Armada 37xx CPU, since it affects all Cortex-A53
revisions from r0p0 to r0p4.

Enable the workaround for this err

fix(plat/marvell/a3k): enable workaround for erratum 1530924

Erratum 1530924 affects Armada 37xx CPU, since it affects all Cortex-A53
revisions from r0p0 to r0p4.

Enable the workaround for this erratum.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I753225040e49e956788d5617cd7ce76d5e6ea8e8

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docs(stm32mp1): update doc for FIP/FCONF

Describe the boot using FIP, and how to compile it.
The STM32IMAGE boot chain is still available but it is not recommended.
Update the build command lines, f

docs(stm32mp1): update doc for FIP/FCONF

Describe the boot using FIP, and how to compile it.
The STM32IMAGE boot chain is still available but it is not recommended.
Update the build command lines, for FIP.
The memory mapping is also updated.

Change-Id: I2b1e0df5500b6213d33dc558b0e0da38340a4d79
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): add a new DDR firewall management

Based on FCONF framework, define DDR firewall regions
from firmware config file instead of static defines.

Change-Id: I471e15410ca286d9079a86e3dc347

feat(plat/st): add a new DDR firewall management

Based on FCONF framework, define DDR firewall regions
from firmware config file instead of static defines.

Change-Id: I471e15410ca286d9079a86e3dc3474f66d37b5ab
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(tzc400): update filters by region

Add a new function that allows to enable or disabled filters on
configured regions dynamically. This will avoid the need to
reconfigure the entire attribute an

feat(tzc400): update filters by region

Add a new function that allows to enable or disabled filters on
configured regions dynamically. This will avoid the need to
reconfigure the entire attribute and just manage to
enable/disable filters.

Change-Id: If0937ca755bec6c45d3649718147108459682fff
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge "docs(contribution-guidelines): add coverity build configuration section" into integration

Merge changes from topic "advk-serror" into integration

* changes:
fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default
fix(plat/marvell/a3k): update information about PCIe abort hack

docs(contribution-guidelines): add coverity build configuration section

Added a sub-section in the "Processes and Policies" chapter under
Contributor's guide on how to add new build configurations w

docs(contribution-guidelines): add coverity build configuration section

Added a sub-section in the "Processes and Policies" chapter under
Contributor's guide on how to add new build configurations when new
source files are added to the TF-A repository. This will help the patch
contributor to update their files to get analysed by Coverity Scan.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I71f410a061028f89bd0e984e48e61e5935616d71

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fix(plat/qti/sc7180): qti smc addition

Adding QTI SIP SMC CALL to detect qti platform supporting ARM 64 SMC
calls or not.

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I323132

fix(plat/qti/sc7180): qti smc addition

Adding QTI SIP SMC CALL to detect qti platform supporting ARM 64 SMC
calls or not.

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3231325a6ffe5aa69856dd25ac2c0a2004484e4b

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Merge changes I0ae8a6ea,I0b4fc83e into integration

* changes:
feat(tc): Enable SVE for both secure and non-secure world
feat(tc): populate HW_CONFIG in BL31

feat(tc): Enable SVE for both secure and non-secure world

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I0ae8a6ea3245373a17af76c9b7dc3f38f3711091

feat(tc): populate HW_CONFIG in BL31

BL2 passes FW_CONFIG to BL31 which contains information
about different DTBs present. BL31 then uses FW_CONFIG
to get the base address of HW_CONFIG and populate

feat(tc): populate HW_CONFIG in BL31

BL2 passes FW_CONFIG to BL31 which contains information
about different DTBs present. BL31 then uses FW_CONFIG
to get the base address of HW_CONFIG and populate fconf.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I0b4fc83e6e0a0b9401f692516654eb9a3b037616

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Merge "docs: nxp soc-lx2160a based platforms" into integration

feat(fdts): add firewall regions into STM32MP1 DT

Add the corresponding firewall memory regions
into fw-config device tree.

Change-Id: Ie39b0339f3c42b3dd756354138a872500c64f84c
Signed-off-by: Lione

feat(fdts): add firewall regions into STM32MP1 DT

Add the corresponding firewall memory regions
into fw-config device tree.

Change-Id: Ie39b0339f3c42b3dd756354138a872500c64f84c
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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refactor(plat/st): use TZC400 bindings

This avoids duplicate define of TZC_REGION_NSEC_ALL_ACCESS_RDWR.
And remove the previous TZC400 definitions from stm32mp1_def.h.

Change-Id: I6c72c2a18731f69d8

refactor(plat/st): use TZC400 bindings

This avoids duplicate define of TZC_REGION_NSEC_ALL_ACCESS_RDWR.
And remove the previous TZC400 definitions from stm32mp1_def.h.

Change-Id: I6c72c2a18731f69d855fbce8ce822a21da9364fa
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): manage io_policies with FCONF

Introduced IO policies management through the trusted
boot firmware config device tree for UUID references.

Change-Id: Ibeeabede51b0514ebba26dbbdae58736

feat(plat/st): manage io_policies with FCONF

Introduced IO policies management through the trusted
boot firmware config device tree for UUID references.

Change-Id: Ibeeabede51b0514ebba26dbbdae587363b2aa0a7
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): use FCONF to configure platform

Add required code to support FCONF on STM32MP1 platform.
The new FW_CONFIG DT file will be inside the FIP, and loaded by BL2.
It will be used to config

feat(plat/st): use FCONF to configure platform

Add required code to support FCONF on STM32MP1 platform.
The new FW_CONFIG DT file will be inside the FIP, and loaded by BL2.
It will be used to configure the addresses where to load other binaries.
BL2 should be agnostic of which BL32 is in the FIP (OP-TEE or SP_min),
so optee_utils.c is always compiled, and some OP-TEE flags are removed.

Change-Id: Id957b49b0117864136250bfc416664f815043ada
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): improve FIP image loading from MMC

Instead of using a scratch buffer of 512 bytes, we can directly use the
image address and max size. The mmc_block_dev_spec struct info is then
overw

feat(plat/st): improve FIP image loading from MMC

Instead of using a scratch buffer of 512 bytes, we can directly use the
image address and max size. The mmc_block_dev_spec struct info is then
overwritten for each image with this info, except FW_CONFIG and GPT
table which will still use the scratch buffer.
This allows using multiple blocks read on MMC, and so improves the boot
time.
A cache invalidate is required for the remaining data not used from the
first and last blocks read. It is not required for FW_CONFIG_ID,
as it is in scratch buffer in SYSRAM, and also because bl_mem_params
struct is overwritten in this case. This should also not be done if
the image is not found (OP-TEE extra binaries when using SP_min).

Change-Id: If3ecfdfe35bb9db66284036ca49c4bd1be4fd121
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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