| 27bb509d | 09-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix: use rsvg-convert as the conversion backend" into integration |
| 1fd03dd6 | 08-Aug-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(cpus): revert erroneous use of override_vector_table macro in Cortex-A73" into integration |
| a3919ed0 | 08-Aug-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(fvp): extract core id from mpidr for pwrc operations" into integration |
| 72e8f245 | 08-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "chore: update to use Arm word across TF-A" into integration |
| 995eaa63 | 08-Aug-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "hm/errata-a710" into integration
* changes:
refactor(cpus): convert the Cortex-A710 to use cpu helpers
refactor(cpus): convert Cortex-A710 to use the errata framework
Merge changes from topic "hm/errata-a710" into integration
* changes:
refactor(cpus): convert the Cortex-A710 to use cpu helpers
refactor(cpus): convert Cortex-A710 to use the errata framework
refactor(cpus): reorder Cortex-A710 errata by ascending order
feat(cpus): make revision procedure call optional
show more ...
|
| 4c700c15 | 01-Aug-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: update to use Arm word across TF-A
Align entire TF-A to use Arm in copyright header.
Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.co
chore: update to use Arm word across TF-A
Align entire TF-A to use Arm in copyright header.
Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
show more ...
|
| c399679c | 08-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(stm32mp1): add FWU with boot from NOR-SPI" into integration |
| 1142b38f | 08-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes I2c4e826f,I388e8dcd,I6fd20225 into integration
* changes:
chore(ethos-n): use non blocking soft reset on npu
docs(ethos-n): update build-options.rst
refactor(ethos-n): move build
Merge changes I2c4e826f,I388e8dcd,I6fd20225 into integration
* changes:
chore(ethos-n): use non blocking soft reset on npu
docs(ethos-n): update build-options.rst
refactor(ethos-n): move build flags to ethosn_npu.mk
show more ...
|
| 2c65b79e | 31-Jul-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(versal-net): make pmc ipi channel as secure
Make PMC IPI channel for Versal NET as secure so that NS
systems cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <ja
fix(versal-net): make pmc ipi channel as secure
Make PMC IPI channel for Versal NET as secure so that NS
systems cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I75ba8796859dcb35644f3e144d7dc5926755ef78
show more ...
|
| 96eaafa3 | 31-Jul-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(versal): make pmc ipi channel as secure
Make PMC IPI channel for Versal as secure so that NS systems
cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <jay.buddha
fix(versal): make pmc ipi channel as secure
Make PMC IPI channel for Versal as secure so that NS systems
cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I22148653fa2d27941cb3031ac790892cee0d1796
show more ...
|
| cebb7cc1 | 31-Jul-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(versal-net): add redundant call to avoid glitches
Add redundant macro call to increase security by making
code glitch immune as security operations might be
called with the IPI command.
Signed-
fix(versal-net): add redundant call to avoid glitches
Add redundant macro call to increase security by making
code glitch immune as security operations might be
called with the IPI command.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I84d84cca258b7cd981f62816c51032341e19095c
show more ...
|
| e8efb65a | 31-Jul-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(versal-net): change flag to increase security
Currently security flag is set to SECURE by default and
is changed to NON_SECURE if NS system is detected. In this
case NS system may access secure
fix(versal-net): change flag to increase security
Currently security flag is set to SECURE by default and
is changed to NON_SECURE if NS system is detected. In this
case NS system may access secure system if condition check
gets skipped due to glitches.
So, initialize security_flag to NON_SECURE_FLAG and switch
to SECURE_FLAG if the TrustZone bit is detected to be
in more secure state.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I7af54465bd8744ba97a58c02607631ee23619d47
show more ...
|
| 273cf25c | 19-Jul-2023 |
Zingo Andersen <zingo.andersen@arm.com> |
chore(ethos-n): use non blocking soft reset on npu
Signed-off-by: Zingo Andersen <zingo.andersen@arm.com>
Change-Id: I2c4e826f4bbbcd7c9170d5df2f8088f82ac2da7c |
| 9a0c8125 | 07-Aug-2023 |
Sona Mathew <SonaRebecca.Mathew@arm.com> |
fix(cpus): revert erroneous use of override_vector_table macro in Cortex-A73
override_vector_table does adr, followed by an msr ops.
Accidentally was used here for for adr and mrs op.
Signed-off-by
fix(cpus): revert erroneous use of override_vector_table macro in Cortex-A73
override_vector_table does adr, followed by an msr ops.
Accidentally was used here for for adr and mrs op.
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
Change-Id: I2d3fda12acd097acabbde9b7dcc376d08419e223
show more ...
|
| 7b1e8c1c | 04-May-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
refactor(cpus): convert the Cortex-A710 to use cpu helpers
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I5e928f139c2e9fa91c78947cf6a8bff546f7be05 |
| d16a90d4 | 26-Apr-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
refactor(cpus): convert Cortex-A710 to use the errata framework
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_
refactor(cpus): convert Cortex-A710 to use the errata framework
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame. Testing was
conducted by:
* Building for release with all errata flags enabled and running script
in change 19136 to compare output of objdump for each errata.
* Manual comparison of disassembly of converted functions with non-
converted functions
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I417539ab292f13a4f0949625d2fef6b7792fbd35
show more ...
|
| d25136da | 25-Apr-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
refactor(cpus): reorder Cortex-A710 errata by ascending order
Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definitio
refactor(cpus): reorder Cortex-A710 errata by ascending order
Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.
Change-Id: I4a6ed55d48e91ec914b7a591c6d30da5ce5d915d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
show more ...
|
| 4d22b0e5 | 26-Jun-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
feat(cpus): make revision procedure call optional
For runtime errata, we should avoid generating calls to
`cpu_get_rev_var` unless its necessary. Make the path that generates
this call parameterized
feat(cpus): make revision procedure call optional
For runtime errata, we should avoid generating calls to
`cpu_get_rev_var` unless its necessary. Make the path that generates
this call parameterized, and cache the result in a temporary register to
allow future calls that go down the alternate path to retrieve the cache
CPU revision.
Change-Id: I9882ede76568fbd9a7ccd4caa74eff0c66a7b20e
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
show more ...
|
| ffdf5ea4 | 09-May-2023 |
Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com> |
docs(ethos-n): update build-options.rst
Move documentation related to Arm(R) Ethos(TM)-N NPU driver from
docs/plat/arm/arm-build-options.rst to
docs/getting_started/build-options.rst.
Signed-off-by
docs(ethos-n): update build-options.rst
Move documentation related to Arm(R) Ethos(TM)-N NPU driver from
docs/plat/arm/arm-build-options.rst to
docs/getting_started/build-options.rst.
Signed-off-by: Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com>
Change-Id: I388e8dcd3950b11bc3305f5e6396ee2e49c04493
show more ...
|
| 352366ed | 08-May-2023 |
Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com> |
refactor(ethos-n): move build flags to ethosn_npu.mk
The build flags to enable the Arm(R) Ethos(TM)-N NPU driver are in arm
platform specific make files i.e. plat/arm/common/arm_common.mk. These
fla
refactor(ethos-n): move build flags to ethosn_npu.mk
The build flags to enable the Arm(R) Ethos(TM)-N NPU driver are in arm
platform specific make files i.e. plat/arm/common/arm_common.mk. These
flags are renamed and moved to ethosn_npu.mk. Other source and make
files are changed to reflect the changes in these flags.
Signed-off-by: Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com>
Change-Id: I6fd20225343c574cb5ac1f0f32ff2fc28ef37ea6
show more ...
|
| 29ae73e3 | 07-Aug-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "mb/mb-signer-id" into integration
* changes:
feat(qemu): add dummy plat_mboot_measure_key() function
docs(rss): update RSS doc for signer-ID
feat(imx): add dummy 'pla
Merge changes from topic "mb/mb-signer-id" into integration
* changes:
feat(qemu): add dummy plat_mboot_measure_key() function
docs(rss): update RSS doc for signer-ID
feat(imx): add dummy 'plat_mboot_measure_key' function
feat(tc): implement platform function to measure and publish Public Key
feat(auth): measure and publicise the Public Key
feat(fvp): implement platform function to measure and publish Public Key
feat(fvp): add public key-OID information in RSS metadata structure
feat(auth): add explicit entries for key OIDs
feat(rss): set the signer-ID in the RSS metadata
feat(auth): create a zero-OID for Subject Public Key
docs: add details about plat_mboot_measure_key function
feat(measured-boot): introduce platform function to measure and publish Public Key
show more ...
|
| 70bc7444 | 01-Aug-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
fix(fvp): extract core id from mpidr for pwrc operations
The ID field populated for every FVP PWRC register interface must be
computed from the affinity level values from MPIDR.
Signed-off-by: Madh
fix(fvp): extract core id from mpidr for pwrc operations
The ID field populated for every FVP PWRC register interface must be
computed from the affinity level values from MPIDR.
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: If1474fd25704911f8f717dafb419a0734b99a4ec
show more ...
|
| 96eb2dc4 | 07-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "chore(xilinx): reorder headers in assembly files" into integration |
| 8a26478f | 07-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "chore(xilinx): correct kernel doc warnings for missing functions" into integration |
| 16f19ed1 | 07-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "xlnx_zynmp_tsp" into integration
* changes:
chore(zynqmp): remove unused configuration from TSP
fix(zynqmp): resolve runtime error in TSP |